drivers/i2c/busses/i2c-mpc.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
   4
   5  * This is a combined i2c adapter and algorithm driver for the
   6  * MPC107/Tsi107 PowerPC northbridge and processors that include
   7  * the same I2C unit (8240, 8245, 85xx).
   8  *
   9  * Release 0.8
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/init.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_i2c.h>
  22 #include <linux/slab.h>
  23
  24 #include <linux/io.h>
  25 #include <linux/fsl_devices.h>
  26 #include <linux/i2c.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29
  30 #include <asm/mpc52xx.h>
  31 #include <sysdev/fsl_soc.h>
  32
  33 #define DRV_NAME "mpc-i2c"
  34
  35 #define MPC_I2C_CLOCK_LEGACY   0
  36 #define MPC_I2C_CLOCK_PRESERVE (~0U)
  37
  38 #define MPC_I2C_FDR   0x04
  39 #define MPC_I2C_CR    0x08
  40 #define MPC_I2C_SR    0x0c
  41 #define MPC_I2C_DR    0x10
  42 #define MPC_I2C_DFSRR 0x14
  43
  44 #define CCR_MEN  0x80
  45 #define CCR_MIEN 0x40
  46 #define CCR_MSTA 0x20
  47 #define CCR_MTX  0x10
  48 #define CCR_TXAK 0x08
  49 #define CCR_RSTA 0x04
  50
  51 #define CSR_MCF  0x80
  52 #define CSR_MAAS 0x40
  53 #define CSR_MBB  0x20
  54 #define CSR_MAL  0x10
  55 #define CSR_SRW  0x04
  56 #define CSR_MIF  0x02
  57 #define CSR_RXAK 0x01
  58
  59 struct mpc_i2c {
  60         struct device *dev;
  61         void __iomem *base;
  62         u32 interrupt;
  63         wait_queue_head_t queue;
  64         struct i2c_adapter adap;
  65         int irq;
  66         u32 real_clk;
  67 };
  68
  69 struct mpc_i2c_divider {
  70         u16 divider;
  71         u16 fdr;        /* including dfsrr */
  72 };
  73
  74 struct mpc_i2c_data {
  75         void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
  76                       u32 clock, u32 prescaler);
  77         u32 prescaler;
  78 };
  79
  80 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
  81 {
  82         writeb(x, i2c->base + MPC_I2C_CR);
  83 }
  84
  85 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
  86 {
  87         struct mpc_i2c *i2c = dev_id;
  88         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  89                 /* Read again to allow register to stabilise */
  90                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
  91                 writeb(0, i2c->base + MPC_I2C_SR);
  92                 wake_up(&i2c->queue);
  93         }
  94         return IRQ_HANDLED;
  95 }
  96
  97 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
  98  * the bus, because it wants to send ACK.
  99  * Following sequence of enabling/disabling and sending start/stop generates
 100  * the 9 pulses, so it's all OK.
 101  */
 102 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 103 {
 104         int k;
 105         u32 delay_val = 1000000 / i2c->real_clk + 1;
 106
 107         if (delay_val < 2)
 108                 delay_val = 2;
 109
 110         for (k = 9; k; k--) {
 111                 writeccr(i2c, 0);
 112                 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
 113                 udelay(delay_val);
 114                 writeccr(i2c, CCR_MEN);
 115                 udelay(delay_val << 1);
 116         }
 117 }
 118
 119 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
 120 {
 121         unsigned long orig_jiffies = jiffies;
 122         u32 x;
 123         int result = 0;
 124
 125         if (!i2c->irq) {
 126                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
 127                         schedule();
 128                         if (time_after(jiffies, orig_jiffies + timeout)) {
 129                                 dev_dbg(i2c->dev, "timeout\n");
 130                                 writeccr(i2c, 0);
 131                                 result = -EIO;
 132                                 break;
 133                         }
 134                 }
 135                 x = readb(i2c->base + MPC_I2C_SR);
 136                 writeb(0, i2c->base + MPC_I2C_SR);
 137         } else {
 138                 /* Interrupt mode */
 139                 result = wait_event_timeout(i2c->queue,
 140                         (i2c->interrupt & CSR_MIF), timeout);
 141
 142                 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
 143                         dev_dbg(i2c->dev, "wait timeout\n");
 144                         writeccr(i2c, 0);
 145                         result = -ETIMEDOUT;
 146                 }
 147
 148                 x = i2c->interrupt;
 149                 i2c->interrupt = 0;
 150         }
 151
 152         if (result < 0)
 153                 return result;
 154
 155         if (!(x & CSR_MCF)) {
 156                 dev_dbg(i2c->dev, "unfinished\n");
 157                 return -EIO;
 158         }
 159
 160         if (x & CSR_MAL) {
 161                 dev_dbg(i2c->dev, "MAL\n");
 162                 return -EIO;
 163         }
 164
 165         if (writing && (x & CSR_RXAK)) {
 166                 dev_dbg(i2c->dev, "No RXAK\n");
 167                 /* generate stop */
 168                 writeccr(i2c, CCR_MEN);
 169                 return -EIO;
 170         }
 171         return 0;
 172 }
 173
 174 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
 175 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
 176         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
 177         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
 178         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
 179         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
 180         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
 181         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
 182         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
 183         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
 184         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
 185         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
 186         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
 187         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
 188         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
 189         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
 190         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
 191         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
 192         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
 193         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
 194 };
 195
 196 static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
 197                                           int prescaler, u32 *real_clk)
 198 {
 199         const struct mpc_i2c_divider *div = NULL;
 200         unsigned int pvr = mfspr(SPRN_PVR);
 201         u32 divider;
 202         int i;
 203
 204         if (clock == MPC_I2C_CLOCK_LEGACY) {
 205                 /* see below - default fdr = 0x3f -> div = 2048 */
 206                 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
 207                 return -EINVAL;
 208         }
 209
 210         /* Determine divider value */
 211         divider = mpc5xxx_get_bus_frequency(node) / clock;
 212
 213         /*
 214          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 215          * is equal to or lower than the requested speed.
 216          */
 217         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
 218                 div = &mpc_i2c_dividers_52xx[i];
 219                 /* Old MPC5200 rev A CPUs do not support the high bits */
 220                 if (div->fdr & 0xc0 && pvr == 0x80822011)
 221                         continue;
 222                 if (div->divider >= divider)
 223                         break;
 224         }
 225
 226         *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
 227         return (int)div->fdr;
 228 }
 229
 230 static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
 231                                          struct mpc_i2c *i2c,
 232                                          u32 clock, u32 prescaler)
 233 {
 234         int ret, fdr;
 235
 236         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 237                 dev_dbg(i2c->dev, "using fdr %d\n",
 238                         readb(i2c->base + MPC_I2C_FDR));
 239                 return;
 240         }
 241
 242         ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
 243         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
 244
 245         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 246
 247         if (ret >= 0)
 248                 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
 249                          fdr);
 250 }
 251 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
 252 static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
 253                                          struct mpc_i2c *i2c,
 254                                          u32 clock, u32 prescaler)
 255 {
 256 }
 257 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
 258
 259 #ifdef CONFIG_PPC_MPC512x
 260 static void __devinit mpc_i2c_setup_512x(struct device_node *node,
 261                                          struct mpc_i2c *i2c,
 262                                          u32 clock, u32 prescaler)
 263 {
 264         struct device_node *node_ctrl;
 265         void __iomem *ctrl;
 266         const u32 *pval;
 267         u32 idx;
 268
 269         /* Enable I2C interrupts for mpc5121 */
 270         node_ctrl = of_find_compatible_node(NULL, NULL,
 271                                             "fsl,mpc5121-i2c-ctrl");
 272         if (node_ctrl) {
 273                 ctrl = of_iomap(node_ctrl, 0);
 274                 if (ctrl) {
 275                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
 276                         pval = of_get_property(node, "reg", NULL);
 277                         idx = (*pval & 0xff) / 0x20;
 278                         setbits32(ctrl, 1 << (24 + idx * 2));
 279                         iounmap(ctrl);
 280                 }
 281                 of_node_put(node_ctrl);
 282         }
 283
 284         /* The clock setup for the 52xx works also fine for the 512x */
 285         mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
 286 }
 287 #else /* CONFIG_PPC_MPC512x */
 288 static void __devinit mpc_i2c_setup_512x(struct device_node *node,
 289                                          struct mpc_i2c *i2c,
 290                                          u32 clock, u32 prescaler)
 291 {
 292 }
 293 #endif /* CONFIG_PPC_MPC512x */
 294
 295 #ifdef CONFIG_FSL_SOC
 296 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = {
 297         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
 298         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
 299         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
 300         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
 301         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
 302         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
 303         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
 304         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
 305         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
 306         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
 307         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
 308         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
 309         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
 310         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
 311         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
 312         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
 313         {49152, 0x011e}, {61440, 0x011f}
 314 };
 315
 316 static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
 317 {
 318         struct device_node *node = NULL;
 319         u32 __iomem *reg;
 320         u32 val = 0;
 321
 322         node = of_find_node_by_name(NULL, "global-utilities");
 323         if (node) {
 324                 const u32 *prop = of_get_property(node, "reg", NULL);
 325                 if (prop) {
 326                         /*
 327                          * Map and check POR Device Status Register 2
 328                          * (PORDEVSR2) at 0xE0014
 329                          */
 330                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
 331                         if (!reg)
 332                                 printk(KERN_ERR
 333                                        "Error: couldn't map PORDEVSR2\n");
 334                         else
 335                                 val = in_be32(reg) & 0x00000080; /* sec-cfg */
 336                         iounmap(reg);
 337                 }
 338         }
 339         if (node)
 340                 of_node_put(node);
 341
 342         return val;
 343 }
 344
 345 static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
 346                                           u32 prescaler, u32 *real_clk)
 347 {
 348         const struct mpc_i2c_divider *div = NULL;
 349         u32 divider;
 350         int i;
 351
 352         if (clock == MPC_I2C_CLOCK_LEGACY) {
 353                 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
 354                 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
 355                 return -EINVAL;
 356         }
 357
 358         /* Determine proper divider value */
 359         if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
 360                 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
 361         if (!prescaler)
 362                 prescaler = 1;
 363
 364         divider = fsl_get_sys_freq() / clock / prescaler;
 365
 366         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
 367                  fsl_get_sys_freq(), clock, divider);
 368
 369         /*
 370          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 371          * is equal to or lower than the requested speed.
 372          */
 373         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
 374                 div = &mpc_i2c_dividers_8xxx[i];
 375                 if (div->divider >= divider)
 376                         break;
 377         }
 378
 379         *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
 380         return div ? (int)div->fdr : -EINVAL;
 381 }
 382
 383 static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
 384                                          struct mpc_i2c *i2c,
 385                                          u32 clock, u32 prescaler)
 386 {
 387         int ret, fdr;
 388
 389         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 390                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
 391                         readb(i2c->base + MPC_I2C_DFSRR),
 392                         readb(i2c->base + MPC_I2C_FDR));
 393                 return;
 394         }
 395
 396         ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
 397         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
 398
 399         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 400         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
 401
 402         if (ret >= 0)
 403                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
 404                          i2c->real_clk, fdr >> 8, fdr & 0xff);
 405 }
 406
 407 #else /* !CONFIG_FSL_SOC */
 408 static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
 409                                          struct mpc_i2c *i2c,
 410                                          u32 clock, u32 prescaler)
 411 {
 412 }
 413 #endif /* CONFIG_FSL_SOC */
 414
 415 static void mpc_i2c_start(struct mpc_i2c *i2c)
 416 {
 417         /* Clear arbitration */
 418         writeb(0, i2c->base + MPC_I2C_SR);
 419         /* Start with MEN */
 420         writeccr(i2c, CCR_MEN);
 421 }
 422
 423 static void mpc_i2c_stop(struct mpc_i2c *i2c)
 424 {
 425         writeccr(i2c, CCR_MEN);
 426 }
 427
 428 static int mpc_write(struct mpc_i2c *i2c, int target,
 429                      const u8 *data, int length, int restart)
 430 {
 431         int i, result;
 432         unsigned timeout = i2c->adap.timeout;
 433         u32 flags = restart ? CCR_RSTA : 0;
 434
 435         /* Start as master */
 436         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 437         /* Write target byte */
 438         writeb((target << 1), i2c->base + MPC_I2C_DR);
 439
 440         result = i2c_wait(i2c, timeout, 1);
 441         if (result < 0)
 442                 return result;
 443
 444         for (i = 0; i < length; i++) {
 445                 /* Write data byte */
 446                 writeb(data[i], i2c->base + MPC_I2C_DR);
 447
 448                 result = i2c_wait(i2c, timeout, 1);
 449                 if (result < 0)
 450                         return result;
 451         }
 452
 453         return 0;
 454 }
 455
 456 static int mpc_read(struct mpc_i2c *i2c, int target,
 457                     u8 *data, int length, int restart)
 458 {
 459         unsigned timeout = i2c->adap.timeout;
 460         int i, result;
 461         u32 flags = restart ? CCR_RSTA : 0;
 462
 463         /* Switch to read - restart */
 464         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 465         /* Write target address byte - this time with the read flag set */
 466         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
 467
 468         result = i2c_wait(i2c, timeout, 1);
 469         if (result < 0)
 470                 return result;
 471
 472         if (length) {
 473                 if (length == 1)
 474                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 475                 else
 476                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
 477                 /* Dummy read */
 478                 readb(i2c->base + MPC_I2C_DR);
 479         }
 480
 481         for (i = 0; i < length; i++) {
 482                 result = i2c_wait(i2c, timeout, 0);
 483                 if (result < 0)
 484                         return result;
 485
 486                 /* Generate txack on next to last byte */
 487                 if (i == length - 2)
 488                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 489                 /* Do not generate stop on last byte */
 490                 if (i == length - 1)
 491                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX);
 492                 data[i] = readb(i2c->base + MPC_I2C_DR);
 493         }
 494
 495         return length;
 496 }
 497
 498 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 499 {
 500         struct i2c_msg *pmsg;
 501         int i;
 502         int ret = 0;
 503         unsigned long orig_jiffies = jiffies;
 504         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 505
 506         mpc_i2c_start(i2c);
 507
 508         /* Allow bus up to 1s to become not busy */
 509         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 510                 if (signal_pending(current)) {
 511                         dev_dbg(i2c->dev, "Interrupted\n");
 512                         writeccr(i2c, 0);
 513                         return -EINTR;
 514                 }
 515                 if (time_after(jiffies, orig_jiffies + HZ)) {
 516                         u8 status = readb(i2c->base + MPC_I2C_SR);
 517
 518                         dev_dbg(i2c->dev, "timeout\n");
 519                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
 520                                 writeb(status & ~CSR_MAL,
 521                                        i2c->base + MPC_I2C_SR);
 522                                 mpc_i2c_fixup(i2c);
 523                         }
 524                         return -EIO;
 525                 }
 526                 schedule();
 527         }
 528
 529         for (i = 0; ret >= 0 && i < num; i++) {
 530                 pmsg = &msgs[i];
 531                 dev_dbg(i2c->dev,
 532                         "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
 533                         pmsg->flags & I2C_M_RD ? "read" : "write",
 534                         pmsg->len, pmsg->addr, i + 1, num);
 535                 if (pmsg->flags & I2C_M_RD)
 536                         ret =
 537                             mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 538                 else
 539                         ret =
 540                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 541         }
 542         mpc_i2c_stop(i2c);
 543         return (ret < 0) ? ret : num;
 544 }
 545
 546 static u32 mpc_functionality(struct i2c_adapter *adap)
 547 {
 548         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 549 }
 550
 551 static const struct i2c_algorithm mpc_algo = {
 552         .master_xfer = mpc_xfer,
 553         .functionality = mpc_functionality,
 554 };
 555
 556 static struct i2c_adapter mpc_ops = {
 557         .owner = THIS_MODULE,
 558         .name = "MPC adapter",
 559         .algo = &mpc_algo,
 560         .timeout = HZ,
 561 };
 562
 563 static const struct of_device_id mpc_i2c_of_match[];
 564 static int __devinit fsl_i2c_probe(struct platform_device *op)
 565 {
 566         const struct of_device_id *match;
 567         struct mpc_i2c *i2c;
 568         const u32 *prop;
 569         u32 clock = MPC_I2C_CLOCK_LEGACY;
 570         int result = 0;
 571         int plen;
 572
 573         match = of_match_device(mpc_i2c_of_match, &op->dev);
 574         if (!match)
 575                 return -EINVAL;
 576
 577         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
 578         if (!i2c)
 579                 return -ENOMEM;
 580
 581         i2c->dev = &op->dev; /* for debug and error output */
 582
 583         init_waitqueue_head(&i2c->queue);
 584
 585         i2c->base = of_iomap(op->dev.of_node, 0);
 586         if (!i2c->base) {
 587                 dev_err(i2c->dev, "failed to map controller\n");
 588                 result = -ENOMEM;
 589                 goto fail_map;
 590         }
 591
 592         i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 593         if (i2c->irq) { /* no i2c->irq implies polling */
 594                 result = request_irq(i2c->irq, mpc_i2c_isr,
 595                                      IRQF_SHARED, "i2c-mpc", i2c);
 596                 if (result < 0) {
 597                         dev_err(i2c->dev, "failed to attach interrupt\n");
 598                         goto fail_request;
 599                 }
 600         }
 601
 602         if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) {
 603                 clock = MPC_I2C_CLOCK_PRESERVE;
 604         } else {
 605                 prop = of_get_property(op->dev.of_node, "clock-frequency",
 606                                         &plen);
 607                 if (prop && plen == sizeof(u32))
 608                         clock = *prop;
 609         }
 610
 611         if (match->data) {
 612                 struct mpc_i2c_data *data = match->data;
 613                 data->setup(op->dev.of_node, i2c, clock, data->prescaler);
 614         } else {
 615                 /* Backwards compatibility */
 616                 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
 617                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
 618         }
 619
 620         prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
 621         if (prop && plen == sizeof(u32)) {
 622                 mpc_ops.timeout = *prop * HZ / 1000000;
 623                 if (mpc_ops.timeout < 5)
 624                         mpc_ops.timeout = 5;
 625         }
 626         dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
 627
 628         dev_set_drvdata(&op->dev, i2c);
 629
 630         i2c->adap = mpc_ops;
 631         i2c_set_adapdata(&i2c->adap, i2c);
 632         i2c->adap.dev.parent = &op->dev;
 633         i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
 634
 635         result = i2c_add_adapter(&i2c->adap);
 636         if (result < 0) {
 637                 dev_err(i2c->dev, "failed to add adapter\n");
 638                 goto fail_add;
 639         }
 640         of_i2c_register_devices(&i2c->adap);
 641
 642         return result;
 643
 644  fail_add:
 645         dev_set_drvdata(&op->dev, NULL);
 646         free_irq(i2c->irq, i2c);
 647  fail_request:
 648         irq_dispose_mapping(i2c->irq);
 649         iounmap(i2c->base);
 650  fail_map:
 651         kfree(i2c);
 652         return result;
 653 };
 654
 655 static int __devexit fsl_i2c_remove(struct platform_device *op)
 656 {
 657         struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
 658
 659         i2c_del_adapter(&i2c->adap);
 660         dev_set_drvdata(&op->dev, NULL);
 661
 662         if (i2c->irq)
 663                 free_irq(i2c->irq, i2c);
 664
 665         irq_dispose_mapping(i2c->irq);
 666         iounmap(i2c->base);
 667         kfree(i2c);
 668         return 0;
 669 };
 670
 671 static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = {
 672         .setup = mpc_i2c_setup_512x,
 673 };
 674
 675 static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = {
 676         .setup = mpc_i2c_setup_52xx,
 677 };
 678
 679 static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = {
 680         .setup = mpc_i2c_setup_8xxx,
 681 };
 682
 683 static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = {
 684         .setup = mpc_i2c_setup_8xxx,
 685         .prescaler = 2,
 686 };
 687
 688 static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = {
 689         .setup = mpc_i2c_setup_8xxx,
 690         .prescaler = 3,
 691 };
 692
 693 static const struct of_device_id mpc_i2c_of_match[] = {
 694         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 695         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
 696         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 697         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
 698         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
 699         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
 700         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
 701         /* Backward compatibility */
 702         {.compatible = "fsl-i2c", },
 703         {},
 704 };
 705 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
 706
 707 /* Structure for a device driver */
 708 static struct platform_driver mpc_i2c_driver = {
 709         .probe          = fsl_i2c_probe,
 710         .remove         = __devexit_p(fsl_i2c_remove),
 711         .driver = {
 712                 .owner = THIS_MODULE,
 713                 .name = DRV_NAME,
 714                 .of_match_table = mpc_i2c_of_match,
 715         },
 716 };
 717
 718 module_platform_driver(mpc_i2c_driver);
 719
 720 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 721 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
 722                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
 723 MODULE_LICENSE("GPL");