drivers/mfd/dbx500-prcmu-regs.h

   1 /*
   2  * Copyright (C) STMicroelectronics 2009
   3  * Copyright (C) ST-Ericsson SA 2010
   4  *
   5  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   6  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
   7  *
   8  * License Terms: GNU General Public License v2
   9  *
  10  * PRCM Unit registers
  11  */
  12
  13 #ifndef __DB8500_PRCMU_REGS_H
  14 #define __DB8500_PRCMU_REGS_H
  15
  16 #include <mach/hardware.h>
  17
  18 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
  19
  20 #define PRCM_SVACLK_MGT_OFF             0x008
  21 #define PRCM_SIACLK_MGT_OFF             0x00C
  22 #define PRCM_SGACLK_MGT_OFF             0x014
  23 #define PRCM_UARTCLK_MGT_OFF            0x018
  24 #define PRCM_MSP02CLK_MGT_OFF           0x01C
  25 #define PRCM_I2CCLK_MGT_OFF             0x020
  26 #define PRCM_SDMMCCLK_MGT_OFF           0x024
  27 #define PRCM_SLIMCLK_MGT_OFF            0x028
  28 #define PRCM_PER1CLK_MGT_OFF            0x02C
  29 #define PRCM_PER2CLK_MGT_OFF            0x030
  30 #define PRCM_PER3CLK_MGT_OFF            0x034
  31 #define PRCM_PER5CLK_MGT_OFF            0x038
  32 #define PRCM_PER6CLK_MGT_OFF            0x03C
  33 #define PRCM_PER7CLK_MGT_OFF            0x040
  34 #define PRCM_PWMCLK_MGT_OFF             0x044 /* for DB5500 */
  35 #define PRCM_IRDACLK_MGT_OFF            0x048 /* for DB5500 */
  36 #define PRCM_IRRCCLK_MGT_OFF            0x04C /* for DB5500 */
  37 #define PRCM_LCDCLK_MGT_OFF             0x044
  38 #define PRCM_BMLCLK_MGT_OFF             0x04C
  39 #define PRCM_HSITXCLK_MGT_OFF           0x050
  40 #define PRCM_HSIRXCLK_MGT_OFF           0x054
  41 #define PRCM_HDMICLK_MGT_OFF            0x058
  42 #define PRCM_APEATCLK_MGT_OFF           0x05C
  43 #define PRCM_APETRACECLK_MGT_OFF        0x060
  44 #define PRCM_MCDECLK_MGT_OFF            0x064
  45 #define PRCM_IPI2CCLK_MGT_OFF           0x068
  46 #define PRCM_DSIALTCLK_MGT_OFF          0x06C
  47 #define PRCM_DMACLK_MGT_OFF             0x074
  48 #define PRCM_B2R2CLK_MGT_OFF            0x078
  49 #define PRCM_TVCLK_MGT_OFF              0x07C
  50 #define PRCM_UNIPROCLK_MGT_OFF          0x278
  51 #define PRCM_SSPCLK_MGT_OFF             0x280
  52 #define PRCM_RNGCLK_MGT_OFF             0x284
  53 #define PRCM_UICCCLK_MGT_OFF            0x27C
  54 #define PRCM_MSP1CLK_MGT_OFF            0x288
  55
  56 #define PRCM_ARM_PLLDIVPS       (_PRCMU_BASE + 0x118)
  57 #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE          0x3f
  58 #define PRCM_ARM_PLLDIVPS_MAX_MASK              0xf
  59
  60 #define PRCM_PLLARM_LOCKP       (_PRCMU_BASE + 0x0a8)
  61 #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3    0x2
  62
  63 #define PRCM_ARM_CHGCLKREQ      (_PRCMU_BASE + 0x114)
  64 #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ   0x1
  65
  66 #define PRCM_PLLARM_ENABLE      (_PRCMU_BASE + 0x98)
  67 #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE   0x1
  68 #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON  0x100
  69
  70 #define PRCM_ARMCLKFIX_MGT      (_PRCMU_BASE + 0x0)
  71 #define PRCM_A9PL_FORCE_CLKEN   (_PRCMU_BASE + 0x19C)
  72 #define PRCM_A9_RESETN_CLR      (_PRCMU_BASE + 0x1f4)
  73 #define PRCM_A9_RESETN_SET      (_PRCMU_BASE + 0x1f0)
  74 #define PRCM_ARM_LS_CLAMP       (_PRCMU_BASE + 0x30c)
  75 #define PRCM_SRAM_A9            (_PRCMU_BASE + 0x308)
  76
  77 #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
  78 #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
  79
  80 /* ARM WFI Standby signal register */
  81 #define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)
  82 #define PRCM_IOCR               (_PRCMU_BASE + 0x310)
  83 #define PRCM_IOCR_IOFORCE                       0x1
  84
  85 /* CPU mailbox registers */
  86 #define PRCM_MBOX_CPU_VAL       (_PRCMU_BASE + 0x0fc)
  87 #define PRCM_MBOX_CPU_SET       (_PRCMU_BASE + 0x100)
  88 #define PRCM_MBOX_CPU_CLR       (_PRCMU_BASE + 0x104)
  89
  90 /* Dual A9 core interrupt management unit registers */
  91 #define PRCM_A9_MASK_REQ        (_PRCMU_BASE + 0x328)
  92 #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ       0x1
  93
  94 #define PRCM_A9_MASK_ACK        (_PRCMU_BASE + 0x32c)
  95 #define PRCM_ARMITMSK31TO0      (_PRCMU_BASE + 0x11c)
  96 #define PRCM_ARMITMSK63TO32     (_PRCMU_BASE + 0x120)
  97 #define PRCM_ARMITMSK95TO64     (_PRCMU_BASE + 0x124)
  98 #define PRCM_ARMITMSK127TO96    (_PRCMU_BASE + 0x128)
  99 #define PRCM_POWER_STATE_VAL    (_PRCMU_BASE + 0x25C)
 100 #define PRCM_ARMITVAL31TO0      (_PRCMU_BASE + 0x260)
 101 #define PRCM_ARMITVAL63TO32     (_PRCMU_BASE + 0x264)
 102 #define PRCM_ARMITVAL95TO64     (_PRCMU_BASE + 0x268)
 103 #define PRCM_ARMITVAL127TO96    (_PRCMU_BASE + 0x26C)
 104
 105 #define PRCM_HOSTACCESS_REQ     (_PRCMU_BASE + 0x334)
 106 #define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
 107 #define ARM_WAKEUP_MODEM        0x1
 108
 109 #define PRCM_ARM_IT1_CLR        (_PRCMU_BASE + 0x48C)
 110 #define PRCM_ARM_IT1_VAL        (_PRCMU_BASE + 0x494)
 111 #define PRCM_HOLD_EVT           (_PRCMU_BASE + 0x174)
 112
 113 #define PRCM_MOD_AWAKE_STATUS   (_PRCMU_BASE + 0x4A0)
 114 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE     BIT(0)
 115 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE       BIT(1)
 116 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO   BIT(2)
 117
 118 #define PRCM_ITSTATUS0          (_PRCMU_BASE + 0x148)
 119 #define PRCM_ITSTATUS1          (_PRCMU_BASE + 0x150)
 120 #define PRCM_ITSTATUS2          (_PRCMU_BASE + 0x158)
 121 #define PRCM_ITSTATUS3          (_PRCMU_BASE + 0x160)
 122 #define PRCM_ITSTATUS4          (_PRCMU_BASE + 0x168)
 123 #define PRCM_ITSTATUS5          (_PRCMU_BASE + 0x484)
 124 #define PRCM_ITCLEAR5           (_PRCMU_BASE + 0x488)
 125 #define PRCM_ARMIT_MASKXP70_IT  (_PRCMU_BASE + 0x1018)
 126
 127 /* System reset register */
 128 #define PRCM_APE_SOFTRST        (_PRCMU_BASE + 0x228)
 129
 130 /* Level shifter and clamp control registers */
 131 #define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)
 132 #define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)
 133
 134 /* PRCMU clock/PLL/reset registers */
 135 #define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)
 136 #define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)
 137 #define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
 138 #define PRCM_LCDCLK_MGT            (_PRCMU_BASE + PRCM_LCDCLK_MGT_OFF)
 139 #define PRCM_MCDECLK_MGT           (_PRCMU_BASE + PRCM_MCDECLK_MGT_OFF)
 140 #define PRCM_HDMICLK_MGT           (_PRCMU_BASE + PRCM_HDMICLK_MGT_OFF)
 141 #define PRCM_TVCLK_MGT             (_PRCMU_BASE + PRCM_TVCLK_MGT_OFF)
 142 #define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)
 143 #define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)
 144 #define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
 145 #define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
 146 #define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
 147
 148 #define PRCM_CLKOCR                (_PRCMU_BASE + 0x1CC)
 149 #define PRCM_CLKOCR_CLKOUT0_REF_CLK     (1 << 0)
 150 #define PRCM_CLKOCR_CLKOUT0_MASK        BITS(0, 13)
 151 #define PRCM_CLKOCR_CLKOUT1_REF_CLK     (1 << 16)
 152 #define PRCM_CLKOCR_CLKOUT1_MASK        BITS(16, 29)
 153
 154 /* ePOD and memory power signal control registers */
 155 #define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)
 156 #define PRCM_SRAM_LS_SLEEP         (_PRCMU_BASE + 0x304)
 157
 158 /* Debug power control unit registers */
 159 #define PRCM_POWER_STATE_SET       (_PRCMU_BASE + 0x254)
 160
 161 /* Miscellaneous unit registers */
 162 #define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)
 163 #define PRCM_GPIOCR                (_PRCMU_BASE + 0x138)
 164 #define PRCM_GPIOCR_DBG_STM_MOD_CMD1            0x800
 165 #define PRCM_GPIOCR_DBG_UARTMOD_CMD0            0x1
 166
 167 /* PRCMU HW semaphore */
 168 #define PRCM_SEM                   (_PRCMU_BASE + 0x400)
 169 #define PRCM_SEM_PRCM_SEM BIT(0)
 170
 171 #define PRCM_TCR                   (_PRCMU_BASE + 0x1C8)
 172 #define PRCM_TCR_TENSEL_MASK       BITS(0, 7)
 173 #define PRCM_TCR_STOP_TIMERS       BIT(16)
 174 #define PRCM_TCR_DOZE_MODE         BIT(17)
 175
 176 #define PRCM_CLKOCR_CLKODIV0_SHIFT      0
 177 #define PRCM_CLKOCR_CLKODIV0_MASK       BITS(0, 5)
 178 #define PRCM_CLKOCR_CLKOSEL0_SHIFT      6
 179 #define PRCM_CLKOCR_CLKOSEL0_MASK       BITS(6, 8)
 180 #define PRCM_CLKOCR_CLKODIV1_SHIFT      16
 181 #define PRCM_CLKOCR_CLKODIV1_MASK       BITS(16, 21)
 182 #define PRCM_CLKOCR_CLKOSEL1_SHIFT      22
 183 #define PRCM_CLKOCR_CLKOSEL1_MASK       BITS(22, 24)
 184 #define PRCM_CLKOCR_CLK1TYPE            BIT(28)
 185
 186 #define PRCM_CLK_MGT_CLKPLLDIV_MASK     BITS(0, 4)
 187 #define PRCM_CLK_MGT_CLKPLLSW_MASK      BITS(5, 7)
 188 #define PRCM_CLK_MGT_CLKEN              BIT(8)
 189
 190 /* GPIOCR register */
 191 #define PRCM_GPIOCR_SPI2_SELECT BIT(23)
 192
 193 #define PRCM_DDR_SUBSYS_APE_MINBW       (_PRCMU_BASE + 0x438)
 194 #define PRCM_CGATING_BYPASS             (_PRCMU_BASE + 0x134)
 195 #define PRCM_CGATING_BYPASS_ICN2        BIT(6)
 196
 197 /* Miscellaneous unit registers */
 198 #define PRCM_RESOUTN_SET                (_PRCMU_BASE + 0x214)
 199 #define PRCM_RESOUTN_CLR                (_PRCMU_BASE + 0x218)
 200
 201 /* System reset register */
 202 #define PRCM_APE_SOFTRST                (_PRCMU_BASE + 0x228)
 203
 204 #endif /* __DB8500_PRCMU_REGS_H */