spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / mfd / wm8994-irq.c
blob46b20c445ecfdfa8e1d6f189344e8d037a503f2c
1 /*
2 * wm8994-irq.c -- Interrupt controller support for Wolfson WM8994
4 * Copyright 2010 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/i2c.h>
18 #include <linux/irq.h>
19 #include <linux/mfd/core.h>
20 #include <linux/interrupt.h>
21 #include <linux/regmap.h>
23 #include <linux/mfd/wm8994/core.h>
24 #include <linux/mfd/wm8994/registers.h>
26 #include <linux/delay.h>
28 static struct regmap_irq wm8994_irqs[] = {
29 [WM8994_IRQ_TEMP_SHUT] = {
30 .reg_offset = 1,
31 .mask = WM8994_TEMP_SHUT_EINT,
33 [WM8994_IRQ_MIC1_DET] = {
34 .reg_offset = 1,
35 .mask = WM8994_MIC1_DET_EINT,
37 [WM8994_IRQ_MIC1_SHRT] = {
38 .reg_offset = 1,
39 .mask = WM8994_MIC1_SHRT_EINT,
41 [WM8994_IRQ_MIC2_DET] = {
42 .reg_offset = 1,
43 .mask = WM8994_MIC2_DET_EINT,
45 [WM8994_IRQ_MIC2_SHRT] = {
46 .reg_offset = 1,
47 .mask = WM8994_MIC2_SHRT_EINT,
49 [WM8994_IRQ_FLL1_LOCK] = {
50 .reg_offset = 1,
51 .mask = WM8994_FLL1_LOCK_EINT,
53 [WM8994_IRQ_FLL2_LOCK] = {
54 .reg_offset = 1,
55 .mask = WM8994_FLL2_LOCK_EINT,
57 [WM8994_IRQ_SRC1_LOCK] = {
58 .reg_offset = 1,
59 .mask = WM8994_SRC1_LOCK_EINT,
61 [WM8994_IRQ_SRC2_LOCK] = {
62 .reg_offset = 1,
63 .mask = WM8994_SRC2_LOCK_EINT,
65 [WM8994_IRQ_AIF1DRC1_SIG_DET] = {
66 .reg_offset = 1,
67 .mask = WM8994_AIF1DRC1_SIG_DET,
69 [WM8994_IRQ_AIF1DRC2_SIG_DET] = {
70 .reg_offset = 1,
71 .mask = WM8994_AIF1DRC2_SIG_DET_EINT,
73 [WM8994_IRQ_AIF2DRC_SIG_DET] = {
74 .reg_offset = 1,
75 .mask = WM8994_AIF2DRC_SIG_DET_EINT,
77 [WM8994_IRQ_FIFOS_ERR] = {
78 .reg_offset = 1,
79 .mask = WM8994_FIFOS_ERR_EINT,
81 [WM8994_IRQ_WSEQ_DONE] = {
82 .reg_offset = 1,
83 .mask = WM8994_WSEQ_DONE_EINT,
85 [WM8994_IRQ_DCS_DONE] = {
86 .reg_offset = 1,
87 .mask = WM8994_DCS_DONE_EINT,
89 [WM8994_IRQ_TEMP_WARN] = {
90 .reg_offset = 1,
91 .mask = WM8994_TEMP_WARN_EINT,
93 [WM8994_IRQ_GPIO(1)] = {
94 .mask = WM8994_GP1_EINT,
96 [WM8994_IRQ_GPIO(2)] = {
97 .mask = WM8994_GP2_EINT,
99 [WM8994_IRQ_GPIO(3)] = {
100 .mask = WM8994_GP3_EINT,
102 [WM8994_IRQ_GPIO(4)] = {
103 .mask = WM8994_GP4_EINT,
105 [WM8994_IRQ_GPIO(5)] = {
106 .mask = WM8994_GP5_EINT,
108 [WM8994_IRQ_GPIO(6)] = {
109 .mask = WM8994_GP6_EINT,
111 [WM8994_IRQ_GPIO(7)] = {
112 .mask = WM8994_GP7_EINT,
114 [WM8994_IRQ_GPIO(8)] = {
115 .mask = WM8994_GP8_EINT,
117 [WM8994_IRQ_GPIO(9)] = {
118 .mask = WM8994_GP8_EINT,
120 [WM8994_IRQ_GPIO(10)] = {
121 .mask = WM8994_GP10_EINT,
123 [WM8994_IRQ_GPIO(11)] = {
124 .mask = WM8994_GP11_EINT,
128 static struct regmap_irq_chip wm8994_irq_chip = {
129 .name = "wm8994",
130 .irqs = wm8994_irqs,
131 .num_irqs = ARRAY_SIZE(wm8994_irqs),
133 .num_regs = 2,
134 .status_base = WM8994_INTERRUPT_STATUS_1,
135 .mask_base = WM8994_INTERRUPT_STATUS_1_MASK,
136 .ack_base = WM8994_INTERRUPT_STATUS_1,
139 int wm8994_irq_init(struct wm8994 *wm8994)
141 int ret;
143 if (!wm8994->irq) {
144 dev_warn(wm8994->dev,
145 "No interrupt specified, no interrupts\n");
146 wm8994->irq_base = 0;
147 return 0;
150 if (!wm8994->irq_base) {
151 dev_err(wm8994->dev,
152 "No interrupt base specified, no interrupts\n");
153 return 0;
156 ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq,
157 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
158 wm8994->irq_base, &wm8994_irq_chip,
159 &wm8994->irq_data);
160 if (ret != 0) {
161 dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret);
162 return ret;
165 /* Enable top level interrupt if it was masked */
166 wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0);
168 return 0;
171 void wm8994_irq_exit(struct wm8994 *wm8994)
173 regmap_del_irq_chip(wm8994->irq, wm8994->irq_data);