spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / misc / iwmc3200top / iwmc3200top.h
blob620973ed8bf9252dbb6297e6a13a318ed482aabf
1 /*
2 * iwmc3200top - Intel Wireless MultiCom 3200 Top Driver
3 * drivers/misc/iwmc3200top/iwmc3200top.h
5 * Copyright (C) 2009 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License version
9 * 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301, USA.
22 * Author Name: Maxim Grabarnik <maxim.grabarnink@intel.com>
23 * -
27 #ifndef __IWMC3200TOP_H__
28 #define __IWMC3200TOP_H__
30 #include <linux/workqueue.h>
32 #define DRV_NAME "iwmc3200top"
33 #define FW_API_VER 1
34 #define _FW_NAME(api) DRV_NAME "." #api ".fw"
35 #define FW_NAME(api) _FW_NAME(api)
37 #define IWMC_SDIO_BLK_SIZE 256
38 #define IWMC_DEFAULT_TR_BLK 64
39 #define IWMC_SDIO_DATA_ADDR 0x0
40 #define IWMC_SDIO_INTR_ENABLE_ADDR 0x14
41 #define IWMC_SDIO_INTR_STATUS_ADDR 0x13
42 #define IWMC_SDIO_INTR_CLEAR_ADDR 0x13
43 #define IWMC_SDIO_INTR_GET_SIZE_ADDR 0x2C
45 #define COMM_HUB_HEADER_LENGTH 16
46 #define LOGGER_HEADER_LENGTH 10
49 #define BARKER_DNLOAD_BT_POS 0
50 #define BARKER_DNLOAD_BT_MSK BIT(BARKER_DNLOAD_BT_POS)
51 #define BARKER_DNLOAD_GPS_POS 1
52 #define BARKER_DNLOAD_GPS_MSK BIT(BARKER_DNLOAD_GPS_POS)
53 #define BARKER_DNLOAD_TOP_POS 2
54 #define BARKER_DNLOAD_TOP_MSK BIT(BARKER_DNLOAD_TOP_POS)
55 #define BARKER_DNLOAD_RESERVED1_POS 3
56 #define BARKER_DNLOAD_RESERVED1_MSK BIT(BARKER_DNLOAD_RESERVED1_POS)
57 #define BARKER_DNLOAD_JUMP_POS 4
58 #define BARKER_DNLOAD_JUMP_MSK BIT(BARKER_DNLOAD_JUMP_POS)
59 #define BARKER_DNLOAD_SYNC_POS 5
60 #define BARKER_DNLOAD_SYNC_MSK BIT(BARKER_DNLOAD_SYNC_POS)
61 #define BARKER_DNLOAD_RESERVED2_POS 6
62 #define BARKER_DNLOAD_RESERVED2_MSK (0x3 << BARKER_DNLOAD_RESERVED2_POS)
63 #define BARKER_DNLOAD_BARKER_POS 8
64 #define BARKER_DNLOAD_BARKER_MSK (0xffffff << BARKER_DNLOAD_BARKER_POS)
66 #define IWMC_BARKER_REBOOT (0xdeadbe << BARKER_DNLOAD_BARKER_POS)
67 /* whole field barker */
68 #define IWMC_BARKER_ACK 0xfeedbabe
70 #define IWMC_CMD_SIGNATURE 0xcbbc
72 #define CMD_HDR_OPCODE_POS 0
73 #define CMD_HDR_OPCODE_MSK_MSK (0xf << CMD_HDR_OPCODE_MSK_POS)
74 #define CMD_HDR_RESPONSE_CODE_POS 4
75 #define CMD_HDR_RESPONSE_CODE_MSK (0xf << CMD_HDR_RESPONSE_CODE_POS)
76 #define CMD_HDR_USE_CHECKSUM_POS 8
77 #define CMD_HDR_USE_CHECKSUM_MSK BIT(CMD_HDR_USE_CHECKSUM_POS)
78 #define CMD_HDR_RESPONSE_REQUIRED_POS 9
79 #define CMD_HDR_RESPONSE_REQUIRED_MSK BIT(CMD_HDR_RESPONSE_REQUIRED_POS)
80 #define CMD_HDR_DIRECT_ACCESS_POS 10
81 #define CMD_HDR_DIRECT_ACCESS_MSK BIT(CMD_HDR_DIRECT_ACCESS_POS)
82 #define CMD_HDR_RESERVED_POS 11
83 #define CMD_HDR_RESERVED_MSK BIT(0x1f << CMD_HDR_RESERVED_POS)
84 #define CMD_HDR_SIGNATURE_POS 16
85 #define CMD_HDR_SIGNATURE_MSK BIT(0xffff << CMD_HDR_SIGNATURE_POS)
87 enum {
88 IWMC_OPCODE_PING = 0,
89 IWMC_OPCODE_READ = 1,
90 IWMC_OPCODE_WRITE = 2,
91 IWMC_OPCODE_JUMP = 3,
92 IWMC_OPCODE_REBOOT = 4,
93 IWMC_OPCODE_PERSISTENT_WRITE = 5,
94 IWMC_OPCODE_PERSISTENT_READ = 6,
95 IWMC_OPCODE_READ_MODIFY_WRITE = 7,
96 IWMC_OPCODE_LAST_COMMAND = 15
99 struct iwmct_fw_load_hdr {
100 __le32 cmd;
101 __le32 target_addr;
102 __le32 data_size;
103 __le32 block_chksm;
104 u8 data[0];
108 * struct iwmct_fw_hdr
109 * holds all sw components versions
111 struct iwmct_fw_hdr {
112 u8 top_major;
113 u8 top_minor;
114 u8 top_revision;
115 u8 gps_major;
116 u8 gps_minor;
117 u8 gps_revision;
118 u8 bt_major;
119 u8 bt_minor;
120 u8 bt_revision;
121 u8 tic_name[31];
125 * struct iwmct_fw_sec_hdr
126 * @type: function type
127 * @data_size: section's data size
128 * @target_addr: download address
130 struct iwmct_fw_sec_hdr {
131 u8 type[4];
132 __le32 data_size;
133 __le32 target_addr;
137 * struct iwmct_parser
138 * @file: fw image
139 * @file_size: fw size
140 * @cur_pos: position in file
141 * @buf: temp buf for download
142 * @buf_size: size of buf
143 * @entry_point: address to jump in fw kick-off
145 struct iwmct_parser {
146 const u8 *file;
147 size_t file_size;
148 size_t cur_pos;
149 u8 *buf;
150 size_t buf_size;
151 u32 entry_point;
152 struct iwmct_fw_hdr versions;
156 struct iwmct_work_struct {
157 struct list_head list;
158 ssize_t iosize;
161 struct iwmct_dbg {
162 int blocks;
163 bool dump;
164 bool jump;
165 bool direct;
166 bool checksum;
167 bool fw_download;
168 int block_size;
169 int download_trans_blks;
171 char label_fw[256];
174 struct iwmct_debugfs;
176 struct iwmct_priv {
177 struct sdio_func *func;
178 struct iwmct_debugfs *dbgfs;
179 struct iwmct_parser parser;
180 atomic_t reset;
181 atomic_t dev_sync;
182 u32 trans_len;
183 u32 barker;
184 struct iwmct_dbg dbg;
186 /* drivers work items */
187 struct work_struct bus_rescan_worker;
188 struct work_struct isr_worker;
190 /* drivers wait queue */
191 wait_queue_head_t wait_q;
193 /* rx request list */
194 struct list_head read_req_list;
197 extern int iwmct_tx(struct iwmct_priv *priv, void *src, int count);
198 extern int iwmct_fw_load(struct iwmct_priv *priv);
200 extern void iwmct_dbg_init_params(struct iwmct_priv *drv);
201 extern void iwmct_dbg_init_drv_attrs(struct device_driver *drv);
202 extern void iwmct_dbg_remove_drv_attrs(struct device_driver *drv);
203 extern int iwmct_send_hcmd(struct iwmct_priv *priv, u8 *cmd, u16 len);
205 #endif /* __IWMC3200TOP_H__ */