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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / mmc / host / mxcmmc.c
blob4184b7946bbf34fd459c671a921ae6baf659e4d2
1 /*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
32 #include <linux/io.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/dmaengine.h>
36
37 #include <asm/dma.h>
38 #include <asm/irq.h>
39 #include <asm/sizes.h>
40 #include <mach/mmc.h>
41
42 #include <mach/dma.h>
43 #include <mach/hardware.h>
44
45 #define DRIVER_NAME "mxc-mmc"
46
47 #define MMC_REG_STR_STP_CLK 0x00
48 #define MMC_REG_STATUS 0x04
49 #define MMC_REG_CLK_RATE 0x08
50 #define MMC_REG_CMD_DAT_CONT 0x0C
51 #define MMC_REG_RES_TO 0x10
52 #define MMC_REG_READ_TO 0x14
53 #define MMC_REG_BLK_LEN 0x18
54 #define MMC_REG_NOB 0x1C
55 #define MMC_REG_REV_NO 0x20
56 #define MMC_REG_INT_CNTR 0x24
57 #define MMC_REG_CMD 0x28
58 #define MMC_REG_ARG 0x2C
59 #define MMC_REG_RES_FIFO 0x34
60 #define MMC_REG_BUFFER_ACCESS 0x38
61
62 #define STR_STP_CLK_RESET (1 << 3)
63 #define STR_STP_CLK_START_CLK (1 << 1)
64 #define STR_STP_CLK_STOP_CLK (1 << 0)
65
66 #define STATUS_CARD_INSERTION (1 << 31)
67 #define STATUS_CARD_REMOVAL (1 << 30)
68 #define STATUS_YBUF_EMPTY (1 << 29)
69 #define STATUS_XBUF_EMPTY (1 << 28)
70 #define STATUS_YBUF_FULL (1 << 27)
71 #define STATUS_XBUF_FULL (1 << 26)
72 #define STATUS_BUF_UND_RUN (1 << 25)
73 #define STATUS_BUF_OVFL (1 << 24)
74 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
75 #define STATUS_END_CMD_RESP (1 << 13)
76 #define STATUS_WRITE_OP_DONE (1 << 12)
77 #define STATUS_DATA_TRANS_DONE (1 << 11)
78 #define STATUS_READ_OP_DONE (1 << 11)
79 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81 #define STATUS_BUF_READ_RDY (1 << 7)
82 #define STATUS_BUF_WRITE_RDY (1 << 6)
83 #define STATUS_RESP_CRC_ERR (1 << 5)
84 #define STATUS_CRC_READ_ERR (1 << 3)
85 #define STATUS_CRC_WRITE_ERR (1 << 2)
86 #define STATUS_TIME_OUT_RESP (1 << 1)
87 #define STATUS_TIME_OUT_READ (1 << 0)
88 #define STATUS_ERR_MASK 0x2f
89
90 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
93 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94 #define CMD_DAT_CONT_INIT (1 << 7)
95 #define CMD_DAT_CONT_WRITE (1 << 4)
96 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100
101 #define INT_SDIO_INT_WKP_EN (1 << 18)
102 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
103 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104 #define INT_CARD_INSERTION_EN (1 << 15)
105 #define INT_CARD_REMOVAL_EN (1 << 14)
106 #define INT_SDIO_IRQ_EN (1 << 13)
107 #define INT_DAT0_EN (1 << 12)
108 #define INT_BUF_READ_EN (1 << 4)
109 #define INT_BUF_WRITE_EN (1 << 3)
110 #define INT_END_CMD_RES_EN (1 << 2)
111 #define INT_WRITE_OP_DONE_EN (1 << 1)
112 #define INT_READ_OP_EN (1 << 0)
113
114 struct mxcmci_host {
115 struct mmc_host *mmc;
116 struct resource *res;
117 void __iomem *base;
118 int irq;
119 int detect_irq;
120 struct dma_chan *dma;
121 struct dma_async_tx_descriptor *desc;
122 int do_dma;
123 int default_irq_mask;
124 int use_sdio;
125 unsigned int power_mode;
126 struct imxmmc_platform_data *pdata;
127
128 struct mmc_request *req;
129 struct mmc_command *cmd;
130 struct mmc_data *data;
131
132 unsigned int datasize;
133 unsigned int dma_dir;
134
135 u16 rev_no;
136 unsigned int cmdat;
137
138 struct clk *clk;
139
140 int clock;
141
142 struct work_struct datawork;
143 spinlock_t lock;
144
145 struct regulator *vcc;
146
147 int burstlen;
148 int dmareq;
149 struct dma_slave_config dma_slave_config;
150 struct imx_dma_data dma_data;
151 };
152
153 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
154
155 static inline void mxcmci_init_ocr(struct mxcmci_host *host)
156 {
157 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
158
159 if (IS_ERR(host->vcc)) {
160 host->vcc = NULL;
161 } else {
162 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
163 if (host->pdata && host->pdata->ocr_avail)
164 dev_warn(mmc_dev(host->mmc),
165 "pdata->ocr_avail will not be used\n");
166 }
167
168 if (host->vcc == NULL) {
169 /* fall-back to platform data */
170 if (host->pdata && host->pdata->ocr_avail)
171 host->mmc->ocr_avail = host->pdata->ocr_avail;
172 else
173 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
174 }
175 }
176
177 static inline void mxcmci_set_power(struct mxcmci_host *host,
178 unsigned char power_mode,
179 unsigned int vdd)
180 {
181 if (host->vcc) {
182 if (power_mode == MMC_POWER_UP)
183 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
184 else if (power_mode == MMC_POWER_OFF)
185 mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
186 }
187
188 if (host->pdata && host->pdata->setpower)
189 host->pdata->setpower(mmc_dev(host->mmc), vdd);
190 }
191
192 static inline int mxcmci_use_dma(struct mxcmci_host *host)
193 {
194 return host->do_dma;
195 }
196
197 static void mxcmci_softreset(struct mxcmci_host *host)
198 {
199 int i;
200
201 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
202
203 /* reset sequence */
204 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
205 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
206 host->base + MMC_REG_STR_STP_CLK);
207
208 for (i = 0; i < 8; i++)
209 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
210
211 writew(0xff, host->base + MMC_REG_RES_TO);
212 }
213 static int mxcmci_setup_dma(struct mmc_host *mmc);
214
215 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
216 {
217 unsigned int nob = data->blocks;
218 unsigned int blksz = data->blksz;
219 unsigned int datasize = nob * blksz;
220 struct scatterlist *sg;
221 enum dma_transfer_direction slave_dirn;
222 int i, nents;
223
224 if (data->flags & MMC_DATA_STREAM)
225 nob = 0xffff;
226
227 host->data = data;
228 data->bytes_xfered = 0;
229
230 writew(nob, host->base + MMC_REG_NOB);
231 writew(blksz, host->base + MMC_REG_BLK_LEN);
232 host->datasize = datasize;
233
234 if (!mxcmci_use_dma(host))
235 return 0;
236
237 for_each_sg(data->sg, sg, data->sg_len, i) {
238 if (sg->offset & 3 || sg->length & 3) {
239 host->do_dma = 0;
240 return 0;
241 }
242 }
243
244 if (data->flags & MMC_DATA_READ) {
245 host->dma_dir = DMA_FROM_DEVICE;
246 slave_dirn = DMA_DEV_TO_MEM;
247 } else {
248 host->dma_dir = DMA_TO_DEVICE;
249 slave_dirn = DMA_MEM_TO_DEV;
250 }
251
252 nents = dma_map_sg(host->dma->device->dev, data->sg,
253 data->sg_len, host->dma_dir);
254 if (nents != data->sg_len)
255 return -EINVAL;
256
257 host->desc = host->dma->device->device_prep_slave_sg(host->dma,
258 data->sg, data->sg_len, slave_dirn,
259 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
260
261 if (!host->desc) {
262 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
263 host->dma_dir);
264 host->do_dma = 0;
265 return 0; /* Fall back to PIO */
266 }
267 wmb();
268
269 dmaengine_submit(host->desc);
270
271 return 0;
272 }
273
274 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
275 unsigned int cmdat)
276 {
277 u32 int_cntr = host->default_irq_mask;
278 unsigned long flags;
279
280 WARN_ON(host->cmd != NULL);
281 host->cmd = cmd;
282
283 switch (mmc_resp_type(cmd)) {
284 case MMC_RSP_R1: /* short CRC, OPCODE */
285 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
286 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
287 break;
288 case MMC_RSP_R2: /* long 136 bit + CRC */
289 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
290 break;
291 case MMC_RSP_R3: /* short */
292 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
293 break;
294 case MMC_RSP_NONE:
295 break;
296 default:
297 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
298 mmc_resp_type(cmd));
299 cmd->error = -EINVAL;
300 return -EINVAL;
301 }
302
303 int_cntr = INT_END_CMD_RES_EN;
304
305 if (mxcmci_use_dma(host))
306 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN;
307
308 spin_lock_irqsave(&host->lock, flags);
309 if (host->use_sdio)
310 int_cntr |= INT_SDIO_IRQ_EN;
311 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
312 spin_unlock_irqrestore(&host->lock, flags);
313
314 writew(cmd->opcode, host->base + MMC_REG_CMD);
315 writel(cmd->arg, host->base + MMC_REG_ARG);
316 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
317
318 return 0;
319 }
320
321 static void mxcmci_finish_request(struct mxcmci_host *host,
322 struct mmc_request *req)
323 {
324 u32 int_cntr = host->default_irq_mask;
325 unsigned long flags;
326
327 spin_lock_irqsave(&host->lock, flags);
328 if (host->use_sdio)
329 int_cntr |= INT_SDIO_IRQ_EN;
330 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
331 spin_unlock_irqrestore(&host->lock, flags);
332
333 host->req = NULL;
334 host->cmd = NULL;
335 host->data = NULL;
336
337 mmc_request_done(host->mmc, req);
338 }
339
340 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
341 {
342 struct mmc_data *data = host->data;
343 int data_error;
344
345 if (mxcmci_use_dma(host)) {
346 dmaengine_terminate_all(host->dma);
347 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
348 host->dma_dir);
349 }
350
351 if (stat & STATUS_ERR_MASK) {
352 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
353 stat);
354 if (stat & STATUS_CRC_READ_ERR) {
355 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
356 data->error = -EILSEQ;
357 } else if (stat & STATUS_CRC_WRITE_ERR) {
358 u32 err_code = (stat >> 9) & 0x3;
359 if (err_code == 2) { /* No CRC response */
360 dev_err(mmc_dev(host->mmc),
361 "%s: No CRC -ETIMEDOUT\n", __func__);
362 data->error = -ETIMEDOUT;
363 } else {
364 dev_err(mmc_dev(host->mmc),
365 "%s: -EILSEQ\n", __func__);
366 data->error = -EILSEQ;
367 }
368 } else if (stat & STATUS_TIME_OUT_READ) {
369 dev_err(mmc_dev(host->mmc),
370 "%s: read -ETIMEDOUT\n", __func__);
371 data->error = -ETIMEDOUT;
372 } else {
373 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
374 data->error = -EIO;
375 }
376 } else {
377 data->bytes_xfered = host->datasize;
378 }
379
380 data_error = data->error;
381
382 host->data = NULL;
383
384 return data_error;
385 }
386
387 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
388 {
389 struct mmc_command *cmd = host->cmd;
390 int i;
391 u32 a, b, c;
392
393 if (!cmd)
394 return;
395
396 if (stat & STATUS_TIME_OUT_RESP) {
397 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
398 cmd->error = -ETIMEDOUT;
399 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
400 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
401 cmd->error = -EILSEQ;
402 }
403
404 if (cmd->flags & MMC_RSP_PRESENT) {
405 if (cmd->flags & MMC_RSP_136) {
406 for (i = 0; i < 4; i++) {
407 a = readw(host->base + MMC_REG_RES_FIFO);
408 b = readw(host->base + MMC_REG_RES_FIFO);
409 cmd->resp[i] = a << 16 | b;
410 }
411 } else {
412 a = readw(host->base + MMC_REG_RES_FIFO);
413 b = readw(host->base + MMC_REG_RES_FIFO);
414 c = readw(host->base + MMC_REG_RES_FIFO);
415 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
416 }
417 }
418 }
419
420 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
421 {
422 u32 stat;
423 unsigned long timeout = jiffies + HZ;
424
425 do {
426 stat = readl(host->base + MMC_REG_STATUS);
427 if (stat & STATUS_ERR_MASK)
428 return stat;
429 if (time_after(jiffies, timeout)) {
430 mxcmci_softreset(host);
431 mxcmci_set_clk_rate(host, host->clock);
432 return STATUS_TIME_OUT_READ;
433 }
434 if (stat & mask)
435 return 0;
436 cpu_relax();
437 } while (1);
438 }
439
440 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
441 {
442 unsigned int stat;
443 u32 *buf = _buf;
444
445 while (bytes > 3) {
446 stat = mxcmci_poll_status(host,
447 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
448 if (stat)
449 return stat;
450 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
451 bytes -= 4;
452 }
453
454 if (bytes) {
455 u8 *b = (u8 *)buf;
456 u32 tmp;
457
458 stat = mxcmci_poll_status(host,
459 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
460 if (stat)
461 return stat;
462 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
463 memcpy(b, &tmp, bytes);
464 }
465
466 return 0;
467 }
468
469 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
470 {
471 unsigned int stat;
472 u32 *buf = _buf;
473
474 while (bytes > 3) {
475 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
476 if (stat)
477 return stat;
478 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
479 bytes -= 4;
480 }
481
482 if (bytes) {
483 u8 *b = (u8 *)buf;
484 u32 tmp;
485
486 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
487 if (stat)
488 return stat;
489
490 memcpy(&tmp, b, bytes);
491 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
492 }
493
494 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
495 if (stat)
496 return stat;
497
498 return 0;
499 }
500
501 static int mxcmci_transfer_data(struct mxcmci_host *host)
502 {
503 struct mmc_data *data = host->req->data;
504 struct scatterlist *sg;
505 int stat, i;
506
507 host->data = data;
508 host->datasize = 0;
509
510 if (data->flags & MMC_DATA_READ) {
511 for_each_sg(data->sg, sg, data->sg_len, i) {
512 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
513 if (stat)
514 return stat;
515 host->datasize += sg->length;
516 }
517 } else {
518 for_each_sg(data->sg, sg, data->sg_len, i) {
519 stat = mxcmci_push(host, sg_virt(sg), sg->length);
520 if (stat)
521 return stat;
522 host->datasize += sg->length;
523 }
524 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
525 if (stat)
526 return stat;
527 }
528 return 0;
529 }
530
531 static void mxcmci_datawork(struct work_struct *work)
532 {
533 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
534 datawork);
535 int datastat = mxcmci_transfer_data(host);
536
537 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
538 host->base + MMC_REG_STATUS);
539 mxcmci_finish_data(host, datastat);
540
541 if (host->req->stop) {
542 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
543 mxcmci_finish_request(host, host->req);
544 return;
545 }
546 } else {
547 mxcmci_finish_request(host, host->req);
548 }
549 }
550
551 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
552 {
553 struct mmc_data *data = host->data;
554 int data_error;
555
556 if (!data)
557 return;
558
559 data_error = mxcmci_finish_data(host, stat);
560
561 mxcmci_read_response(host, stat);
562 host->cmd = NULL;
563
564 if (host->req->stop) {
565 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
566 mxcmci_finish_request(host, host->req);
567 return;
568 }
569 } else {
570 mxcmci_finish_request(host, host->req);
571 }
572 }
573
574 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
575 {
576 mxcmci_read_response(host, stat);
577 host->cmd = NULL;
578
579 if (!host->data && host->req) {
580 mxcmci_finish_request(host, host->req);
581 return;
582 }
583
584 /* For the DMA case the DMA engine handles the data transfer
585 * automatically. For non DMA we have to do it ourselves.
586 * Don't do it in interrupt context though.
587 */
588 if (!mxcmci_use_dma(host) && host->data)
589 schedule_work(&host->datawork);
590
591 }
592
593 static irqreturn_t mxcmci_irq(int irq, void *devid)
594 {
595 struct mxcmci_host *host = devid;
596 unsigned long flags;
597 bool sdio_irq;
598 u32 stat;
599
600 stat = readl(host->base + MMC_REG_STATUS);
601 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
602 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
603
604 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
605
606 spin_lock_irqsave(&host->lock, flags);
607 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
608 spin_unlock_irqrestore(&host->lock, flags);
609
610 if (mxcmci_use_dma(host) &&
611 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
612 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
613 host->base + MMC_REG_STATUS);
614
615 if (sdio_irq) {
616 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
617 mmc_signal_sdio_irq(host->mmc);
618 }
619
620 if (stat & STATUS_END_CMD_RESP)
621 mxcmci_cmd_done(host, stat);
622
623 if (mxcmci_use_dma(host) &&
624 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
625 mxcmci_data_done(host, stat);
626
627 if (host->default_irq_mask &&
628 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
629 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
630
631 return IRQ_HANDLED;
632 }
633
634 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
635 {
636 struct mxcmci_host *host = mmc_priv(mmc);
637 unsigned int cmdat = host->cmdat;
638 int error;
639
640 WARN_ON(host->req != NULL);
641
642 host->req = req;
643 host->cmdat &= ~CMD_DAT_CONT_INIT;
644
645 if (host->dma)
646 host->do_dma = 1;
647
648 if (req->data) {
649 error = mxcmci_setup_data(host, req->data);
650 if (error) {
651 req->cmd->error = error;
652 goto out;
653 }
654
655
656 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
657
658 if (req->data->flags & MMC_DATA_WRITE)
659 cmdat |= CMD_DAT_CONT_WRITE;
660 }
661
662 error = mxcmci_start_cmd(host, req->cmd, cmdat);
663
664 out:
665 if (error)
666 mxcmci_finish_request(host, req);
667 }
668
669 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
670 {
671 unsigned int divider;
672 int prescaler = 0;
673 unsigned int clk_in = clk_get_rate(host->clk);
674
675 while (prescaler <= 0x800) {
676 for (divider = 1; divider <= 0xF; divider++) {
677 int x;
678
679 x = (clk_in / (divider + 1));
680
681 if (prescaler)
682 x /= (prescaler * 2);
683
684 if (x <= clk_ios)
685 break;
686 }
687 if (divider < 0x10)
688 break;
689
690 if (prescaler == 0)
691 prescaler = 1;
692 else
693 prescaler <<= 1;
694 }
695
696 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
697
698 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
699 prescaler, divider, clk_in, clk_ios);
700 }
701
702 static int mxcmci_setup_dma(struct mmc_host *mmc)
703 {
704 struct mxcmci_host *host = mmc_priv(mmc);
705 struct dma_slave_config *config = &host->dma_slave_config;
706
707 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
708 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
709 config->dst_addr_width = 4;
710 config->src_addr_width = 4;
711 config->dst_maxburst = host->burstlen;
712 config->src_maxburst = host->burstlen;
713
714 return dmaengine_slave_config(host->dma, config);
715 }
716
717 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
718 {
719 struct mxcmci_host *host = mmc_priv(mmc);
720 int burstlen, ret;
721
722 /*
723 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
724 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
725 */
726 if (ios->bus_width == MMC_BUS_WIDTH_4)
727 burstlen = 16;
728 else
729 burstlen = 4;
730
731 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
732 host->burstlen = burstlen;
733 ret = mxcmci_setup_dma(mmc);
734 if (ret) {
735 dev_err(mmc_dev(host->mmc),
736 "failed to config DMA channel. Falling back to PIO\n");
737 dma_release_channel(host->dma);
738 host->do_dma = 0;
739 host->dma = NULL;
740 }
741 }
742
743 if (ios->bus_width == MMC_BUS_WIDTH_4)
744 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
745 else
746 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
747
748 if (host->power_mode != ios->power_mode) {
749 mxcmci_set_power(host, ios->power_mode, ios->vdd);
750 host->power_mode = ios->power_mode;
751
752 if (ios->power_mode == MMC_POWER_ON)
753 host->cmdat |= CMD_DAT_CONT_INIT;
754 }
755
756 if (ios->clock) {
757 mxcmci_set_clk_rate(host, ios->clock);
758 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
759 } else {
760 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
761 }
762
763 host->clock = ios->clock;
764 }
765
766 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
767 {
768 struct mmc_host *mmc = data;
769
770 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
771
772 mmc_detect_change(mmc, msecs_to_jiffies(250));
773 return IRQ_HANDLED;
774 }
775
776 static int mxcmci_get_ro(struct mmc_host *mmc)
777 {
778 struct mxcmci_host *host = mmc_priv(mmc);
779
780 if (host->pdata && host->pdata->get_ro)
781 return !!host->pdata->get_ro(mmc_dev(mmc));
782 /*
783 * Board doesn't support read only detection; let the mmc core
784 * decide what to do.
785 */
786 return -ENOSYS;
787 }
788
789 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
790 {
791 struct mxcmci_host *host = mmc_priv(mmc);
792 unsigned long flags;
793 u32 int_cntr;
794
795 spin_lock_irqsave(&host->lock, flags);
796 host->use_sdio = enable;
797 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
798
799 if (enable)
800 int_cntr |= INT_SDIO_IRQ_EN;
801 else
802 int_cntr &= ~INT_SDIO_IRQ_EN;
803
804 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
805 spin_unlock_irqrestore(&host->lock, flags);
806 }
807
808 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
809 {
810 /*
811 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
812 * multi-block transfers when connected SDIO peripheral doesn't
813 * drive the BUSY line as required by the specs.
814 * One way to prevent this is to only allow 1-bit transfers.
815 */
816
817 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO)
818 host->caps &= ~MMC_CAP_4_BIT_DATA;
819 else
820 host->caps |= MMC_CAP_4_BIT_DATA;
821 }
822
823 static bool filter(struct dma_chan *chan, void *param)
824 {
825 struct mxcmci_host *host = param;
826
827 if (!imx_dma_is_general_purpose(chan))
828 return false;
829
830 chan->private = &host->dma_data;
831
832 return true;
833 }
834
835 static const struct mmc_host_ops mxcmci_ops = {
836 .request = mxcmci_request,
837 .set_ios = mxcmci_set_ios,
838 .get_ro = mxcmci_get_ro,
839 .enable_sdio_irq = mxcmci_enable_sdio_irq,
840 .init_card = mxcmci_init_card,
841 };
842
843 static int mxcmci_probe(struct platform_device *pdev)
844 {
845 struct mmc_host *mmc;
846 struct mxcmci_host *host = NULL;
847 struct resource *iores, *r;
848 int ret = 0, irq;
849 dma_cap_mask_t mask;
850
851 pr_info("i.MX SDHC driver\n");
852
853 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
854 irq = platform_get_irq(pdev, 0);
855 if (!iores || irq < 0)
856 return -EINVAL;
857
858 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
859 if (!r)
860 return -EBUSY;
861
862 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
863 if (!mmc) {
864 ret = -ENOMEM;
865 goto out_release_mem;
866 }
867
868 mmc->ops = &mxcmci_ops;
869 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
870
871 /* MMC core transfer sizes tunable parameters */
872 mmc->max_segs = 64;
873 mmc->max_blk_size = 2048;
874 mmc->max_blk_count = 65535;
875 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
876 mmc->max_seg_size = mmc->max_req_size;
877
878 host = mmc_priv(mmc);
879 host->base = ioremap(r->start, resource_size(r));
880 if (!host->base) {
881 ret = -ENOMEM;
882 goto out_free;
883 }
884
885 host->mmc = mmc;
886 host->pdata = pdev->dev.platform_data;
887 spin_lock_init(&host->lock);
888
889 mxcmci_init_ocr(host);
890
891 if (host->pdata && host->pdata->dat3_card_detect)
892 host->default_irq_mask =
893 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
894 else
895 host->default_irq_mask = 0;
896
897 host->res = r;
898 host->irq = irq;
899
900 host->clk = clk_get(&pdev->dev, NULL);
901 if (IS_ERR(host->clk)) {
902 ret = PTR_ERR(host->clk);
903 goto out_iounmap;
904 }
905 clk_enable(host->clk);
906
907 mxcmci_softreset(host);
908
909 host->rev_no = readw(host->base + MMC_REG_REV_NO);
910 if (host->rev_no != 0x400) {
911 ret = -ENODEV;
912 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
913 host->rev_no);
914 goto out_clk_put;
915 }
916
917 mmc->f_min = clk_get_rate(host->clk) >> 16;
918 mmc->f_max = clk_get_rate(host->clk) >> 1;
919
920 /* recommended in data sheet */
921 writew(0x2db4, host->base + MMC_REG_READ_TO);
922
923 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
924
925 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
926 if (r) {
927 host->dmareq = r->start;
928 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
929 host->dma_data.priority = DMA_PRIO_LOW;
930 host->dma_data.dma_request = host->dmareq;
931 dma_cap_zero(mask);
932 dma_cap_set(DMA_SLAVE, mask);
933 host->dma = dma_request_channel(mask, filter, host);
934 if (host->dma)
935 mmc->max_seg_size = dma_get_max_seg_size(
936 host->dma->device->dev);
937 }
938
939 if (!host->dma)
940 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
941
942 INIT_WORK(&host->datawork, mxcmci_datawork);
943
944 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
945 if (ret)
946 goto out_free_dma;
947
948 platform_set_drvdata(pdev, mmc);
949
950 if (host->pdata && host->pdata->init) {
951 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
952 host->mmc);
953 if (ret)
954 goto out_free_irq;
955 }
956
957 mmc_add_host(mmc);
958
959 return 0;
960
961 out_free_irq:
962 free_irq(host->irq, host);
963 out_free_dma:
964 if (host->dma)
965 dma_release_channel(host->dma);
966 out_clk_put:
967 clk_disable(host->clk);
968 clk_put(host->clk);
969 out_iounmap:
970 iounmap(host->base);
971 out_free:
972 mmc_free_host(mmc);
973 out_release_mem:
974 release_mem_region(iores->start, resource_size(iores));
975 return ret;
976 }
977
978 static int mxcmci_remove(struct platform_device *pdev)
979 {
980 struct mmc_host *mmc = platform_get_drvdata(pdev);
981 struct mxcmci_host *host = mmc_priv(mmc);
982
983 platform_set_drvdata(pdev, NULL);
984
985 mmc_remove_host(mmc);
986
987 if (host->vcc)
988 regulator_put(host->vcc);
989
990 if (host->pdata && host->pdata->exit)
991 host->pdata->exit(&pdev->dev, mmc);
992
993 free_irq(host->irq, host);
994 iounmap(host->base);
995
996 if (host->dma)
997 dma_release_channel(host->dma);
998
999 clk_disable(host->clk);
1000 clk_put(host->clk);
1001
1002 release_mem_region(host->res->start, resource_size(host->res));
1003
1004 mmc_free_host(mmc);
1005
1006 return 0;
1007 }
1008
1009 #ifdef CONFIG_PM
1010 static int mxcmci_suspend(struct device *dev)
1011 {
1012 struct mmc_host *mmc = dev_get_drvdata(dev);
1013 struct mxcmci_host *host = mmc_priv(mmc);
1014 int ret = 0;
1015
1016 if (mmc)
1017 ret = mmc_suspend_host(mmc);
1018 clk_disable(host->clk);
1019
1020 return ret;
1021 }
1022
1023 static int mxcmci_resume(struct device *dev)
1024 {
1025 struct mmc_host *mmc = dev_get_drvdata(dev);
1026 struct mxcmci_host *host = mmc_priv(mmc);
1027 int ret = 0;
1028
1029 clk_enable(host->clk);
1030 if (mmc)
1031 ret = mmc_resume_host(mmc);
1032
1033 return ret;
1034 }
1035
1036 static const struct dev_pm_ops mxcmci_pm_ops = {
1037 .suspend = mxcmci_suspend,
1038 .resume = mxcmci_resume,
1039 };
1040 #endif
1041
1042 static struct platform_driver mxcmci_driver = {
1043 .probe = mxcmci_probe,
1044 .remove = mxcmci_remove,
1045 .driver = {
1046 .name = DRIVER_NAME,
1047 .owner = THIS_MODULE,
1048 #ifdef CONFIG_PM
1049 .pm = &mxcmci_pm_ops,
1050 #endif
1051 }
1052 };
1053
1054 module_platform_driver(mxcmci_driver);
1055
1056 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1057 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1058 MODULE_LICENSE("GPL");
1059 MODULE_ALIAS("platform:imx-mmc");