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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / mmc / host / mxs-mmc.c
blob382c835d217cf23372594b230dcd7923971288d5
1 /*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/platform_device.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmaengine.h>
31 #include <linux/highmem.h>
32 #include <linux/clk.h>
33 #include <linux/err.h>
34 #include <linux/completion.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/mmc/sdio.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/module.h>
41
42 #include <mach/mxs.h>
43 #include <mach/common.h>
44 #include <mach/dma.h>
45 #include <mach/mmc.h>
46
47 #define DRIVER_NAME "mxs-mmc"
48
49 /* card detect polling timeout */
50 #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
51
52 #define SSP_VERSION_LATEST 4
53 #define ssp_is_old() (host->version < SSP_VERSION_LATEST)
54
55 /* SSP registers */
56 #define HW_SSP_CTRL0 0x000
57 #define BM_SSP_CTRL0_RUN (1 << 29)
58 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
59 #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
60 #define BM_SSP_CTRL0_READ (1 << 25)
61 #define BM_SSP_CTRL0_DATA_XFER (1 << 24)
62 #define BP_SSP_CTRL0_BUS_WIDTH (22)
63 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
64 #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
65 #define BM_SSP_CTRL0_LONG_RESP (1 << 19)
66 #define BM_SSP_CTRL0_GET_RESP (1 << 17)
67 #define BM_SSP_CTRL0_ENABLE (1 << 16)
68 #define BP_SSP_CTRL0_XFER_COUNT (0)
69 #define BM_SSP_CTRL0_XFER_COUNT (0xffff)
70 #define HW_SSP_CMD0 0x010
71 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
72 #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
73 #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
74 #define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
75 #define BP_SSP_CMD0_BLOCK_SIZE (16)
76 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
77 #define BP_SSP_CMD0_BLOCK_COUNT (8)
78 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
79 #define BP_SSP_CMD0_CMD (0)
80 #define BM_SSP_CMD0_CMD (0xff)
81 #define HW_SSP_CMD1 0x020
82 #define HW_SSP_XFER_SIZE 0x030
83 #define HW_SSP_BLOCK_SIZE 0x040
84 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
85 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
86 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
87 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
88 #define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070)
89 #define BP_SSP_TIMING_TIMEOUT (16)
90 #define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
91 #define BP_SSP_TIMING_CLOCK_DIVIDE (8)
92 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
93 #define BP_SSP_TIMING_CLOCK_RATE (0)
94 #define BM_SSP_TIMING_CLOCK_RATE (0xff)
95 #define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080)
96 #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
97 #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
98 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
99 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
100 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
101 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
102 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
103 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
104 #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
105 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
106 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
107 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
108 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
109 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
110 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
111 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
112 #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
113 #define BM_SSP_CTRL1_POLARITY (1 << 9)
114 #define BP_SSP_CTRL1_WORD_LENGTH (4)
115 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
116 #define BP_SSP_CTRL1_SSP_MODE (0)
117 #define BM_SSP_CTRL1_SSP_MODE (0xf)
118 #define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0)
119 #define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0)
120 #define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0)
121 #define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0)
122 #define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100)
123 #define BM_SSP_STATUS_CARD_DETECT (1 << 28)
124 #define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
125 #define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130)
126 #define BP_SSP_VERSION_MAJOR (24)
127
128 #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
129
130 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
131 BM_SSP_CTRL1_RESP_ERR_IRQ | \
132 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
134 BM_SSP_CTRL1_DATA_CRC_IRQ | \
135 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
136 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
137 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
138
139 #define SSP_PIO_NUM 3
140
141 struct mxs_mmc_host {
142 struct mmc_host *mmc;
143 struct mmc_request *mrq;
144 struct mmc_command *cmd;
145 struct mmc_data *data;
146
147 void __iomem *base;
148 int irq;
149 struct resource *res;
150 struct resource *dma_res;
151 struct clk *clk;
152 unsigned int clk_rate;
153
154 struct dma_chan *dmach;
155 struct mxs_dma_data dma_data;
156 unsigned int dma_dir;
157 enum dma_transfer_direction slave_dirn;
158 u32 ssp_pio_words[SSP_PIO_NUM];
159
160 unsigned int version;
161 unsigned char bus_width;
162 spinlock_t lock;
163 int sdio_irq_en;
164 };
165
166 static int mxs_mmc_get_ro(struct mmc_host *mmc)
167 {
168 struct mxs_mmc_host *host = mmc_priv(mmc);
169 struct mxs_mmc_platform_data *pdata =
170 mmc_dev(host->mmc)->platform_data;
171
172 if (!pdata)
173 return -EFAULT;
174
175 if (!gpio_is_valid(pdata->wp_gpio))
176 return -EINVAL;
177
178 return gpio_get_value(pdata->wp_gpio);
179 }
180
181 static int mxs_mmc_get_cd(struct mmc_host *mmc)
182 {
183 struct mxs_mmc_host *host = mmc_priv(mmc);
184
185 return !(readl(host->base + HW_SSP_STATUS) &
186 BM_SSP_STATUS_CARD_DETECT);
187 }
188
189 static void mxs_mmc_reset(struct mxs_mmc_host *host)
190 {
191 u32 ctrl0, ctrl1;
192
193 mxs_reset_block(host->base);
194
195 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
196 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
197 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
198 BM_SSP_CTRL1_DMA_ENABLE |
199 BM_SSP_CTRL1_POLARITY |
200 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
201 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
202 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
203 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
204 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
205
206 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
207 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
208 BF_SSP(0, TIMING_CLOCK_RATE),
209 host->base + HW_SSP_TIMING);
210
211 if (host->sdio_irq_en) {
212 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
213 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
214 }
215
216 writel(ctrl0, host->base + HW_SSP_CTRL0);
217 writel(ctrl1, host->base + HW_SSP_CTRL1);
218 }
219
220 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
221 struct mmc_command *cmd);
222
223 static void mxs_mmc_request_done(struct mxs_mmc_host *host)
224 {
225 struct mmc_command *cmd = host->cmd;
226 struct mmc_data *data = host->data;
227 struct mmc_request *mrq = host->mrq;
228
229 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
230 if (mmc_resp_type(cmd) & MMC_RSP_136) {
231 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0);
232 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1);
233 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2);
234 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3);
235 } else {
236 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0);
237 }
238 }
239
240 if (data) {
241 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
242 data->sg_len, host->dma_dir);
243 /*
244 * If there was an error on any block, we mark all
245 * data blocks as being in error.
246 */
247 if (!data->error)
248 data->bytes_xfered = data->blocks * data->blksz;
249 else
250 data->bytes_xfered = 0;
251
252 host->data = NULL;
253 if (mrq->stop) {
254 mxs_mmc_start_cmd(host, mrq->stop);
255 return;
256 }
257 }
258
259 host->mrq = NULL;
260 mmc_request_done(host->mmc, mrq);
261 }
262
263 static void mxs_mmc_dma_irq_callback(void *param)
264 {
265 struct mxs_mmc_host *host = param;
266
267 mxs_mmc_request_done(host);
268 }
269
270 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
271 {
272 struct mxs_mmc_host *host = dev_id;
273 struct mmc_command *cmd = host->cmd;
274 struct mmc_data *data = host->data;
275 u32 stat;
276
277 spin_lock(&host->lock);
278
279 stat = readl(host->base + HW_SSP_CTRL1);
280 writel(stat & MXS_MMC_IRQ_BITS,
281 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
282
283 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
284 mmc_signal_sdio_irq(host->mmc);
285
286 spin_unlock(&host->lock);
287
288 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
289 cmd->error = -ETIMEDOUT;
290 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
291 cmd->error = -EIO;
292
293 if (data) {
294 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
295 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
296 data->error = -ETIMEDOUT;
297 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
298 data->error = -EILSEQ;
299 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
300 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
301 data->error = -EIO;
302 }
303
304 return IRQ_HANDLED;
305 }
306
307 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
308 struct mxs_mmc_host *host, unsigned int append)
309 {
310 struct dma_async_tx_descriptor *desc;
311 struct mmc_data *data = host->data;
312 struct scatterlist * sgl;
313 unsigned int sg_len;
314
315 if (data) {
316 /* data */
317 dma_map_sg(mmc_dev(host->mmc), data->sg,
318 data->sg_len, host->dma_dir);
319 sgl = data->sg;
320 sg_len = data->sg_len;
321 } else {
322 /* pio */
323 sgl = (struct scatterlist *) host->ssp_pio_words;
324 sg_len = SSP_PIO_NUM;
325 }
326
327 desc = host->dmach->device->device_prep_slave_sg(host->dmach,
328 sgl, sg_len, host->slave_dirn, append);
329 if (desc) {
330 desc->callback = mxs_mmc_dma_irq_callback;
331 desc->callback_param = host;
332 } else {
333 if (data)
334 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
335 data->sg_len, host->dma_dir);
336 }
337
338 return desc;
339 }
340
341 static void mxs_mmc_bc(struct mxs_mmc_host *host)
342 {
343 struct mmc_command *cmd = host->cmd;
344 struct dma_async_tx_descriptor *desc;
345 u32 ctrl0, cmd0, cmd1;
346
347 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
348 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
349 cmd1 = cmd->arg;
350
351 if (host->sdio_irq_en) {
352 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
353 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
354 }
355
356 host->ssp_pio_words[0] = ctrl0;
357 host->ssp_pio_words[1] = cmd0;
358 host->ssp_pio_words[2] = cmd1;
359 host->dma_dir = DMA_NONE;
360 host->slave_dirn = DMA_TRANS_NONE;
361 desc = mxs_mmc_prep_dma(host, 0);
362 if (!desc)
363 goto out;
364
365 dmaengine_submit(desc);
366 return;
367
368 out:
369 dev_warn(mmc_dev(host->mmc),
370 "%s: failed to prep dma\n", __func__);
371 }
372
373 static void mxs_mmc_ac(struct mxs_mmc_host *host)
374 {
375 struct mmc_command *cmd = host->cmd;
376 struct dma_async_tx_descriptor *desc;
377 u32 ignore_crc, get_resp, long_resp;
378 u32 ctrl0, cmd0, cmd1;
379
380 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
381 0 : BM_SSP_CTRL0_IGNORE_CRC;
382 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
383 BM_SSP_CTRL0_GET_RESP : 0;
384 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
385 BM_SSP_CTRL0_LONG_RESP : 0;
386
387 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
388 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
389 cmd1 = cmd->arg;
390
391 if (host->sdio_irq_en) {
392 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
393 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
394 }
395
396 host->ssp_pio_words[0] = ctrl0;
397 host->ssp_pio_words[1] = cmd0;
398 host->ssp_pio_words[2] = cmd1;
399 host->dma_dir = DMA_NONE;
400 host->slave_dirn = DMA_TRANS_NONE;
401 desc = mxs_mmc_prep_dma(host, 0);
402 if (!desc)
403 goto out;
404
405 dmaengine_submit(desc);
406 return;
407
408 out:
409 dev_warn(mmc_dev(host->mmc),
410 "%s: failed to prep dma\n", __func__);
411 }
412
413 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
414 {
415 const unsigned int ssp_timeout_mul = 4096;
416 /*
417 * Calculate ticks in ms since ns are large numbers
418 * and might overflow
419 */
420 const unsigned int clock_per_ms = clock_rate / 1000;
421 const unsigned int ms = ns / 1000;
422 const unsigned int ticks = ms * clock_per_ms;
423 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
424
425 WARN_ON(ssp_ticks == 0);
426 return ssp_ticks;
427 }
428
429 static void mxs_mmc_adtc(struct mxs_mmc_host *host)
430 {
431 struct mmc_command *cmd = host->cmd;
432 struct mmc_data *data = cmd->data;
433 struct dma_async_tx_descriptor *desc;
434 struct scatterlist *sgl = data->sg, *sg;
435 unsigned int sg_len = data->sg_len;
436 int i;
437
438 unsigned short dma_data_dir, timeout;
439 enum dma_transfer_direction slave_dirn;
440 unsigned int data_size = 0, log2_blksz;
441 unsigned int blocks = data->blocks;
442
443 u32 ignore_crc, get_resp, long_resp, read;
444 u32 ctrl0, cmd0, cmd1, val;
445
446 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
447 0 : BM_SSP_CTRL0_IGNORE_CRC;
448 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
449 BM_SSP_CTRL0_GET_RESP : 0;
450 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
451 BM_SSP_CTRL0_LONG_RESP : 0;
452
453 if (data->flags & MMC_DATA_WRITE) {
454 dma_data_dir = DMA_TO_DEVICE;
455 slave_dirn = DMA_MEM_TO_DEV;
456 read = 0;
457 } else {
458 dma_data_dir = DMA_FROM_DEVICE;
459 slave_dirn = DMA_DEV_TO_MEM;
460 read = BM_SSP_CTRL0_READ;
461 }
462
463 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
464 ignore_crc | get_resp | long_resp |
465 BM_SSP_CTRL0_DATA_XFER | read |
466 BM_SSP_CTRL0_WAIT_FOR_IRQ |
467 BM_SSP_CTRL0_ENABLE;
468
469 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
470
471 /* get logarithm to base 2 of block size for setting register */
472 log2_blksz = ilog2(data->blksz);
473
474 /*
475 * take special care of the case that data size from data->sg
476 * is not equal to blocks x blksz
477 */
478 for_each_sg(sgl, sg, sg_len, i)
479 data_size += sg->length;
480
481 if (data_size != data->blocks * data->blksz)
482 blocks = 1;
483
484 /* xfer count, block size and count need to be set differently */
485 if (ssp_is_old()) {
486 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
487 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
488 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
489 } else {
490 writel(data_size, host->base + HW_SSP_XFER_SIZE);
491 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
492 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
493 host->base + HW_SSP_BLOCK_SIZE);
494 }
495
496 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
497 (cmd->opcode == SD_IO_RW_EXTENDED))
498 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
499
500 cmd1 = cmd->arg;
501
502 if (host->sdio_irq_en) {
503 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
504 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
505 }
506
507 /* set the timeout count */
508 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
509 val = readl(host->base + HW_SSP_TIMING);
510 val &= ~(BM_SSP_TIMING_TIMEOUT);
511 val |= BF_SSP(timeout, TIMING_TIMEOUT);
512 writel(val, host->base + HW_SSP_TIMING);
513
514 /* pio */
515 host->ssp_pio_words[0] = ctrl0;
516 host->ssp_pio_words[1] = cmd0;
517 host->ssp_pio_words[2] = cmd1;
518 host->dma_dir = DMA_NONE;
519 host->slave_dirn = DMA_TRANS_NONE;
520 desc = mxs_mmc_prep_dma(host, 0);
521 if (!desc)
522 goto out;
523
524 /* append data sg */
525 WARN_ON(host->data != NULL);
526 host->data = data;
527 host->dma_dir = dma_data_dir;
528 host->slave_dirn = slave_dirn;
529 desc = mxs_mmc_prep_dma(host, 1);
530 if (!desc)
531 goto out;
532
533 dmaengine_submit(desc);
534 return;
535 out:
536 dev_warn(mmc_dev(host->mmc),
537 "%s: failed to prep dma\n", __func__);
538 }
539
540 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
541 struct mmc_command *cmd)
542 {
543 host->cmd = cmd;
544
545 switch (mmc_cmd_type(cmd)) {
546 case MMC_CMD_BC:
547 mxs_mmc_bc(host);
548 break;
549 case MMC_CMD_BCR:
550 mxs_mmc_ac(host);
551 break;
552 case MMC_CMD_AC:
553 mxs_mmc_ac(host);
554 break;
555 case MMC_CMD_ADTC:
556 mxs_mmc_adtc(host);
557 break;
558 default:
559 dev_warn(mmc_dev(host->mmc),
560 "%s: unknown MMC command\n", __func__);
561 break;
562 }
563 }
564
565 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
566 {
567 struct mxs_mmc_host *host = mmc_priv(mmc);
568
569 WARN_ON(host->mrq != NULL);
570 host->mrq = mrq;
571 mxs_mmc_start_cmd(host, mrq->cmd);
572 }
573
574 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
575 {
576 unsigned int ssp_clk, ssp_sck;
577 u32 clock_divide, clock_rate;
578 u32 val;
579
580 ssp_clk = clk_get_rate(host->clk);
581
582 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
583 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
584 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
585 if (clock_rate <= 255)
586 break;
587 }
588
589 if (clock_divide > 254) {
590 dev_err(mmc_dev(host->mmc),
591 "%s: cannot set clock to %d\n", __func__, rate);
592 return;
593 }
594
595 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
596
597 val = readl(host->base + HW_SSP_TIMING);
598 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
599 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
600 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
601 writel(val, host->base + HW_SSP_TIMING);
602
603 host->clk_rate = ssp_sck;
604
605 dev_dbg(mmc_dev(host->mmc),
606 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
607 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
608 }
609
610 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
611 {
612 struct mxs_mmc_host *host = mmc_priv(mmc);
613
614 if (ios->bus_width == MMC_BUS_WIDTH_8)
615 host->bus_width = 2;
616 else if (ios->bus_width == MMC_BUS_WIDTH_4)
617 host->bus_width = 1;
618 else
619 host->bus_width = 0;
620
621 if (ios->clock)
622 mxs_mmc_set_clk_rate(host, ios->clock);
623 }
624
625 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
626 {
627 struct mxs_mmc_host *host = mmc_priv(mmc);
628 unsigned long flags;
629
630 spin_lock_irqsave(&host->lock, flags);
631
632 host->sdio_irq_en = enable;
633
634 if (enable) {
635 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
636 host->base + HW_SSP_CTRL0 + MXS_SET_ADDR);
637 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
638 host->base + HW_SSP_CTRL1 + MXS_SET_ADDR);
639
640 if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ)
641 mmc_signal_sdio_irq(host->mmc);
642
643 } else {
644 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
645 host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR);
646 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
647 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
648 }
649
650 spin_unlock_irqrestore(&host->lock, flags);
651 }
652
653 static const struct mmc_host_ops mxs_mmc_ops = {
654 .request = mxs_mmc_request,
655 .get_ro = mxs_mmc_get_ro,
656 .get_cd = mxs_mmc_get_cd,
657 .set_ios = mxs_mmc_set_ios,
658 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
659 };
660
661 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
662 {
663 struct mxs_mmc_host *host = param;
664
665 if (!mxs_dma_is_apbh(chan))
666 return false;
667
668 if (chan->chan_id != host->dma_res->start)
669 return false;
670
671 chan->private = &host->dma_data;
672
673 return true;
674 }
675
676 static int mxs_mmc_probe(struct platform_device *pdev)
677 {
678 struct mxs_mmc_host *host;
679 struct mmc_host *mmc;
680 struct resource *iores, *dmares, *r;
681 struct mxs_mmc_platform_data *pdata;
682 int ret = 0, irq_err, irq_dma;
683 dma_cap_mask_t mask;
684
685 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
687 irq_err = platform_get_irq(pdev, 0);
688 irq_dma = platform_get_irq(pdev, 1);
689 if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
690 return -EINVAL;
691
692 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
693 if (!r)
694 return -EBUSY;
695
696 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
697 if (!mmc) {
698 ret = -ENOMEM;
699 goto out_release_mem;
700 }
701
702 host = mmc_priv(mmc);
703 host->base = ioremap(r->start, resource_size(r));
704 if (!host->base) {
705 ret = -ENOMEM;
706 goto out_mmc_free;
707 }
708
709 /* only major verion does matter */
710 host->version = readl(host->base + HW_SSP_VERSION) >>
711 BP_SSP_VERSION_MAJOR;
712
713 host->mmc = mmc;
714 host->res = r;
715 host->dma_res = dmares;
716 host->irq = irq_err;
717 host->sdio_irq_en = 0;
718
719 host->clk = clk_get(&pdev->dev, NULL);
720 if (IS_ERR(host->clk)) {
721 ret = PTR_ERR(host->clk);
722 goto out_iounmap;
723 }
724 clk_prepare_enable(host->clk);
725
726 mxs_mmc_reset(host);
727
728 dma_cap_zero(mask);
729 dma_cap_set(DMA_SLAVE, mask);
730 host->dma_data.chan_irq = irq_dma;
731 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
732 if (!host->dmach) {
733 dev_err(mmc_dev(host->mmc),
734 "%s: failed to request dma\n", __func__);
735 goto out_clk_put;
736 }
737
738 /* set mmc core parameters */
739 mmc->ops = &mxs_mmc_ops;
740 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
741 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
742
743 pdata = mmc_dev(host->mmc)->platform_data;
744 if (pdata) {
745 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
746 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
747 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
748 mmc->caps |= MMC_CAP_4_BIT_DATA;
749 }
750
751 mmc->f_min = 400000;
752 mmc->f_max = 288000000;
753 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
754
755 mmc->max_segs = 52;
756 mmc->max_blk_size = 1 << 0xf;
757 mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff;
758 mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff;
759 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
760
761 platform_set_drvdata(pdev, mmc);
762
763 ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host);
764 if (ret)
765 goto out_free_dma;
766
767 spin_lock_init(&host->lock);
768
769 ret = mmc_add_host(mmc);
770 if (ret)
771 goto out_free_irq;
772
773 dev_info(mmc_dev(host->mmc), "initialized\n");
774
775 return 0;
776
777 out_free_irq:
778 free_irq(host->irq, host);
779 out_free_dma:
780 if (host->dmach)
781 dma_release_channel(host->dmach);
782 out_clk_put:
783 clk_disable_unprepare(host->clk);
784 clk_put(host->clk);
785 out_iounmap:
786 iounmap(host->base);
787 out_mmc_free:
788 mmc_free_host(mmc);
789 out_release_mem:
790 release_mem_region(iores->start, resource_size(iores));
791 return ret;
792 }
793
794 static int mxs_mmc_remove(struct platform_device *pdev)
795 {
796 struct mmc_host *mmc = platform_get_drvdata(pdev);
797 struct mxs_mmc_host *host = mmc_priv(mmc);
798 struct resource *res = host->res;
799
800 mmc_remove_host(mmc);
801
802 free_irq(host->irq, host);
803
804 platform_set_drvdata(pdev, NULL);
805
806 if (host->dmach)
807 dma_release_channel(host->dmach);
808
809 clk_disable_unprepare(host->clk);
810 clk_put(host->clk);
811
812 iounmap(host->base);
813
814 mmc_free_host(mmc);
815
816 release_mem_region(res->start, resource_size(res));
817
818 return 0;
819 }
820
821 #ifdef CONFIG_PM
822 static int mxs_mmc_suspend(struct device *dev)
823 {
824 struct mmc_host *mmc = dev_get_drvdata(dev);
825 struct mxs_mmc_host *host = mmc_priv(mmc);
826 int ret = 0;
827
828 ret = mmc_suspend_host(mmc);
829
830 clk_disable_unprepare(host->clk);
831
832 return ret;
833 }
834
835 static int mxs_mmc_resume(struct device *dev)
836 {
837 struct mmc_host *mmc = dev_get_drvdata(dev);
838 struct mxs_mmc_host *host = mmc_priv(mmc);
839 int ret = 0;
840
841 clk_prepare_enable(host->clk);
842
843 ret = mmc_resume_host(mmc);
844
845 return ret;
846 }
847
848 static const struct dev_pm_ops mxs_mmc_pm_ops = {
849 .suspend = mxs_mmc_suspend,
850 .resume = mxs_mmc_resume,
851 };
852 #endif
853
854 static struct platform_driver mxs_mmc_driver = {
855 .probe = mxs_mmc_probe,
856 .remove = mxs_mmc_remove,
857 .driver = {
858 .name = DRIVER_NAME,
859 .owner = THIS_MODULE,
860 #ifdef CONFIG_PM
861 .pm = &mxs_mmc_pm_ops,
862 #endif
863 },
864 };
865
866 module_platform_driver(mxs_mmc_driver);
867
868 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
869 MODULE_AUTHOR("Freescale Semiconductor");
870 MODULE_LICENSE("GPL");