2 * Dave DNET Ethernet Controller driver
4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
5 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/phy.h>
30 /* function for reading internal MAC register */
31 static u16
dnet_readw_mac(struct dnet
*bp
, u16 reg
)
36 dnet_writel(bp
, reg
, MACREG_ADDR
);
38 /* since a read/write op to the MAC is very slow,
39 * we must wait before reading the data */
42 /* read data read from the MAC register */
43 data_read
= dnet_readl(bp
, MACREG_DATA
);
49 /* function for writing internal MAC register */
50 static void dnet_writew_mac(struct dnet
*bp
, u16 reg
, u16 val
)
52 /* load data to write */
53 dnet_writel(bp
, val
, MACREG_DATA
);
56 dnet_writel(bp
, reg
| DNET_INTERNAL_WRITE
, MACREG_ADDR
);
58 /* since a read/write op to the MAC is very slow,
59 * we must wait before exiting */
63 static void __dnet_set_hwaddr(struct dnet
*bp
)
67 tmp
= be16_to_cpup((__be16
*)bp
->dev
->dev_addr
);
68 dnet_writew_mac(bp
, DNET_INTERNAL_MAC_ADDR_0_REG
, tmp
);
69 tmp
= be16_to_cpup((__be16
*)(bp
->dev
->dev_addr
+ 2));
70 dnet_writew_mac(bp
, DNET_INTERNAL_MAC_ADDR_1_REG
, tmp
);
71 tmp
= be16_to_cpup((__be16
*)(bp
->dev
->dev_addr
+ 4));
72 dnet_writew_mac(bp
, DNET_INTERNAL_MAC_ADDR_2_REG
, tmp
);
75 static void __devinit
dnet_get_hwaddr(struct dnet
*bp
)
82 * "Note that the MAC address is stored in the registers in Hexadecimal
83 * form. For example, to set the MAC Address to: AC-DE-48-00-00-80
84 * would require writing 0xAC (octet 0) to address 0x0B (high byte of
85 * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
86 * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
87 * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
88 * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
89 * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
92 tmp
= dnet_readw_mac(bp
, DNET_INTERNAL_MAC_ADDR_0_REG
);
93 *((__be16
*)addr
) = cpu_to_be16(tmp
);
94 tmp
= dnet_readw_mac(bp
, DNET_INTERNAL_MAC_ADDR_1_REG
);
95 *((__be16
*)(addr
+ 2)) = cpu_to_be16(tmp
);
96 tmp
= dnet_readw_mac(bp
, DNET_INTERNAL_MAC_ADDR_2_REG
);
97 *((__be16
*)(addr
+ 4)) = cpu_to_be16(tmp
);
99 if (is_valid_ether_addr(addr
))
100 memcpy(bp
->dev
->dev_addr
, addr
, sizeof(addr
));
103 static int dnet_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
105 struct dnet
*bp
= bus
->priv
;
108 while (!(dnet_readw_mac(bp
, DNET_INTERNAL_GMII_MNG_CTL_REG
)
109 & DNET_INTERNAL_GMII_MNG_CMD_FIN
))
112 /* only 5 bits allowed for phy-addr and reg_offset */
116 /* prepare reg_value for a read */
117 value
= (mii_id
<< 8);
120 /* write control word */
121 dnet_writew_mac(bp
, DNET_INTERNAL_GMII_MNG_CTL_REG
, value
);
123 /* wait for end of transfer */
124 while (!(dnet_readw_mac(bp
, DNET_INTERNAL_GMII_MNG_CTL_REG
)
125 & DNET_INTERNAL_GMII_MNG_CMD_FIN
))
128 value
= dnet_readw_mac(bp
, DNET_INTERNAL_GMII_MNG_DAT_REG
);
130 pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id
, regnum
, value
);
135 static int dnet_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
138 struct dnet
*bp
= bus
->priv
;
141 pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id
, regnum
, value
);
143 while (!(dnet_readw_mac(bp
, DNET_INTERNAL_GMII_MNG_CTL_REG
)
144 & DNET_INTERNAL_GMII_MNG_CMD_FIN
))
147 /* prepare for a write operation */
150 /* only 5 bits allowed for phy-addr and reg_offset */
154 /* only 16 bits on data */
157 /* prepare reg_value for a write */
158 tmp
|= (mii_id
<< 8);
161 /* write data to write first */
162 dnet_writew_mac(bp
, DNET_INTERNAL_GMII_MNG_DAT_REG
, value
);
164 /* write control word */
165 dnet_writew_mac(bp
, DNET_INTERNAL_GMII_MNG_CTL_REG
, tmp
);
167 while (!(dnet_readw_mac(bp
, DNET_INTERNAL_GMII_MNG_CTL_REG
)
168 & DNET_INTERNAL_GMII_MNG_CMD_FIN
))
174 static int dnet_mdio_reset(struct mii_bus
*bus
)
179 static void dnet_handle_link_change(struct net_device
*dev
)
181 struct dnet
*bp
= netdev_priv(dev
);
182 struct phy_device
*phydev
= bp
->phy_dev
;
184 u32 mode_reg
, ctl_reg
;
186 int status_change
= 0;
188 spin_lock_irqsave(&bp
->lock
, flags
);
190 mode_reg
= dnet_readw_mac(bp
, DNET_INTERNAL_MODE_REG
);
191 ctl_reg
= dnet_readw_mac(bp
, DNET_INTERNAL_RXTX_CONTROL_REG
);
194 if (bp
->duplex
!= phydev
->duplex
) {
197 ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP
);
200 DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP
;
202 bp
->duplex
= phydev
->duplex
;
206 if (bp
->speed
!= phydev
->speed
) {
208 switch (phydev
->speed
) {
210 mode_reg
|= DNET_INTERNAL_MODE_GBITEN
;
214 mode_reg
&= ~DNET_INTERNAL_MODE_GBITEN
;
218 "%s: Ack! Speed (%d) is not "
219 "10/100/1000!\n", dev
->name
,
223 bp
->speed
= phydev
->speed
;
227 if (phydev
->link
!= bp
->link
) {
230 (DNET_INTERNAL_MODE_RXEN
| DNET_INTERNAL_MODE_TXEN
);
233 ~(DNET_INTERNAL_MODE_RXEN
|
234 DNET_INTERNAL_MODE_TXEN
);
238 bp
->link
= phydev
->link
;
244 dnet_writew_mac(bp
, DNET_INTERNAL_RXTX_CONTROL_REG
, ctl_reg
);
245 dnet_writew_mac(bp
, DNET_INTERNAL_MODE_REG
, mode_reg
);
248 spin_unlock_irqrestore(&bp
->lock
, flags
);
252 printk(KERN_INFO
"%s: link up (%d/%s)\n",
253 dev
->name
, phydev
->speed
,
254 DUPLEX_FULL
== phydev
->duplex
? "Full" : "Half");
256 printk(KERN_INFO
"%s: link down\n", dev
->name
);
260 static int dnet_mii_probe(struct net_device
*dev
)
262 struct dnet
*bp
= netdev_priv(dev
);
263 struct phy_device
*phydev
= NULL
;
266 /* find the first phy */
267 for (phy_addr
= 0; phy_addr
< PHY_MAX_ADDR
; phy_addr
++) {
268 if (bp
->mii_bus
->phy_map
[phy_addr
]) {
269 phydev
= bp
->mii_bus
->phy_map
[phy_addr
];
275 printk(KERN_ERR
"%s: no PHY found\n", dev
->name
);
279 /* TODO : add pin_irq */
281 /* attach the mac to the phy */
282 if (bp
->capabilities
& DNET_HAS_RMII
) {
283 phydev
= phy_connect(dev
, dev_name(&phydev
->dev
),
284 &dnet_handle_link_change
, 0,
285 PHY_INTERFACE_MODE_RMII
);
287 phydev
= phy_connect(dev
, dev_name(&phydev
->dev
),
288 &dnet_handle_link_change
, 0,
289 PHY_INTERFACE_MODE_MII
);
292 if (IS_ERR(phydev
)) {
293 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
294 return PTR_ERR(phydev
);
297 /* mask with MAC supported features */
298 if (bp
->capabilities
& DNET_HAS_GIGABIT
)
299 phydev
->supported
&= PHY_GBIT_FEATURES
;
301 phydev
->supported
&= PHY_BASIC_FEATURES
;
303 phydev
->supported
|= SUPPORTED_Asym_Pause
| SUPPORTED_Pause
;
305 phydev
->advertising
= phydev
->supported
;
310 bp
->phy_dev
= phydev
;
315 static int dnet_mii_init(struct dnet
*bp
)
319 bp
->mii_bus
= mdiobus_alloc();
320 if (bp
->mii_bus
== NULL
)
323 bp
->mii_bus
->name
= "dnet_mii_bus";
324 bp
->mii_bus
->read
= &dnet_mdio_read
;
325 bp
->mii_bus
->write
= &dnet_mdio_write
;
326 bp
->mii_bus
->reset
= &dnet_mdio_reset
;
328 snprintf(bp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
329 bp
->pdev
->name
, bp
->pdev
->id
);
331 bp
->mii_bus
->priv
= bp
;
333 bp
->mii_bus
->irq
= kmalloc(sizeof(int) * PHY_MAX_ADDR
, GFP_KERNEL
);
334 if (!bp
->mii_bus
->irq
) {
339 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
340 bp
->mii_bus
->irq
[i
] = PHY_POLL
;
342 if (mdiobus_register(bp
->mii_bus
)) {
344 goto err_out_free_mdio_irq
;
347 if (dnet_mii_probe(bp
->dev
) != 0) {
349 goto err_out_unregister_bus
;
354 err_out_unregister_bus
:
355 mdiobus_unregister(bp
->mii_bus
);
356 err_out_free_mdio_irq
:
357 kfree(bp
->mii_bus
->irq
);
359 mdiobus_free(bp
->mii_bus
);
363 /* For Neptune board: LINK1000 as Link LED and TX as activity LED */
364 static int dnet_phy_marvell_fixup(struct phy_device
*phydev
)
366 return phy_write(phydev
, 0x18, 0x4148);
369 static void dnet_update_stats(struct dnet
*bp
)
371 u32 __iomem
*reg
= bp
->regs
+ DNET_RX_PKT_IGNR_CNT
;
372 u32
*p
= &bp
->hw_stats
.rx_pkt_ignr
;
373 u32
*end
= &bp
->hw_stats
.rx_byte
+ 1;
375 WARN_ON((unsigned long)(end
- p
- 1) !=
376 (DNET_RX_BYTE_CNT
- DNET_RX_PKT_IGNR_CNT
) / 4);
378 for (; p
< end
; p
++, reg
++)
381 reg
= bp
->regs
+ DNET_TX_UNICAST_CNT
;
382 p
= &bp
->hw_stats
.tx_unicast
;
383 end
= &bp
->hw_stats
.tx_byte
+ 1;
385 WARN_ON((unsigned long)(end
- p
- 1) !=
386 (DNET_TX_BYTE_CNT
- DNET_TX_UNICAST_CNT
) / 4);
388 for (; p
< end
; p
++, reg
++)
392 static int dnet_poll(struct napi_struct
*napi
, int budget
)
394 struct dnet
*bp
= container_of(napi
, struct dnet
, napi
);
395 struct net_device
*dev
= bp
->dev
;
397 unsigned int pkt_len
;
399 unsigned int *data_ptr
;
404 while (npackets
< budget
) {
406 * break out of while loop if there are no more
409 if (!(dnet_readl(bp
, RX_FIFO_WCNT
) >> 16)) {
411 int_enable
= dnet_readl(bp
, INTR_ENB
);
412 int_enable
|= DNET_INTR_SRC_RX_CMDFIFOAF
;
413 dnet_writel(bp
, int_enable
, INTR_ENB
);
417 cmd_word
= dnet_readl(bp
, RX_LEN_FIFO
);
418 pkt_len
= cmd_word
& 0xFFFF;
420 if (cmd_word
& 0xDF180000)
421 printk(KERN_ERR
"%s packet receive error %x\n",
424 skb
= dev_alloc_skb(pkt_len
+ 5);
426 /* Align IP on 16 byte boundaries */
429 * 'skb_put()' points to the start of sk_buff
432 data_ptr
= (unsigned int *)skb_put(skb
, pkt_len
);
433 for (i
= 0; i
< (pkt_len
+ 3) >> 2; i
++)
434 *data_ptr
++ = dnet_readl(bp
, RX_DATA_FIFO
);
435 skb
->protocol
= eth_type_trans(skb
, dev
);
436 netif_receive_skb(skb
);
440 "%s: No memory to allocate a sk_buff of "
441 "size %u.\n", dev
->name
, pkt_len
);
446 if (npackets
< budget
) {
447 /* We processed all packets available. Tell NAPI it can
448 * stop polling then re-enable rx interrupts */
450 int_enable
= dnet_readl(bp
, INTR_ENB
);
451 int_enable
|= DNET_INTR_SRC_RX_CMDFIFOAF
;
452 dnet_writel(bp
, int_enable
, INTR_ENB
);
456 /* There are still packets waiting */
460 static irqreturn_t
dnet_interrupt(int irq
, void *dev_id
)
462 struct net_device
*dev
= dev_id
;
463 struct dnet
*bp
= netdev_priv(dev
);
464 u32 int_src
, int_enable
, int_current
;
466 unsigned int handled
= 0;
468 spin_lock_irqsave(&bp
->lock
, flags
);
470 /* read and clear the DNET irq (clear on read) */
471 int_src
= dnet_readl(bp
, INTR_SRC
);
472 int_enable
= dnet_readl(bp
, INTR_ENB
);
473 int_current
= int_src
& int_enable
;
475 /* restart the queue if we had stopped it for TX fifo almost full */
476 if (int_current
& DNET_INTR_SRC_TX_FIFOAE
) {
477 int_enable
= dnet_readl(bp
, INTR_ENB
);
478 int_enable
&= ~DNET_INTR_ENB_TX_FIFOAE
;
479 dnet_writel(bp
, int_enable
, INTR_ENB
);
480 netif_wake_queue(dev
);
484 /* RX FIFO error checking */
486 (DNET_INTR_SRC_RX_CMDFIFOFF
| DNET_INTR_SRC_RX_DATAFIFOFF
)) {
487 printk(KERN_ERR
"%s: RX fifo error %x, irq %x\n", __func__
,
488 dnet_readl(bp
, RX_STATUS
), int_current
);
489 /* we can only flush the RX FIFOs */
490 dnet_writel(bp
, DNET_SYS_CTL_RXFIFOFLUSH
, SYS_CTL
);
492 dnet_writel(bp
, 0, SYS_CTL
);
496 /* TX FIFO error checking */
498 (DNET_INTR_SRC_TX_FIFOFULL
| DNET_INTR_SRC_TX_DISCFRM
)) {
499 printk(KERN_ERR
"%s: TX fifo error %x, irq %x\n", __func__
,
500 dnet_readl(bp
, TX_STATUS
), int_current
);
501 /* we can only flush the TX FIFOs */
502 dnet_writel(bp
, DNET_SYS_CTL_TXFIFOFLUSH
, SYS_CTL
);
504 dnet_writel(bp
, 0, SYS_CTL
);
508 if (int_current
& DNET_INTR_SRC_RX_CMDFIFOAF
) {
509 if (napi_schedule_prep(&bp
->napi
)) {
511 * There's no point taking any more interrupts
512 * until we have processed the buffers
514 /* Disable Rx interrupts and schedule NAPI poll */
515 int_enable
= dnet_readl(bp
, INTR_ENB
);
516 int_enable
&= ~DNET_INTR_SRC_RX_CMDFIFOAF
;
517 dnet_writel(bp
, int_enable
, INTR_ENB
);
518 __napi_schedule(&bp
->napi
);
524 pr_debug("%s: irq %x remains\n", __func__
, int_current
);
526 spin_unlock_irqrestore(&bp
->lock
, flags
);
528 return IRQ_RETVAL(handled
);
532 static inline void dnet_print_skb(struct sk_buff
*skb
)
535 printk(KERN_DEBUG PFX
"data:");
536 for (k
= 0; k
< skb
->len
; k
++)
537 printk(" %02x", (unsigned int)skb
->data
[k
]);
541 #define dnet_print_skb(skb) do {} while (0)
544 static netdev_tx_t
dnet_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
547 struct dnet
*bp
= netdev_priv(dev
);
548 u32 tx_status
, irq_enable
;
549 unsigned int len
, i
, tx_cmd
, wrsz
;
553 tx_status
= dnet_readl(bp
, TX_STATUS
);
555 pr_debug("start_xmit: len %u head %p data %p\n",
556 skb
->len
, skb
->head
, skb
->data
);
559 /* frame size (words) */
560 len
= (skb
->len
+ 3) >> 2;
562 spin_lock_irqsave(&bp
->lock
, flags
);
564 tx_status
= dnet_readl(bp
, TX_STATUS
);
566 bufp
= (unsigned int *)(((unsigned long) skb
->data
) & ~0x3UL
);
567 wrsz
= (u32
) skb
->len
+ 3;
568 wrsz
+= ((unsigned long) skb
->data
) & 0x3;
570 tx_cmd
= ((((unsigned long)(skb
->data
)) & 0x03) << 16) | (u32
) skb
->len
;
572 /* check if there is enough room for the current frame */
573 if (wrsz
< (DNET_FIFO_SIZE
- dnet_readl(bp
, TX_FIFO_WCNT
))) {
574 for (i
= 0; i
< wrsz
; i
++)
575 dnet_writel(bp
, *bufp
++, TX_DATA_FIFO
);
578 * inform MAC that a packet's written and ready to be
581 dnet_writel(bp
, tx_cmd
, TX_LEN_FIFO
);
584 if (dnet_readl(bp
, TX_FIFO_WCNT
) > DNET_FIFO_TX_DATA_AF_TH
) {
585 netif_stop_queue(dev
);
586 tx_status
= dnet_readl(bp
, INTR_SRC
);
587 irq_enable
= dnet_readl(bp
, INTR_ENB
);
588 irq_enable
|= DNET_INTR_ENB_TX_FIFOAE
;
589 dnet_writel(bp
, irq_enable
, INTR_ENB
);
592 skb_tx_timestamp(skb
);
594 /* free the buffer */
597 spin_unlock_irqrestore(&bp
->lock
, flags
);
602 static void dnet_reset_hw(struct dnet
*bp
)
604 /* put ts_mac in IDLE state i.e. disable rx/tx */
605 dnet_writew_mac(bp
, DNET_INTERNAL_MODE_REG
, DNET_INTERNAL_MODE_FCEN
);
608 * RX FIFO almost full threshold: only cmd FIFO almost full is
609 * implemented for RX side
611 dnet_writel(bp
, DNET_FIFO_RX_CMD_AF_TH
, RX_FIFO_TH
);
613 * TX FIFO almost empty threshold: only data FIFO almost empty
614 * is implemented for TX side
616 dnet_writel(bp
, DNET_FIFO_TX_DATA_AE_TH
, TX_FIFO_TH
);
618 /* flush rx/tx fifos */
619 dnet_writel(bp
, DNET_SYS_CTL_RXFIFOFLUSH
| DNET_SYS_CTL_TXFIFOFLUSH
,
622 dnet_writel(bp
, 0, SYS_CTL
);
625 static void dnet_init_hw(struct dnet
*bp
)
630 __dnet_set_hwaddr(bp
);
632 config
= dnet_readw_mac(bp
, DNET_INTERNAL_RXTX_CONTROL_REG
);
634 if (bp
->dev
->flags
& IFF_PROMISC
)
635 /* Copy All Frames */
636 config
|= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC
;
637 if (!(bp
->dev
->flags
& IFF_BROADCAST
))
639 config
|= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST
;
641 config
|= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE
|
642 DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST
|
643 DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL
|
644 DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS
;
646 dnet_writew_mac(bp
, DNET_INTERNAL_RXTX_CONTROL_REG
, config
);
648 /* clear irq before enabling them */
649 config
= dnet_readl(bp
, INTR_SRC
);
651 /* enable RX/TX interrupt, recv packet ready interrupt */
652 dnet_writel(bp
, DNET_INTR_ENB_GLOBAL_ENABLE
| DNET_INTR_ENB_RX_SUMMARY
|
653 DNET_INTR_ENB_TX_SUMMARY
| DNET_INTR_ENB_RX_FIFOERR
|
654 DNET_INTR_ENB_RX_ERROR
| DNET_INTR_ENB_RX_FIFOFULL
|
655 DNET_INTR_ENB_TX_FIFOFULL
| DNET_INTR_ENB_TX_DISCFRM
|
656 DNET_INTR_ENB_RX_PKTRDY
, INTR_ENB
);
659 static int dnet_open(struct net_device
*dev
)
661 struct dnet
*bp
= netdev_priv(dev
);
663 /* if the phy is not yet register, retry later */
667 if (!is_valid_ether_addr(dev
->dev_addr
))
668 return -EADDRNOTAVAIL
;
670 napi_enable(&bp
->napi
);
673 phy_start_aneg(bp
->phy_dev
);
675 /* schedule a link state check */
676 phy_start(bp
->phy_dev
);
678 netif_start_queue(dev
);
683 static int dnet_close(struct net_device
*dev
)
685 struct dnet
*bp
= netdev_priv(dev
);
687 netif_stop_queue(dev
);
688 napi_disable(&bp
->napi
);
691 phy_stop(bp
->phy_dev
);
694 netif_carrier_off(dev
);
699 static inline void dnet_print_pretty_hwstats(struct dnet_stats
*hwstat
)
701 pr_debug("%s\n", __func__
);
702 pr_debug("----------------------------- RX statistics "
703 "-------------------------------\n");
704 pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat
->rx_pkt_ignr
);
705 pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat
->rx_len_chk_err
);
706 pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat
->rx_lng_frm
);
707 pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat
->rx_shrt_frm
);
708 pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat
->rx_ipg_viol
);
709 pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat
->rx_crc_err
);
710 pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat
->rx_ok_pkt
);
711 pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat
->rx_ctl_frm
);
712 pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat
->rx_pause_frm
);
713 pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat
->rx_multicast
);
714 pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat
->rx_broadcast
);
715 pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat
->rx_vlan_tag
);
716 pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat
->rx_pre_shrink
);
717 pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat
->rx_drib_nib
);
718 pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat
->rx_unsup_opcd
);
719 pr_debug("RX_BYTE_CNT %-8x\n", hwstat
->rx_byte
);
720 pr_debug("----------------------------- TX statistics "
721 "-------------------------------\n");
722 pr_debug("TX_UNICAST_CNT %-8x\n", hwstat
->tx_unicast
);
723 pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat
->tx_pause_frm
);
724 pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat
->tx_multicast
);
725 pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat
->tx_brdcast
);
726 pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat
->tx_vlan_tag
);
727 pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat
->tx_bad_fcs
);
728 pr_debug("TX_JUMBO_CNT %-8x\n", hwstat
->tx_jumbo
);
729 pr_debug("TX_BYTE_CNT %-8x\n", hwstat
->tx_byte
);
732 static struct net_device_stats
*dnet_get_stats(struct net_device
*dev
)
735 struct dnet
*bp
= netdev_priv(dev
);
736 struct net_device_stats
*nstat
= &dev
->stats
;
737 struct dnet_stats
*hwstat
= &bp
->hw_stats
;
739 /* read stats from hardware */
740 dnet_update_stats(bp
);
742 /* Convert HW stats into netdevice stats */
743 nstat
->rx_errors
= (hwstat
->rx_len_chk_err
+
744 hwstat
->rx_lng_frm
+ hwstat
->rx_shrt_frm
+
745 /* ignore IGP violation error
746 hwstat->rx_ipg_viol + */
748 hwstat
->rx_pre_shrink
+
749 hwstat
->rx_drib_nib
+ hwstat
->rx_unsup_opcd
);
750 nstat
->tx_errors
= hwstat
->tx_bad_fcs
;
751 nstat
->rx_length_errors
= (hwstat
->rx_len_chk_err
+
753 hwstat
->rx_shrt_frm
+ hwstat
->rx_pre_shrink
);
754 nstat
->rx_crc_errors
= hwstat
->rx_crc_err
;
755 nstat
->rx_frame_errors
= hwstat
->rx_pre_shrink
+ hwstat
->rx_drib_nib
;
756 nstat
->rx_packets
= hwstat
->rx_ok_pkt
;
757 nstat
->tx_packets
= (hwstat
->tx_unicast
+
758 hwstat
->tx_multicast
+ hwstat
->tx_brdcast
);
759 nstat
->rx_bytes
= hwstat
->rx_byte
;
760 nstat
->tx_bytes
= hwstat
->tx_byte
;
761 nstat
->multicast
= hwstat
->rx_multicast
;
762 nstat
->rx_missed_errors
= hwstat
->rx_pkt_ignr
;
764 dnet_print_pretty_hwstats(hwstat
);
769 static int dnet_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
771 struct dnet
*bp
= netdev_priv(dev
);
772 struct phy_device
*phydev
= bp
->phy_dev
;
777 return phy_ethtool_gset(phydev
, cmd
);
780 static int dnet_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
782 struct dnet
*bp
= netdev_priv(dev
);
783 struct phy_device
*phydev
= bp
->phy_dev
;
788 return phy_ethtool_sset(phydev
, cmd
);
791 static int dnet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
793 struct dnet
*bp
= netdev_priv(dev
);
794 struct phy_device
*phydev
= bp
->phy_dev
;
796 if (!netif_running(dev
))
802 return phy_mii_ioctl(phydev
, rq
, cmd
);
805 static void dnet_get_drvinfo(struct net_device
*dev
,
806 struct ethtool_drvinfo
*info
)
808 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
809 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
810 strlcpy(info
->bus_info
, "0", sizeof(info
->bus_info
));
813 static const struct ethtool_ops dnet_ethtool_ops
= {
814 .get_settings
= dnet_get_settings
,
815 .set_settings
= dnet_set_settings
,
816 .get_drvinfo
= dnet_get_drvinfo
,
817 .get_link
= ethtool_op_get_link
,
820 static const struct net_device_ops dnet_netdev_ops
= {
821 .ndo_open
= dnet_open
,
822 .ndo_stop
= dnet_close
,
823 .ndo_get_stats
= dnet_get_stats
,
824 .ndo_start_xmit
= dnet_start_xmit
,
825 .ndo_do_ioctl
= dnet_ioctl
,
826 .ndo_set_mac_address
= eth_mac_addr
,
827 .ndo_validate_addr
= eth_validate_addr
,
828 .ndo_change_mtu
= eth_change_mtu
,
831 static int __devinit
dnet_probe(struct platform_device
*pdev
)
833 struct resource
*res
;
834 struct net_device
*dev
;
836 struct phy_device
*phydev
;
838 unsigned int mem_base
, mem_size
, irq
;
840 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
842 dev_err(&pdev
->dev
, "no mmio resource defined\n");
845 mem_base
= res
->start
;
846 mem_size
= resource_size(res
);
847 irq
= platform_get_irq(pdev
, 0);
849 if (!request_mem_region(mem_base
, mem_size
, DRV_NAME
)) {
850 dev_err(&pdev
->dev
, "no memory region available\n");
856 dev
= alloc_etherdev(sizeof(*bp
));
858 dev_err(&pdev
->dev
, "etherdev alloc failed, aborting.\n");
859 goto err_out_release_mem
;
862 /* TODO: Actually, we have some interesting features... */
865 bp
= netdev_priv(dev
);
868 platform_set_drvdata(pdev
, dev
);
869 SET_NETDEV_DEV(dev
, &pdev
->dev
);
871 spin_lock_init(&bp
->lock
);
873 bp
->regs
= ioremap(mem_base
, mem_size
);
875 dev_err(&pdev
->dev
, "failed to map registers, aborting.\n");
877 goto err_out_free_dev
;
881 err
= request_irq(dev
->irq
, dnet_interrupt
, 0, DRV_NAME
, dev
);
883 dev_err(&pdev
->dev
, "Unable to request IRQ %d (error %d)\n",
885 goto err_out_iounmap
;
888 dev
->netdev_ops
= &dnet_netdev_ops
;
889 netif_napi_add(dev
, &bp
->napi
, dnet_poll
, 64);
890 dev
->ethtool_ops
= &dnet_ethtool_ops
;
892 dev
->base_addr
= (unsigned long)bp
->regs
;
894 bp
->capabilities
= dnet_readl(bp
, VERCAPS
) & DNET_CAPS_MASK
;
898 if (!is_valid_ether_addr(dev
->dev_addr
)) {
899 /* choose a random ethernet address */
900 random_ether_addr(dev
->dev_addr
);
901 __dnet_set_hwaddr(bp
);
904 err
= register_netdev(dev
);
906 dev_err(&pdev
->dev
, "Cannot register net device, aborting.\n");
907 goto err_out_free_irq
;
910 /* register the PHY board fixup (for Marvell 88E1111) */
911 err
= phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
912 dnet_phy_marvell_fixup
);
913 /* we can live without it, so just issue a warning */
915 dev_warn(&pdev
->dev
, "Cannot register PHY board fixup.\n");
917 err
= dnet_mii_init(bp
);
919 goto err_out_unregister_netdev
;
921 dev_info(&pdev
->dev
, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
922 bp
->regs
, mem_base
, dev
->irq
, dev
->dev_addr
);
923 dev_info(&pdev
->dev
, "has %smdio, %sirq, %sgigabit, %sdma\n",
924 (bp
->capabilities
& DNET_HAS_MDIO
) ? "" : "no ",
925 (bp
->capabilities
& DNET_HAS_IRQ
) ? "" : "no ",
926 (bp
->capabilities
& DNET_HAS_GIGABIT
) ? "" : "no ",
927 (bp
->capabilities
& DNET_HAS_DMA
) ? "" : "no ");
928 phydev
= bp
->phy_dev
;
929 dev_info(&pdev
->dev
, "attached PHY driver [%s] "
930 "(mii_bus:phy_addr=%s, irq=%d)\n",
931 phydev
->drv
->name
, dev_name(&phydev
->dev
), phydev
->irq
);
935 err_out_unregister_netdev
:
936 unregister_netdev(dev
);
938 free_irq(dev
->irq
, dev
);
944 release_mem_region(mem_base
, mem_size
);
949 static int __devexit
dnet_remove(struct platform_device
*pdev
)
952 struct net_device
*dev
;
955 dev
= platform_get_drvdata(pdev
);
958 bp
= netdev_priv(dev
);
960 phy_disconnect(bp
->phy_dev
);
961 mdiobus_unregister(bp
->mii_bus
);
962 kfree(bp
->mii_bus
->irq
);
963 mdiobus_free(bp
->mii_bus
);
964 unregister_netdev(dev
);
965 free_irq(dev
->irq
, dev
);
973 static struct platform_driver dnet_driver
= {
975 .remove
= __devexit_p(dnet_remove
),
981 module_platform_driver(dnet_driver
);
983 MODULE_LICENSE("GPL");
984 MODULE_DESCRIPTION("Dave DNET Ethernet driver");
985 MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
986 "Matteo Vit <matteo.vit@dave.eu>");