spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / ethernet / intel / ixgbevf / regs.h
blobdebd8c0e1f28df74db51c04809beeff3f2a9855c
1 /*******************************************************************************
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #ifndef _IXGBEVF_REGS_H_
29 #define _IXGBEVF_REGS_H_
31 #define IXGBE_VFCTRL 0x00000
32 #define IXGBE_VFSTATUS 0x00008
33 #define IXGBE_VFLINKS 0x00010
34 #define IXGBE_VFFRTIMER 0x00048
35 #define IXGBE_VFRXMEMWRAP 0x03190
36 #define IXGBE_VTEICR 0x00100
37 #define IXGBE_VTEICS 0x00104
38 #define IXGBE_VTEIMS 0x00108
39 #define IXGBE_VTEIMC 0x0010C
40 #define IXGBE_VTEIAC 0x00110
41 #define IXGBE_VTEIAM 0x00114
42 #define IXGBE_VTEITR(x) (0x00820 + (4 * (x)))
43 #define IXGBE_VTIVAR(x) (0x00120 + (4 * (x)))
44 #define IXGBE_VTIVAR_MISC 0x00140
45 #define IXGBE_VTRSCINT(x) (0x00180 + (4 * (x)))
46 #define IXGBE_VFRDBAL(x) (0x01000 + (0x40 * (x)))
47 #define IXGBE_VFRDBAH(x) (0x01004 + (0x40 * (x)))
48 #define IXGBE_VFRDLEN(x) (0x01008 + (0x40 * (x)))
49 #define IXGBE_VFRDH(x) (0x01010 + (0x40 * (x)))
50 #define IXGBE_VFRDT(x) (0x01018 + (0x40 * (x)))
51 #define IXGBE_VFRXDCTL(x) (0x01028 + (0x40 * (x)))
52 #define IXGBE_VFSRRCTL(x) (0x01014 + (0x40 * (x)))
53 #define IXGBE_VFRSCCTL(x) (0x0102C + (0x40 * (x)))
54 #define IXGBE_VFPSRTYPE 0x00300
55 #define IXGBE_VFTDBAL(x) (0x02000 + (0x40 * (x)))
56 #define IXGBE_VFTDBAH(x) (0x02004 + (0x40 * (x)))
57 #define IXGBE_VFTDLEN(x) (0x02008 + (0x40 * (x)))
58 #define IXGBE_VFTDH(x) (0x02010 + (0x40 * (x)))
59 #define IXGBE_VFTDT(x) (0x02018 + (0x40 * (x)))
60 #define IXGBE_VFTXDCTL(x) (0x02028 + (0x40 * (x)))
61 #define IXGBE_VFTDWBAL(x) (0x02038 + (0x40 * (x)))
62 #define IXGBE_VFTDWBAH(x) (0x0203C + (0x40 * (x)))
63 #define IXGBE_VFDCA_RXCTRL(x) (0x0100C + (0x40 * (x)))
64 #define IXGBE_VFDCA_TXCTRL(x) (0x0200c + (0x40 * (x)))
65 #define IXGBE_VFGPRC 0x0101C
66 #define IXGBE_VFGPTC 0x0201C
67 #define IXGBE_VFGORC_LSB 0x01020
68 #define IXGBE_VFGORC_MSB 0x01024
69 #define IXGBE_VFGOTC_LSB 0x02020
70 #define IXGBE_VFGOTC_MSB 0x02024
71 #define IXGBE_VFMPRC 0x01034
73 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
75 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
77 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
78 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
80 #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
81 readl((a)->hw_addr + (reg) + ((offset) << 2)))
83 #define IXGBE_WRITE_FLUSH(a) (IXGBE_READ_REG(a, IXGBE_VFSTATUS))
85 #endif /* _IXGBEVF_REGS_H_ */