spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / ethernet / mellanox / mlx4 / en_cq.c
blob00b81272e31404eb47a59bccd3d9012565df2f26
1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
34 #include <linux/mlx4/cq.h>
35 #include <linux/mlx4/qp.h>
36 #include <linux/mlx4/cmd.h>
38 #include "mlx4_en.h"
40 static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event)
42 return;
46 int mlx4_en_create_cq(struct mlx4_en_priv *priv,
47 struct mlx4_en_cq *cq,
48 int entries, int ring, enum cq_type mode)
50 struct mlx4_en_dev *mdev = priv->mdev;
51 int err;
53 cq->size = entries;
54 cq->buf_size = cq->size * sizeof(struct mlx4_cqe);
56 cq->ring = ring;
57 cq->is_tx = mode;
58 spin_lock_init(&cq->lock);
60 err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres,
61 cq->buf_size, 2 * PAGE_SIZE);
62 if (err)
63 return err;
65 err = mlx4_en_map_buffer(&cq->wqres.buf);
66 if (err)
67 mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
68 else
69 cq->buf = (struct mlx4_cqe *) cq->wqres.buf.direct.buf;
71 return err;
74 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
75 int cq_idx)
77 struct mlx4_en_dev *mdev = priv->mdev;
78 int err = 0;
79 char name[25];
81 cq->dev = mdev->pndev[priv->port];
82 cq->mcq.set_ci_db = cq->wqres.db.db;
83 cq->mcq.arm_db = cq->wqres.db.db + 1;
84 *cq->mcq.set_ci_db = 0;
85 *cq->mcq.arm_db = 0;
86 memset(cq->buf, 0, cq->buf_size);
88 if (cq->is_tx == RX) {
89 if (mdev->dev->caps.comp_pool) {
90 if (!cq->vector) {
91 sprintf(name, "%s-%d", priv->dev->name,
92 cq->ring);
93 /* Set IRQ for specific name (per ring) */
94 if (mlx4_assign_eq(mdev->dev, name, &cq->vector)) {
95 cq->vector = (cq->ring + 1 + priv->port)
96 % mdev->dev->caps.num_comp_vectors;
97 mlx4_warn(mdev, "Failed Assigning an EQ to "
98 "%s ,Falling back to legacy EQ's\n",
99 name);
102 } else {
103 cq->vector = (cq->ring + 1 + priv->port) %
104 mdev->dev->caps.num_comp_vectors;
106 } else {
107 /* For TX we use the same irq per
108 ring we assigned for the RX */
109 struct mlx4_en_cq *rx_cq;
111 cq_idx = cq_idx % priv->rx_ring_num;
112 rx_cq = &priv->rx_cq[cq_idx];
113 cq->vector = rx_cq->vector;
116 if (!cq->is_tx)
117 cq->size = priv->rx_ring[cq->ring].actual_size;
119 err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt, &mdev->priv_uar,
120 cq->wqres.db.dma, &cq->mcq, cq->vector, 0);
121 if (err)
122 return err;
124 cq->mcq.comp = cq->is_tx ? mlx4_en_tx_irq : mlx4_en_rx_irq;
125 cq->mcq.event = mlx4_en_cq_event;
127 if (cq->is_tx) {
128 init_timer(&cq->timer);
129 cq->timer.function = mlx4_en_poll_tx_cq;
130 cq->timer.data = (unsigned long) cq;
131 } else {
132 netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq, 64);
133 napi_enable(&cq->napi);
136 return 0;
139 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
141 struct mlx4_en_dev *mdev = priv->mdev;
143 mlx4_en_unmap_buffer(&cq->wqres.buf);
144 mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
145 if (priv->mdev->dev->caps.comp_pool && cq->vector)
146 mlx4_release_eq(priv->mdev->dev, cq->vector);
147 cq->vector = 0;
148 cq->buf_size = 0;
149 cq->buf = NULL;
152 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
154 struct mlx4_en_dev *mdev = priv->mdev;
156 if (cq->is_tx)
157 del_timer(&cq->timer);
158 else {
159 napi_disable(&cq->napi);
160 netif_napi_del(&cq->napi);
163 mlx4_cq_free(mdev->dev, &cq->mcq);
166 /* Set rx cq moderation parameters */
167 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
169 return mlx4_cq_modify(priv->mdev->dev, &cq->mcq,
170 cq->moder_cnt, cq->moder_time);
173 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
175 mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map,
176 &priv->mdev->uar_lock);
178 return 0;