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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / ethernet / sfc / falcon.c
blob8ae1ebd3539796870baaab658c07ea45e0eccac3
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "nic.h"
25 #include "regs.h"
26 #include "io.h"
27 #include "phy.h"
28 #include "workarounds.h"
29
30 /* Hardware control for SFC4000 (aka Falcon). */
31
32 static const unsigned int
33 /* "Large" EEPROM device: Atmel AT25640 or similar
34 * 8 KB, 16-bit address, 32 B write block */
35 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
36 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
37 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
38 /* Default flash device: Atmel AT25F1024
39 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
40 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
41 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
42 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
43 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
44 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
45
46 /**************************************************************************
47 *
48 * I2C bus - this is a bit-bashing interface using GPIO pins
49 * Note that it uses the output enables to tristate the outputs
50 * SDA is the data pin and SCL is the clock
51 *
52 **************************************************************************
53 */
54 static void falcon_setsda(void *data, int state)
55 {
56 struct efx_nic *efx = (struct efx_nic *)data;
57 efx_oword_t reg;
58
59 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
60 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
61 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
62 }
63
64 static void falcon_setscl(void *data, int state)
65 {
66 struct efx_nic *efx = (struct efx_nic *)data;
67 efx_oword_t reg;
68
69 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
70 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
71 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
72 }
73
74 static int falcon_getsda(void *data)
75 {
76 struct efx_nic *efx = (struct efx_nic *)data;
77 efx_oword_t reg;
78
79 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
80 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
81 }
82
83 static int falcon_getscl(void *data)
84 {
85 struct efx_nic *efx = (struct efx_nic *)data;
86 efx_oword_t reg;
87
88 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
89 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
90 }
91
92 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
93 .setsda = falcon_setsda,
94 .setscl = falcon_setscl,
95 .getsda = falcon_getsda,
96 .getscl = falcon_getscl,
97 .udelay = 5,
98 /* Wait up to 50 ms for slave to let us pull SCL high */
99 .timeout = DIV_ROUND_UP(HZ, 20),
100 };
101
102 static void falcon_push_irq_moderation(struct efx_channel *channel)
103 {
104 efx_dword_t timer_cmd;
105 struct efx_nic *efx = channel->efx;
106
107 BUILD_BUG_ON(EFX_IRQ_MOD_MAX > (1 << FRF_AB_TC_TIMER_VAL_WIDTH));
108
109 /* Set timer register */
110 if (channel->irq_moderation) {
111 EFX_POPULATE_DWORD_2(timer_cmd,
112 FRF_AB_TC_TIMER_MODE,
113 FFE_BB_TIMER_MODE_INT_HLDOFF,
114 FRF_AB_TC_TIMER_VAL,
115 channel->irq_moderation - 1);
116 } else {
117 EFX_POPULATE_DWORD_2(timer_cmd,
118 FRF_AB_TC_TIMER_MODE,
119 FFE_BB_TIMER_MODE_DIS,
120 FRF_AB_TC_TIMER_VAL, 0);
121 }
122 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
123 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
124 channel->channel);
125 }
126
127 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
128
129 static void falcon_prepare_flush(struct efx_nic *efx)
130 {
131 falcon_deconfigure_mac_wrapper(efx);
132
133 /* Wait for the tx and rx fifo's to get to the next packet boundary
134 * (~1ms without back-pressure), then to drain the remainder of the
135 * fifo's at data path speeds (negligible), with a healthy margin. */
136 msleep(10);
137 }
138
139 /* Acknowledge a legacy interrupt from Falcon
140 *
141 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
142 *
143 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
144 * BIU. Interrupt acknowledge is read sensitive so must write instead
145 * (then read to ensure the BIU collector is flushed)
146 *
147 * NB most hardware supports MSI interrupts
148 */
149 inline void falcon_irq_ack_a1(struct efx_nic *efx)
150 {
151 efx_dword_t reg;
152
153 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
154 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
155 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
156 }
157
158
159 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
160 {
161 struct efx_nic *efx = dev_id;
162 efx_oword_t *int_ker = efx->irq_status.addr;
163 int syserr;
164 int queues;
165
166 /* Check to see if this is our interrupt. If it isn't, we
167 * exit without having touched the hardware.
168 */
169 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
170 netif_vdbg(efx, intr, efx->net_dev,
171 "IRQ %d on CPU %d not for me\n", irq,
172 raw_smp_processor_id());
173 return IRQ_NONE;
174 }
175 efx->last_irq_cpu = raw_smp_processor_id();
176 netif_vdbg(efx, intr, efx->net_dev,
177 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
178 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
179
180 /* Determine interrupting queues, clear interrupt status
181 * register and acknowledge the device interrupt.
182 */
183 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
184 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
185
186 /* Check to see if we have a serious error condition */
187 if (queues & (1U << efx->fatal_irq_level)) {
188 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
189 if (unlikely(syserr))
190 return efx_nic_fatal_interrupt(efx);
191 }
192
193 EFX_ZERO_OWORD(*int_ker);
194 wmb(); /* Ensure the vector is cleared before interrupt ack */
195 falcon_irq_ack_a1(efx);
196
197 if (queues & 1)
198 efx_schedule_channel(efx_get_channel(efx, 0));
199 if (queues & 2)
200 efx_schedule_channel(efx_get_channel(efx, 1));
201 return IRQ_HANDLED;
202 }
203 /**************************************************************************
204 *
205 * EEPROM/flash
206 *
207 **************************************************************************
208 */
209
210 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
211
212 static int falcon_spi_poll(struct efx_nic *efx)
213 {
214 efx_oword_t reg;
215 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
216 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
217 }
218
219 /* Wait for SPI command completion */
220 static int falcon_spi_wait(struct efx_nic *efx)
221 {
222 /* Most commands will finish quickly, so we start polling at
223 * very short intervals. Sometimes the command may have to
224 * wait for VPD or expansion ROM access outside of our
225 * control, so we allow up to 100 ms. */
226 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
227 int i;
228
229 for (i = 0; i < 10; i++) {
230 if (!falcon_spi_poll(efx))
231 return 0;
232 udelay(10);
233 }
234
235 for (;;) {
236 if (!falcon_spi_poll(efx))
237 return 0;
238 if (time_after_eq(jiffies, timeout)) {
239 netif_err(efx, hw, efx->net_dev,
240 "timed out waiting for SPI\n");
241 return -ETIMEDOUT;
242 }
243 schedule_timeout_uninterruptible(1);
244 }
245 }
246
247 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
248 unsigned int command, int address,
249 const void *in, void *out, size_t len)
250 {
251 bool addressed = (address >= 0);
252 bool reading = (out != NULL);
253 efx_oword_t reg;
254 int rc;
255
256 /* Input validation */
257 if (len > FALCON_SPI_MAX_LEN)
258 return -EINVAL;
259
260 /* Check that previous command is not still running */
261 rc = falcon_spi_poll(efx);
262 if (rc)
263 return rc;
264
265 /* Program address register, if we have an address */
266 if (addressed) {
267 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
268 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
269 }
270
271 /* Program data register, if we have data */
272 if (in != NULL) {
273 memcpy(&reg, in, len);
274 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
275 }
276
277 /* Issue read/write command */
278 EFX_POPULATE_OWORD_7(reg,
279 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
280 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
281 FRF_AB_EE_SPI_HCMD_DABCNT, len,
282 FRF_AB_EE_SPI_HCMD_READ, reading,
283 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
284 FRF_AB_EE_SPI_HCMD_ADBCNT,
285 (addressed ? spi->addr_len : 0),
286 FRF_AB_EE_SPI_HCMD_ENC, command);
287 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
288
289 /* Wait for read/write to complete */
290 rc = falcon_spi_wait(efx);
291 if (rc)
292 return rc;
293
294 /* Read data */
295 if (out != NULL) {
296 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
297 memcpy(out, &reg, len);
298 }
299
300 return 0;
301 }
302
303 static size_t
304 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
305 {
306 return min(FALCON_SPI_MAX_LEN,
307 (spi->block_size - (start & (spi->block_size - 1))));
308 }
309
310 static inline u8
311 efx_spi_munge_command(const struct efx_spi_device *spi,
312 const u8 command, const unsigned int address)
313 {
314 return command | (((address >> 8) & spi->munge_address) << 3);
315 }
316
317 /* Wait up to 10 ms for buffered write completion */
318 int
319 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
320 {
321 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
322 u8 status;
323 int rc;
324
325 for (;;) {
326 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
327 &status, sizeof(status));
328 if (rc)
329 return rc;
330 if (!(status & SPI_STATUS_NRDY))
331 return 0;
332 if (time_after_eq(jiffies, timeout)) {
333 netif_err(efx, hw, efx->net_dev,
334 "SPI write timeout on device %d"
335 " last status=0x%02x\n",
336 spi->device_id, status);
337 return -ETIMEDOUT;
338 }
339 schedule_timeout_uninterruptible(1);
340 }
341 }
342
343 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
344 loff_t start, size_t len, size_t *retlen, u8 *buffer)
345 {
346 size_t block_len, pos = 0;
347 unsigned int command;
348 int rc = 0;
349
350 while (pos < len) {
351 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
352
353 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
354 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
355 buffer + pos, block_len);
356 if (rc)
357 break;
358 pos += block_len;
359
360 /* Avoid locking up the system */
361 cond_resched();
362 if (signal_pending(current)) {
363 rc = -EINTR;
364 break;
365 }
366 }
367
368 if (retlen)
369 *retlen = pos;
370 return rc;
371 }
372
373 int
374 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
375 loff_t start, size_t len, size_t *retlen, const u8 *buffer)
376 {
377 u8 verify_buffer[FALCON_SPI_MAX_LEN];
378 size_t block_len, pos = 0;
379 unsigned int command;
380 int rc = 0;
381
382 while (pos < len) {
383 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
384 if (rc)
385 break;
386
387 block_len = min(len - pos,
388 falcon_spi_write_limit(spi, start + pos));
389 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
390 rc = falcon_spi_cmd(efx, spi, command, start + pos,
391 buffer + pos, NULL, block_len);
392 if (rc)
393 break;
394
395 rc = falcon_spi_wait_write(efx, spi);
396 if (rc)
397 break;
398
399 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
400 rc = falcon_spi_cmd(efx, spi, command, start + pos,
401 NULL, verify_buffer, block_len);
402 if (memcmp(verify_buffer, buffer + pos, block_len)) {
403 rc = -EIO;
404 break;
405 }
406
407 pos += block_len;
408
409 /* Avoid locking up the system */
410 cond_resched();
411 if (signal_pending(current)) {
412 rc = -EINTR;
413 break;
414 }
415 }
416
417 if (retlen)
418 *retlen = pos;
419 return rc;
420 }
421
422 /**************************************************************************
423 *
424 * MAC wrapper
425 *
426 **************************************************************************
427 */
428
429 static void falcon_push_multicast_hash(struct efx_nic *efx)
430 {
431 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
432
433 WARN_ON(!mutex_is_locked(&efx->mac_lock));
434
435 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
436 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
437 }
438
439 static void falcon_reset_macs(struct efx_nic *efx)
440 {
441 struct falcon_nic_data *nic_data = efx->nic_data;
442 efx_oword_t reg, mac_ctrl;
443 int count;
444
445 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
446 /* It's not safe to use GLB_CTL_REG to reset the
447 * macs, so instead use the internal MAC resets
448 */
449 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
450 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
451
452 for (count = 0; count < 10000; count++) {
453 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
454 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
455 0)
456 return;
457 udelay(10);
458 }
459
460 netif_err(efx, hw, efx->net_dev,
461 "timed out waiting for XMAC core reset\n");
462 }
463
464 /* Mac stats will fail whist the TX fifo is draining */
465 WARN_ON(nic_data->stats_disable_count == 0);
466
467 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
468 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
469 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
470
471 efx_reado(efx, &reg, FR_AB_GLB_CTL);
472 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
473 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
474 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
475 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
476
477 count = 0;
478 while (1) {
479 efx_reado(efx, &reg, FR_AB_GLB_CTL);
480 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
481 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
482 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
483 netif_dbg(efx, hw, efx->net_dev,
484 "Completed MAC reset after %d loops\n",
485 count);
486 break;
487 }
488 if (count > 20) {
489 netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
490 break;
491 }
492 count++;
493 udelay(10);
494 }
495
496 /* Ensure the correct MAC is selected before statistics
497 * are re-enabled by the caller */
498 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
499
500 falcon_setup_xaui(efx);
501 }
502
503 void falcon_drain_tx_fifo(struct efx_nic *efx)
504 {
505 efx_oword_t reg;
506
507 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
508 (efx->loopback_mode != LOOPBACK_NONE))
509 return;
510
511 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
512 /* There is no point in draining more than once */
513 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
514 return;
515
516 falcon_reset_macs(efx);
517 }
518
519 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
520 {
521 efx_oword_t reg;
522
523 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
524 return;
525
526 /* Isolate the MAC -> RX */
527 efx_reado(efx, &reg, FR_AZ_RX_CFG);
528 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
529 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
530
531 /* Isolate TX -> MAC */
532 falcon_drain_tx_fifo(efx);
533 }
534
535 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
536 {
537 struct efx_link_state *link_state = &efx->link_state;
538 efx_oword_t reg;
539 int link_speed, isolate;
540
541 isolate = !!ACCESS_ONCE(efx->reset_pending);
542
543 switch (link_state->speed) {
544 case 10000: link_speed = 3; break;
545 case 1000: link_speed = 2; break;
546 case 100: link_speed = 1; break;
547 default: link_speed = 0; break;
548 }
549 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
550 * as advertised. Disable to ensure packets are not
551 * indefinitely held and TX queue can be flushed at any point
552 * while the link is down. */
553 EFX_POPULATE_OWORD_5(reg,
554 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
555 FRF_AB_MAC_BCAD_ACPT, 1,
556 FRF_AB_MAC_UC_PROM, efx->promiscuous,
557 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
558 FRF_AB_MAC_SPEED, link_speed);
559 /* On B0, MAC backpressure can be disabled and packets get
560 * discarded. */
561 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
562 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
563 !link_state->up || isolate);
564 }
565
566 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
567
568 /* Restore the multicast hash registers. */
569 falcon_push_multicast_hash(efx);
570
571 efx_reado(efx, &reg, FR_AZ_RX_CFG);
572 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
573 * initialisation but it may read back as 0) */
574 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
575 /* Unisolate the MAC -> RX */
576 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
577 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
578 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
579 }
580
581 static void falcon_stats_request(struct efx_nic *efx)
582 {
583 struct falcon_nic_data *nic_data = efx->nic_data;
584 efx_oword_t reg;
585
586 WARN_ON(nic_data->stats_pending);
587 WARN_ON(nic_data->stats_disable_count);
588
589 if (nic_data->stats_dma_done == NULL)
590 return; /* no mac selected */
591
592 *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
593 nic_data->stats_pending = true;
594 wmb(); /* ensure done flag is clear */
595
596 /* Initiate DMA transfer of stats */
597 EFX_POPULATE_OWORD_2(reg,
598 FRF_AB_MAC_STAT_DMA_CMD, 1,
599 FRF_AB_MAC_STAT_DMA_ADR,
600 efx->stats_buffer.dma_addr);
601 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
602
603 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
604 }
605
606 static void falcon_stats_complete(struct efx_nic *efx)
607 {
608 struct falcon_nic_data *nic_data = efx->nic_data;
609
610 if (!nic_data->stats_pending)
611 return;
612
613 nic_data->stats_pending = false;
614 if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
615 rmb(); /* read the done flag before the stats */
616 efx->mac_op->update_stats(efx);
617 } else {
618 netif_err(efx, hw, efx->net_dev,
619 "timed out waiting for statistics\n");
620 }
621 }
622
623 static void falcon_stats_timer_func(unsigned long context)
624 {
625 struct efx_nic *efx = (struct efx_nic *)context;
626 struct falcon_nic_data *nic_data = efx->nic_data;
627
628 spin_lock(&efx->stats_lock);
629
630 falcon_stats_complete(efx);
631 if (nic_data->stats_disable_count == 0)
632 falcon_stats_request(efx);
633
634 spin_unlock(&efx->stats_lock);
635 }
636
637 static bool falcon_loopback_link_poll(struct efx_nic *efx)
638 {
639 struct efx_link_state old_state = efx->link_state;
640
641 WARN_ON(!mutex_is_locked(&efx->mac_lock));
642 WARN_ON(!LOOPBACK_INTERNAL(efx));
643
644 efx->link_state.fd = true;
645 efx->link_state.fc = efx->wanted_fc;
646 efx->link_state.up = true;
647 efx->link_state.speed = 10000;
648
649 return !efx_link_state_equal(&efx->link_state, &old_state);
650 }
651
652 static int falcon_reconfigure_port(struct efx_nic *efx)
653 {
654 int rc;
655
656 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
657
658 /* Poll the PHY link state *before* reconfiguring it. This means we
659 * will pick up the correct speed (in loopback) to select the correct
660 * MAC.
661 */
662 if (LOOPBACK_INTERNAL(efx))
663 falcon_loopback_link_poll(efx);
664 else
665 efx->phy_op->poll(efx);
666
667 falcon_stop_nic_stats(efx);
668 falcon_deconfigure_mac_wrapper(efx);
669
670 falcon_reset_macs(efx);
671
672 efx->phy_op->reconfigure(efx);
673 rc = efx->mac_op->reconfigure(efx);
674 BUG_ON(rc);
675
676 falcon_start_nic_stats(efx);
677
678 /* Synchronise efx->link_state with the kernel */
679 efx_link_status_changed(efx);
680
681 return 0;
682 }
683
684 /**************************************************************************
685 *
686 * PHY access via GMII
687 *
688 **************************************************************************
689 */
690
691 /* Wait for GMII access to complete */
692 static int falcon_gmii_wait(struct efx_nic *efx)
693 {
694 efx_oword_t md_stat;
695 int count;
696
697 /* wait up to 50ms - taken max from datasheet */
698 for (count = 0; count < 5000; count++) {
699 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
700 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
701 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
702 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
703 netif_err(efx, hw, efx->net_dev,
704 "error from GMII access "
705 EFX_OWORD_FMT"\n",
706 EFX_OWORD_VAL(md_stat));
707 return -EIO;
708 }
709 return 0;
710 }
711 udelay(10);
712 }
713 netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
714 return -ETIMEDOUT;
715 }
716
717 /* Write an MDIO register of a PHY connected to Falcon. */
718 static int falcon_mdio_write(struct net_device *net_dev,
719 int prtad, int devad, u16 addr, u16 value)
720 {
721 struct efx_nic *efx = netdev_priv(net_dev);
722 struct falcon_nic_data *nic_data = efx->nic_data;
723 efx_oword_t reg;
724 int rc;
725
726 netif_vdbg(efx, hw, efx->net_dev,
727 "writing MDIO %d register %d.%d with 0x%04x\n",
728 prtad, devad, addr, value);
729
730 mutex_lock(&nic_data->mdio_lock);
731
732 /* Check MDIO not currently being accessed */
733 rc = falcon_gmii_wait(efx);
734 if (rc)
735 goto out;
736
737 /* Write the address/ID register */
738 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
739 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
740
741 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
742 FRF_AB_MD_DEV_ADR, devad);
743 efx_writeo(efx, &reg, FR_AB_MD_ID);
744
745 /* Write data */
746 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
747 efx_writeo(efx, &reg, FR_AB_MD_TXD);
748
749 EFX_POPULATE_OWORD_2(reg,
750 FRF_AB_MD_WRC, 1,
751 FRF_AB_MD_GC, 0);
752 efx_writeo(efx, &reg, FR_AB_MD_CS);
753
754 /* Wait for data to be written */
755 rc = falcon_gmii_wait(efx);
756 if (rc) {
757 /* Abort the write operation */
758 EFX_POPULATE_OWORD_2(reg,
759 FRF_AB_MD_WRC, 0,
760 FRF_AB_MD_GC, 1);
761 efx_writeo(efx, &reg, FR_AB_MD_CS);
762 udelay(10);
763 }
764
765 out:
766 mutex_unlock(&nic_data->mdio_lock);
767 return rc;
768 }
769
770 /* Read an MDIO register of a PHY connected to Falcon. */
771 static int falcon_mdio_read(struct net_device *net_dev,
772 int prtad, int devad, u16 addr)
773 {
774 struct efx_nic *efx = netdev_priv(net_dev);
775 struct falcon_nic_data *nic_data = efx->nic_data;
776 efx_oword_t reg;
777 int rc;
778
779 mutex_lock(&nic_data->mdio_lock);
780
781 /* Check MDIO not currently being accessed */
782 rc = falcon_gmii_wait(efx);
783 if (rc)
784 goto out;
785
786 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
787 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
788
789 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
790 FRF_AB_MD_DEV_ADR, devad);
791 efx_writeo(efx, &reg, FR_AB_MD_ID);
792
793 /* Request data to be read */
794 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
795 efx_writeo(efx, &reg, FR_AB_MD_CS);
796
797 /* Wait for data to become available */
798 rc = falcon_gmii_wait(efx);
799 if (rc == 0) {
800 efx_reado(efx, &reg, FR_AB_MD_RXD);
801 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
802 netif_vdbg(efx, hw, efx->net_dev,
803 "read from MDIO %d register %d.%d, got %04x\n",
804 prtad, devad, addr, rc);
805 } else {
806 /* Abort the read operation */
807 EFX_POPULATE_OWORD_2(reg,
808 FRF_AB_MD_RIC, 0,
809 FRF_AB_MD_GC, 1);
810 efx_writeo(efx, &reg, FR_AB_MD_CS);
811
812 netif_dbg(efx, hw, efx->net_dev,
813 "read from MDIO %d register %d.%d, got error %d\n",
814 prtad, devad, addr, rc);
815 }
816
817 out:
818 mutex_unlock(&nic_data->mdio_lock);
819 return rc;
820 }
821
822 /* This call is responsible for hooking in the MAC and PHY operations */
823 static int falcon_probe_port(struct efx_nic *efx)
824 {
825 struct falcon_nic_data *nic_data = efx->nic_data;
826 int rc;
827
828 switch (efx->phy_type) {
829 case PHY_TYPE_SFX7101:
830 efx->phy_op = &falcon_sfx7101_phy_ops;
831 break;
832 case PHY_TYPE_QT2022C2:
833 case PHY_TYPE_QT2025C:
834 efx->phy_op = &falcon_qt202x_phy_ops;
835 break;
836 case PHY_TYPE_TXC43128:
837 efx->phy_op = &falcon_txc_phy_ops;
838 break;
839 default:
840 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
841 efx->phy_type);
842 return -ENODEV;
843 }
844
845 /* Fill out MDIO structure and loopback modes */
846 mutex_init(&nic_data->mdio_lock);
847 efx->mdio.mdio_read = falcon_mdio_read;
848 efx->mdio.mdio_write = falcon_mdio_write;
849 rc = efx->phy_op->probe(efx);
850 if (rc != 0)
851 return rc;
852
853 /* Initial assumption */
854 efx->link_state.speed = 10000;
855 efx->link_state.fd = true;
856
857 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
858 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
859 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
860 else
861 efx->wanted_fc = EFX_FC_RX;
862 if (efx->mdio.mmds & MDIO_DEVS_AN)
863 efx->wanted_fc |= EFX_FC_AUTO;
864
865 /* Allocate buffer for stats */
866 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
867 FALCON_MAC_STATS_SIZE);
868 if (rc)
869 return rc;
870 netif_dbg(efx, probe, efx->net_dev,
871 "stats buffer at %llx (virt %p phys %llx)\n",
872 (u64)efx->stats_buffer.dma_addr,
873 efx->stats_buffer.addr,
874 (u64)virt_to_phys(efx->stats_buffer.addr));
875 nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset;
876
877 return 0;
878 }
879
880 static void falcon_remove_port(struct efx_nic *efx)
881 {
882 efx->phy_op->remove(efx);
883 efx_nic_free_buffer(efx, &efx->stats_buffer);
884 }
885
886 /* Global events are basically PHY events */
887 static bool
888 falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
889 {
890 struct efx_nic *efx = channel->efx;
891 struct falcon_nic_data *nic_data = efx->nic_data;
892
893 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
894 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
895 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
896 /* Ignored */
897 return true;
898
899 if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
900 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
901 nic_data->xmac_poll_required = true;
902 return true;
903 }
904
905 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
906 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
907 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
908 netif_err(efx, rx_err, efx->net_dev,
909 "channel %d seen global RX_RESET event. Resetting.\n",
910 channel->channel);
911
912 atomic_inc(&efx->rx_reset);
913 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
914 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
915 return true;
916 }
917
918 return false;
919 }
920
921 /**************************************************************************
922 *
923 * Falcon test code
924 *
925 **************************************************************************/
926
927 static int
928 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
929 {
930 struct falcon_nic_data *nic_data = efx->nic_data;
931 struct falcon_nvconfig *nvconfig;
932 struct efx_spi_device *spi;
933 void *region;
934 int rc, magic_num, struct_ver;
935 __le16 *word, *limit;
936 u32 csum;
937
938 if (efx_spi_present(&nic_data->spi_flash))
939 spi = &nic_data->spi_flash;
940 else if (efx_spi_present(&nic_data->spi_eeprom))
941 spi = &nic_data->spi_eeprom;
942 else
943 return -EINVAL;
944
945 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
946 if (!region)
947 return -ENOMEM;
948 nvconfig = region + FALCON_NVCONFIG_OFFSET;
949
950 mutex_lock(&nic_data->spi_lock);
951 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
952 mutex_unlock(&nic_data->spi_lock);
953 if (rc) {
954 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
955 efx_spi_present(&nic_data->spi_flash) ?
956 "flash" : "EEPROM");
957 rc = -EIO;
958 goto out;
959 }
960
961 magic_num = le16_to_cpu(nvconfig->board_magic_num);
962 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
963
964 rc = -EINVAL;
965 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
966 netif_err(efx, hw, efx->net_dev,
967 "NVRAM bad magic 0x%x\n", magic_num);
968 goto out;
969 }
970 if (struct_ver < 2) {
971 netif_err(efx, hw, efx->net_dev,
972 "NVRAM has ancient version 0x%x\n", struct_ver);
973 goto out;
974 } else if (struct_ver < 4) {
975 word = &nvconfig->board_magic_num;
976 limit = (__le16 *) (nvconfig + 1);
977 } else {
978 word = region;
979 limit = region + FALCON_NVCONFIG_END;
980 }
981 for (csum = 0; word < limit; ++word)
982 csum += le16_to_cpu(*word);
983
984 if (~csum & 0xffff) {
985 netif_err(efx, hw, efx->net_dev,
986 "NVRAM has incorrect checksum\n");
987 goto out;
988 }
989
990 rc = 0;
991 if (nvconfig_out)
992 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
993
994 out:
995 kfree(region);
996 return rc;
997 }
998
999 static int falcon_test_nvram(struct efx_nic *efx)
1000 {
1001 return falcon_read_nvram(efx, NULL);
1002 }
1003
1004 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
1005 { FR_AZ_ADR_REGION,
1006 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1007 { FR_AZ_RX_CFG,
1008 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1009 { FR_AZ_TX_CFG,
1010 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1011 { FR_AZ_TX_RESERVED,
1012 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1013 { FR_AB_MAC_CTRL,
1014 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1015 { FR_AZ_SRM_TX_DC_CFG,
1016 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1017 { FR_AZ_RX_DC_CFG,
1018 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1019 { FR_AZ_RX_DC_PF_WM,
1020 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1021 { FR_BZ_DP_CTRL,
1022 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1023 { FR_AB_GM_CFG2,
1024 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1025 { FR_AB_GMF_CFG0,
1026 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1027 { FR_AB_XM_GLB_CFG,
1028 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1029 { FR_AB_XM_TX_CFG,
1030 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1031 { FR_AB_XM_RX_CFG,
1032 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1033 { FR_AB_XM_RX_PARAM,
1034 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1035 { FR_AB_XM_FC,
1036 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1037 { FR_AB_XM_ADR_LO,
1038 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1039 { FR_AB_XX_SD_CTL,
1040 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1041 };
1042
1043 static int falcon_b0_test_registers(struct efx_nic *efx)
1044 {
1045 return efx_nic_test_registers(efx, falcon_b0_register_tests,
1046 ARRAY_SIZE(falcon_b0_register_tests));
1047 }
1048
1049 /**************************************************************************
1050 *
1051 * Device reset
1052 *
1053 **************************************************************************
1054 */
1055
1056 static enum reset_type falcon_map_reset_reason(enum reset_type reason)
1057 {
1058 switch (reason) {
1059 case RESET_TYPE_RX_RECOVERY:
1060 case RESET_TYPE_RX_DESC_FETCH:
1061 case RESET_TYPE_TX_DESC_FETCH:
1062 case RESET_TYPE_TX_SKIP:
1063 /* These can occasionally occur due to hardware bugs.
1064 * We try to reset without disrupting the link.
1065 */
1066 return RESET_TYPE_INVISIBLE;
1067 default:
1068 return RESET_TYPE_ALL;
1069 }
1070 }
1071
1072 static int falcon_map_reset_flags(u32 *flags)
1073 {
1074 enum {
1075 FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER |
1076 ETH_RESET_OFFLOAD | ETH_RESET_MAC),
1077 FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY,
1078 FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ,
1079 };
1080
1081 if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) {
1082 *flags &= ~FALCON_RESET_WORLD;
1083 return RESET_TYPE_WORLD;
1084 }
1085
1086 if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) {
1087 *flags &= ~FALCON_RESET_ALL;
1088 return RESET_TYPE_ALL;
1089 }
1090
1091 if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) {
1092 *flags &= ~FALCON_RESET_INVISIBLE;
1093 return RESET_TYPE_INVISIBLE;
1094 }
1095
1096 return -EINVAL;
1097 }
1098
1099 /* Resets NIC to known state. This routine must be called in process
1100 * context and is allowed to sleep. */
1101 static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1102 {
1103 struct falcon_nic_data *nic_data = efx->nic_data;
1104 efx_oword_t glb_ctl_reg_ker;
1105 int rc;
1106
1107 netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1108 RESET_TYPE(method));
1109
1110 /* Initiate device reset */
1111 if (method == RESET_TYPE_WORLD) {
1112 rc = pci_save_state(efx->pci_dev);
1113 if (rc) {
1114 netif_err(efx, drv, efx->net_dev,
1115 "failed to backup PCI state of primary "
1116 "function prior to hardware reset\n");
1117 goto fail1;
1118 }
1119 if (efx_nic_is_dual_func(efx)) {
1120 rc = pci_save_state(nic_data->pci_dev2);
1121 if (rc) {
1122 netif_err(efx, drv, efx->net_dev,
1123 "failed to backup PCI state of "
1124 "secondary function prior to "
1125 "hardware reset\n");
1126 goto fail2;
1127 }
1128 }
1129
1130 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1131 FRF_AB_EXT_PHY_RST_DUR,
1132 FFE_AB_EXT_PHY_RST_DUR_10240US,
1133 FRF_AB_SWRST, 1);
1134 } else {
1135 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1136 /* exclude PHY from "invisible" reset */
1137 FRF_AB_EXT_PHY_RST_CTL,
1138 method == RESET_TYPE_INVISIBLE,
1139 /* exclude EEPROM/flash and PCIe */
1140 FRF_AB_PCIE_CORE_RST_CTL, 1,
1141 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1142 FRF_AB_PCIE_SD_RST_CTL, 1,
1143 FRF_AB_EE_RST_CTL, 1,
1144 FRF_AB_EXT_PHY_RST_DUR,
1145 FFE_AB_EXT_PHY_RST_DUR_10240US,
1146 FRF_AB_SWRST, 1);
1147 }
1148 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1149
1150 netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1151 schedule_timeout_uninterruptible(HZ / 20);
1152
1153 /* Restore PCI configuration if needed */
1154 if (method == RESET_TYPE_WORLD) {
1155 if (efx_nic_is_dual_func(efx))
1156 pci_restore_state(nic_data->pci_dev2);
1157 pci_restore_state(efx->pci_dev);
1158 netif_dbg(efx, drv, efx->net_dev,
1159 "successfully restored PCI config\n");
1160 }
1161
1162 /* Assert that reset complete */
1163 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1164 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1165 rc = -ETIMEDOUT;
1166 netif_err(efx, hw, efx->net_dev,
1167 "timed out waiting for hardware reset\n");
1168 goto fail3;
1169 }
1170 netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
1171
1172 return 0;
1173
1174 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1175 fail2:
1176 pci_restore_state(efx->pci_dev);
1177 fail1:
1178 fail3:
1179 return rc;
1180 }
1181
1182 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1183 {
1184 struct falcon_nic_data *nic_data = efx->nic_data;
1185 int rc;
1186
1187 mutex_lock(&nic_data->spi_lock);
1188 rc = __falcon_reset_hw(efx, method);
1189 mutex_unlock(&nic_data->spi_lock);
1190
1191 return rc;
1192 }
1193
1194 static void falcon_monitor(struct efx_nic *efx)
1195 {
1196 bool link_changed;
1197 int rc;
1198
1199 BUG_ON(!mutex_is_locked(&efx->mac_lock));
1200
1201 rc = falcon_board(efx)->type->monitor(efx);
1202 if (rc) {
1203 netif_err(efx, hw, efx->net_dev,
1204 "Board sensor %s; shutting down PHY\n",
1205 (rc == -ERANGE) ? "reported fault" : "failed");
1206 efx->phy_mode |= PHY_MODE_LOW_POWER;
1207 rc = __efx_reconfigure_port(efx);
1208 WARN_ON(rc);
1209 }
1210
1211 if (LOOPBACK_INTERNAL(efx))
1212 link_changed = falcon_loopback_link_poll(efx);
1213 else
1214 link_changed = efx->phy_op->poll(efx);
1215
1216 if (link_changed) {
1217 falcon_stop_nic_stats(efx);
1218 falcon_deconfigure_mac_wrapper(efx);
1219
1220 falcon_reset_macs(efx);
1221 rc = efx->mac_op->reconfigure(efx);
1222 BUG_ON(rc);
1223
1224 falcon_start_nic_stats(efx);
1225
1226 efx_link_status_changed(efx);
1227 }
1228
1229 falcon_poll_xmac(efx);
1230 }
1231
1232 /* Zeroes out the SRAM contents. This routine must be called in
1233 * process context and is allowed to sleep.
1234 */
1235 static int falcon_reset_sram(struct efx_nic *efx)
1236 {
1237 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1238 int count;
1239
1240 /* Set the SRAM wake/sleep GPIO appropriately. */
1241 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1242 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1243 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1244 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1245
1246 /* Initiate SRAM reset */
1247 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1248 FRF_AZ_SRM_INIT_EN, 1,
1249 FRF_AZ_SRM_NB_SZ, 0);
1250 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1251
1252 /* Wait for SRAM reset to complete */
1253 count = 0;
1254 do {
1255 netif_dbg(efx, hw, efx->net_dev,
1256 "waiting for SRAM reset (attempt %d)...\n", count);
1257
1258 /* SRAM reset is slow; expect around 16ms */
1259 schedule_timeout_uninterruptible(HZ / 50);
1260
1261 /* Check for reset complete */
1262 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1263 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1264 netif_dbg(efx, hw, efx->net_dev,
1265 "SRAM reset complete\n");
1266
1267 return 0;
1268 }
1269 } while (++count < 20); /* wait up to 0.4 sec */
1270
1271 netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
1272 return -ETIMEDOUT;
1273 }
1274
1275 static void falcon_spi_device_init(struct efx_nic *efx,
1276 struct efx_spi_device *spi_device,
1277 unsigned int device_id, u32 device_type)
1278 {
1279 if (device_type != 0) {
1280 spi_device->device_id = device_id;
1281 spi_device->size =
1282 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1283 spi_device->addr_len =
1284 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1285 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1286 spi_device->addr_len == 1);
1287 spi_device->erase_command =
1288 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1289 spi_device->erase_size =
1290 1 << SPI_DEV_TYPE_FIELD(device_type,
1291 SPI_DEV_TYPE_ERASE_SIZE);
1292 spi_device->block_size =
1293 1 << SPI_DEV_TYPE_FIELD(device_type,
1294 SPI_DEV_TYPE_BLOCK_SIZE);
1295 } else {
1296 spi_device->size = 0;
1297 }
1298 }
1299
1300 /* Extract non-volatile configuration */
1301 static int falcon_probe_nvconfig(struct efx_nic *efx)
1302 {
1303 struct falcon_nic_data *nic_data = efx->nic_data;
1304 struct falcon_nvconfig *nvconfig;
1305 int rc;
1306
1307 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1308 if (!nvconfig)
1309 return -ENOMEM;
1310
1311 rc = falcon_read_nvram(efx, nvconfig);
1312 if (rc)
1313 goto out;
1314
1315 efx->phy_type = nvconfig->board_v2.port0_phy_type;
1316 efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
1317
1318 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1319 falcon_spi_device_init(
1320 efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1321 le32_to_cpu(nvconfig->board_v3
1322 .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
1323 falcon_spi_device_init(
1324 efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1325 le32_to_cpu(nvconfig->board_v3
1326 .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
1327 }
1328
1329 /* Read the MAC addresses */
1330 memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN);
1331
1332 netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
1333 efx->phy_type, efx->mdio.prtad);
1334
1335 rc = falcon_probe_board(efx,
1336 le16_to_cpu(nvconfig->board_v2.board_revision));
1337 out:
1338 kfree(nvconfig);
1339 return rc;
1340 }
1341
1342 /* Probe all SPI devices on the NIC */
1343 static void falcon_probe_spi_devices(struct efx_nic *efx)
1344 {
1345 struct falcon_nic_data *nic_data = efx->nic_data;
1346 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1347 int boot_dev;
1348
1349 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1350 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1351 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1352
1353 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1354 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1355 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1356 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
1357 boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
1358 "flash" : "EEPROM");
1359 } else {
1360 /* Disable VPD and set clock dividers to safe
1361 * values for initial programming. */
1362 boot_dev = -1;
1363 netif_dbg(efx, probe, efx->net_dev,
1364 "Booted from internal ASIC settings;"
1365 " setting SPI config\n");
1366 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1367 /* 125 MHz / 7 ~= 20 MHz */
1368 FRF_AB_EE_SF_CLOCK_DIV, 7,
1369 /* 125 MHz / 63 ~= 2 MHz */
1370 FRF_AB_EE_EE_CLOCK_DIV, 63);
1371 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1372 }
1373
1374 mutex_init(&nic_data->spi_lock);
1375
1376 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1377 falcon_spi_device_init(efx, &nic_data->spi_flash,
1378 FFE_AB_SPI_DEVICE_FLASH,
1379 default_flash_type);
1380 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1381 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
1382 FFE_AB_SPI_DEVICE_EEPROM,
1383 large_eeprom_type);
1384 }
1385
1386 static int falcon_probe_nic(struct efx_nic *efx)
1387 {
1388 struct falcon_nic_data *nic_data;
1389 struct falcon_board *board;
1390 int rc;
1391
1392 /* Allocate storage for hardware specific data */
1393 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1394 if (!nic_data)
1395 return -ENOMEM;
1396 efx->nic_data = nic_data;
1397
1398 rc = -ENODEV;
1399
1400 if (efx_nic_fpga_ver(efx) != 0) {
1401 netif_err(efx, probe, efx->net_dev,
1402 "Falcon FPGA not supported\n");
1403 goto fail1;
1404 }
1405
1406 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1407 efx_oword_t nic_stat;
1408 struct pci_dev *dev;
1409 u8 pci_rev = efx->pci_dev->revision;
1410
1411 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1412 netif_err(efx, probe, efx->net_dev,
1413 "Falcon rev A0 not supported\n");
1414 goto fail1;
1415 }
1416 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1417 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1418 netif_err(efx, probe, efx->net_dev,
1419 "Falcon rev A1 1G not supported\n");
1420 goto fail1;
1421 }
1422 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1423 netif_err(efx, probe, efx->net_dev,
1424 "Falcon rev A1 PCI-X not supported\n");
1425 goto fail1;
1426 }
1427
1428 dev = pci_dev_get(efx->pci_dev);
1429 while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE,
1430 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1,
1431 dev))) {
1432 if (dev->bus == efx->pci_dev->bus &&
1433 dev->devfn == efx->pci_dev->devfn + 1) {
1434 nic_data->pci_dev2 = dev;
1435 break;
1436 }
1437 }
1438 if (!nic_data->pci_dev2) {
1439 netif_err(efx, probe, efx->net_dev,
1440 "failed to find secondary function\n");
1441 rc = -ENODEV;
1442 goto fail2;
1443 }
1444 }
1445
1446 /* Now we can reset the NIC */
1447 rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
1448 if (rc) {
1449 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
1450 goto fail3;
1451 }
1452
1453 /* Allocate memory for INT_KER */
1454 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1455 if (rc)
1456 goto fail4;
1457 BUG_ON(efx->irq_status.dma_addr & 0x0f);
1458
1459 netif_dbg(efx, probe, efx->net_dev,
1460 "INT_KER at %llx (virt %p phys %llx)\n",
1461 (u64)efx->irq_status.dma_addr,
1462 efx->irq_status.addr,
1463 (u64)virt_to_phys(efx->irq_status.addr));
1464
1465 falcon_probe_spi_devices(efx);
1466
1467 /* Read in the non-volatile configuration */
1468 rc = falcon_probe_nvconfig(efx);
1469 if (rc) {
1470 if (rc == -EINVAL)
1471 netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
1472 goto fail5;
1473 }
1474
1475 /* Initialise I2C adapter */
1476 board = falcon_board(efx);
1477 board->i2c_adap.owner = THIS_MODULE;
1478 board->i2c_data = falcon_i2c_bit_operations;
1479 board->i2c_data.data = efx;
1480 board->i2c_adap.algo_data = &board->i2c_data;
1481 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1482 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1483 sizeof(board->i2c_adap.name));
1484 rc = i2c_bit_add_bus(&board->i2c_adap);
1485 if (rc)
1486 goto fail5;
1487
1488 rc = falcon_board(efx)->type->init(efx);
1489 if (rc) {
1490 netif_err(efx, probe, efx->net_dev,
1491 "failed to initialise board\n");
1492 goto fail6;
1493 }
1494
1495 nic_data->stats_disable_count = 1;
1496 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1497 (unsigned long)efx);
1498
1499 return 0;
1500
1501 fail6:
1502 BUG_ON(i2c_del_adapter(&board->i2c_adap));
1503 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1504 fail5:
1505 efx_nic_free_buffer(efx, &efx->irq_status);
1506 fail4:
1507 fail3:
1508 if (nic_data->pci_dev2) {
1509 pci_dev_put(nic_data->pci_dev2);
1510 nic_data->pci_dev2 = NULL;
1511 }
1512 fail2:
1513 fail1:
1514 kfree(efx->nic_data);
1515 return rc;
1516 }
1517
1518 static void falcon_init_rx_cfg(struct efx_nic *efx)
1519 {
1520 /* Prior to Siena the RX DMA engine will split each frame at
1521 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1522 * be so large that that never happens. */
1523 const unsigned huge_buf_size = (3 * 4096) >> 5;
1524 /* RX control FIFO thresholds (32 entries) */
1525 const unsigned ctrl_xon_thr = 20;
1526 const unsigned ctrl_xoff_thr = 25;
1527 efx_oword_t reg;
1528
1529 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1530 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1531 /* Data FIFO size is 5.5K */
1532 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1533 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1534 huge_buf_size);
1535 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
1536 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
1537 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1538 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1539 } else {
1540 /* Data FIFO size is 80K; register fields moved */
1541 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1542 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1543 huge_buf_size);
1544 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
1545 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
1546 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
1547 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1548 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1549 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1550
1551 /* Enable hash insertion. This is broken for the
1552 * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1553 * IPv4 hashes. */
1554 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
1555 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
1556 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
1557 }
1558 /* Always enable XOFF signal from RX FIFO. We enable
1559 * or disable transmission of pause frames at the MAC. */
1560 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1561 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1562 }
1563
1564 /* This call performs hardware-specific global initialisation, such as
1565 * defining the descriptor cache sizes and number of RSS channels.
1566 * It does not set up any buffers, descriptor rings or event queues.
1567 */
1568 static int falcon_init_nic(struct efx_nic *efx)
1569 {
1570 efx_oword_t temp;
1571 int rc;
1572
1573 /* Use on-chip SRAM */
1574 efx_reado(efx, &temp, FR_AB_NIC_STAT);
1575 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1576 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1577
1578 rc = falcon_reset_sram(efx);
1579 if (rc)
1580 return rc;
1581
1582 /* Clear the parity enables on the TX data fifos as
1583 * they produce false parity errors because of timing issues
1584 */
1585 if (EFX_WORKAROUND_5129(efx)) {
1586 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1587 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1588 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1589 }
1590
1591 if (EFX_WORKAROUND_7244(efx)) {
1592 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1593 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1594 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1595 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1596 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1597 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1598 }
1599
1600 /* XXX This is documented only for Falcon A0/A1 */
1601 /* Setup RX. Wait for descriptor is broken and must
1602 * be disabled. RXDP recovery shouldn't be needed, but is.
1603 */
1604 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1605 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1606 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1607 if (EFX_WORKAROUND_5583(efx))
1608 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1609 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1610
1611 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1612 * descriptors (which is bad).
1613 */
1614 efx_reado(efx, &temp, FR_AZ_TX_CFG);
1615 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1616 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1617
1618 falcon_init_rx_cfg(efx);
1619
1620 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1621 /* Set hash key for IPv4 */
1622 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
1623 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
1624
1625 /* Set destination of both TX and RX Flush events */
1626 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1627 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1628 }
1629
1630 efx_nic_init_common(efx);
1631
1632 return 0;
1633 }
1634
1635 static void falcon_remove_nic(struct efx_nic *efx)
1636 {
1637 struct falcon_nic_data *nic_data = efx->nic_data;
1638 struct falcon_board *board = falcon_board(efx);
1639 int rc;
1640
1641 board->type->fini(efx);
1642
1643 /* Remove I2C adapter and clear it in preparation for a retry */
1644 rc = i2c_del_adapter(&board->i2c_adap);
1645 BUG_ON(rc);
1646 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1647
1648 efx_nic_free_buffer(efx, &efx->irq_status);
1649
1650 __falcon_reset_hw(efx, RESET_TYPE_ALL);
1651
1652 /* Release the second function after the reset */
1653 if (nic_data->pci_dev2) {
1654 pci_dev_put(nic_data->pci_dev2);
1655 nic_data->pci_dev2 = NULL;
1656 }
1657
1658 /* Tear down the private nic state */
1659 kfree(efx->nic_data);
1660 efx->nic_data = NULL;
1661 }
1662
1663 static void falcon_update_nic_stats(struct efx_nic *efx)
1664 {
1665 struct falcon_nic_data *nic_data = efx->nic_data;
1666 efx_oword_t cnt;
1667
1668 if (nic_data->stats_disable_count)
1669 return;
1670
1671 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1672 efx->n_rx_nodesc_drop_cnt +=
1673 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1674
1675 if (nic_data->stats_pending &&
1676 *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1677 nic_data->stats_pending = false;
1678 rmb(); /* read the done flag before the stats */
1679 efx->mac_op->update_stats(efx);
1680 }
1681 }
1682
1683 void falcon_start_nic_stats(struct efx_nic *efx)
1684 {
1685 struct falcon_nic_data *nic_data = efx->nic_data;
1686
1687 spin_lock_bh(&efx->stats_lock);
1688 if (--nic_data->stats_disable_count == 0)
1689 falcon_stats_request(efx);
1690 spin_unlock_bh(&efx->stats_lock);
1691 }
1692
1693 void falcon_stop_nic_stats(struct efx_nic *efx)
1694 {
1695 struct falcon_nic_data *nic_data = efx->nic_data;
1696 int i;
1697
1698 might_sleep();
1699
1700 spin_lock_bh(&efx->stats_lock);
1701 ++nic_data->stats_disable_count;
1702 spin_unlock_bh(&efx->stats_lock);
1703
1704 del_timer_sync(&nic_data->stats_timer);
1705
1706 /* Wait enough time for the most recent transfer to
1707 * complete. */
1708 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1709 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1710 break;
1711 msleep(1);
1712 }
1713
1714 spin_lock_bh(&efx->stats_lock);
1715 falcon_stats_complete(efx);
1716 spin_unlock_bh(&efx->stats_lock);
1717 }
1718
1719 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1720 {
1721 falcon_board(efx)->type->set_id_led(efx, mode);
1722 }
1723
1724 /**************************************************************************
1725 *
1726 * Wake on LAN
1727 *
1728 **************************************************************************
1729 */
1730
1731 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1732 {
1733 wol->supported = 0;
1734 wol->wolopts = 0;
1735 memset(&wol->sopass, 0, sizeof(wol->sopass));
1736 }
1737
1738 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1739 {
1740 if (type != 0)
1741 return -EINVAL;
1742 return 0;
1743 }
1744
1745 /**************************************************************************
1746 *
1747 * Revision-dependent attributes used by efx.c and nic.c
1748 *
1749 **************************************************************************
1750 */
1751
1752 const struct efx_nic_type falcon_a1_nic_type = {
1753 .probe = falcon_probe_nic,
1754 .remove = falcon_remove_nic,
1755 .init = falcon_init_nic,
1756 .fini = efx_port_dummy_op_void,
1757 .monitor = falcon_monitor,
1758 .map_reset_reason = falcon_map_reset_reason,
1759 .map_reset_flags = falcon_map_reset_flags,
1760 .reset = falcon_reset_hw,
1761 .probe_port = falcon_probe_port,
1762 .remove_port = falcon_remove_port,
1763 .handle_global_event = falcon_handle_global_event,
1764 .prepare_flush = falcon_prepare_flush,
1765 .update_stats = falcon_update_nic_stats,
1766 .start_stats = falcon_start_nic_stats,
1767 .stop_stats = falcon_stop_nic_stats,
1768 .set_id_led = falcon_set_id_led,
1769 .push_irq_moderation = falcon_push_irq_moderation,
1770 .push_multicast_hash = falcon_push_multicast_hash,
1771 .reconfigure_port = falcon_reconfigure_port,
1772 .get_wol = falcon_get_wol,
1773 .set_wol = falcon_set_wol,
1774 .resume_wol = efx_port_dummy_op_void,
1775 .test_nvram = falcon_test_nvram,
1776 .default_mac_ops = &falcon_xmac_operations,
1777
1778 .revision = EFX_REV_FALCON_A1,
1779 .mem_map_size = 0x20000,
1780 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1781 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1782 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1783 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1784 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1785 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1786 .rx_buffer_padding = 0x24,
1787 .max_interrupt_mode = EFX_INT_MODE_MSI,
1788 .phys_addr_channels = 4,
1789 .tx_dc_base = 0x130000,
1790 .rx_dc_base = 0x100000,
1791 .offload_features = NETIF_F_IP_CSUM,
1792 };
1793
1794 const struct efx_nic_type falcon_b0_nic_type = {
1795 .probe = falcon_probe_nic,
1796 .remove = falcon_remove_nic,
1797 .init = falcon_init_nic,
1798 .fini = efx_port_dummy_op_void,
1799 .monitor = falcon_monitor,
1800 .map_reset_reason = falcon_map_reset_reason,
1801 .map_reset_flags = falcon_map_reset_flags,
1802 .reset = falcon_reset_hw,
1803 .probe_port = falcon_probe_port,
1804 .remove_port = falcon_remove_port,
1805 .handle_global_event = falcon_handle_global_event,
1806 .prepare_flush = falcon_prepare_flush,
1807 .update_stats = falcon_update_nic_stats,
1808 .start_stats = falcon_start_nic_stats,
1809 .stop_stats = falcon_stop_nic_stats,
1810 .set_id_led = falcon_set_id_led,
1811 .push_irq_moderation = falcon_push_irq_moderation,
1812 .push_multicast_hash = falcon_push_multicast_hash,
1813 .reconfigure_port = falcon_reconfigure_port,
1814 .get_wol = falcon_get_wol,
1815 .set_wol = falcon_set_wol,
1816 .resume_wol = efx_port_dummy_op_void,
1817 .test_registers = falcon_b0_test_registers,
1818 .test_nvram = falcon_test_nvram,
1819 .default_mac_ops = &falcon_xmac_operations,
1820
1821 .revision = EFX_REV_FALCON_B0,
1822 /* Map everything up to and including the RSS indirection
1823 * table. Don't map MSI-X table, MSI-X PBA since Linux
1824 * requires that they not be mapped. */
1825 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1826 FR_BZ_RX_INDIRECTION_TBL_STEP *
1827 FR_BZ_RX_INDIRECTION_TBL_ROWS),
1828 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1829 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1830 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1831 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1832 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1833 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1834 .rx_buffer_hash_size = 0x10,
1835 .rx_buffer_padding = 0,
1836 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1837 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1838 * interrupt handler only supports 32
1839 * channels */
1840 .tx_dc_base = 0x130000,
1841 .rx_dc_base = 0x100000,
1842 .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
1843 };
1844