drivers/net/ethernet/stmicro/stmmac/common.h

   1 /*******************************************************************************
   2   STMMAC Common Header File
   3
   4   Copyright (C) 2007-2009  STMicroelectronics Ltd
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  23 *******************************************************************************/
  24
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/phy.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  31 #define STMMAC_VLAN_TAG_USED
  32 #include <linux/if_vlan.h>
  33 #endif
  34
  35 #include "descs.h"
  36 #include "mmc.h"
  37
  38 #undef CHIP_DEBUG_PRINT
  39 /* Turn-on extra printk debug for MAC core, dma and descriptors */
  40 /* #define CHIP_DEBUG_PRINT */
  41
  42 #ifdef CHIP_DEBUG_PRINT
  43 #define CHIP_DBG(fmt, args...)  printk(fmt, ## args)
  44 #else
  45 #define CHIP_DBG(fmt, args...)  do { } while (0)
  46 #endif
  47
  48 #undef FRAME_FILTER_DEBUG
  49 /* #define FRAME_FILTER_DEBUG */
  50
  51 struct stmmac_extra_stats {
  52         /* Transmit errors */
  53         unsigned long tx_underflow ____cacheline_aligned;
  54         unsigned long tx_carrier;
  55         unsigned long tx_losscarrier;
  56         unsigned long vlan_tag;
  57         unsigned long tx_deferred;
  58         unsigned long tx_vlan;
  59         unsigned long tx_jabber;
  60         unsigned long tx_frame_flushed;
  61         unsigned long tx_payload_error;
  62         unsigned long tx_ip_header_error;
  63         /* Receive errors */
  64         unsigned long rx_desc;
  65         unsigned long sa_filter_fail;
  66         unsigned long overflow_error;
  67         unsigned long ipc_csum_error;
  68         unsigned long rx_collision;
  69         unsigned long rx_crc;
  70         unsigned long dribbling_bit;
  71         unsigned long rx_length;
  72         unsigned long rx_mii;
  73         unsigned long rx_multicast;
  74         unsigned long rx_gmac_overflow;
  75         unsigned long rx_watchdog;
  76         unsigned long da_rx_filter_fail;
  77         unsigned long sa_rx_filter_fail;
  78         unsigned long rx_missed_cntr;
  79         unsigned long rx_overflow_cntr;
  80         unsigned long rx_vlan;
  81         /* Tx/Rx IRQ errors */
  82         unsigned long tx_undeflow_irq;
  83         unsigned long tx_process_stopped_irq;
  84         unsigned long tx_jabber_irq;
  85         unsigned long rx_overflow_irq;
  86         unsigned long rx_buf_unav_irq;
  87         unsigned long rx_process_stopped_irq;
  88         unsigned long rx_watchdog_irq;
  89         unsigned long tx_early_irq;
  90         unsigned long fatal_bus_error_irq;
  91         /* Extra info */
  92         unsigned long threshold;
  93         unsigned long tx_pkt_n;
  94         unsigned long rx_pkt_n;
  95         unsigned long poll_n;
  96         unsigned long sched_timer_n;
  97         unsigned long normal_irq_n;
  98 };
  99
 100 #define HASH_TABLE_SIZE 64
 101 #define PAUSE_TIME 0x200
 102
 103 /* Flow Control defines */
 104 #define FLOW_OFF        0
 105 #define FLOW_RX         1
 106 #define FLOW_TX         2
 107 #define FLOW_AUTO       (FLOW_TX | FLOW_RX)
 108
 109 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
 110
 111 /* DAM HW feature register fields */
 112 #define DMA_HW_FEAT_MIISEL      0x00000001 /* 10/100 Mbps Support */
 113 #define DMA_HW_FEAT_GMIISEL     0x00000002 /* 1000 Mbps Support */
 114 #define DMA_HW_FEAT_HDSEL       0x00000004 /* Half-Duplex Support */
 115 #define DMA_HW_FEAT_EXTHASHEN   0x00000008 /* Expanded DA Hash Filter */
 116 #define DMA_HW_FEAT_HASHSEL     0x00000010 /* HASH Filter */
 117 #define DMA_HW_FEAT_ADDMACADRSEL        0x00000020 /* Multiple MAC Addr Reg */
 118 #define DMA_HW_FEAT_PCSSEL      0x00000040 /* PCS registers */
 119 #define DMA_HW_FEAT_L3L4FLTREN  0x00000080 /* Layer 3 & Layer 4 Feature */
 120 #define DMA_HW_FEAT_SMASEL      0x00000100 /* SMA(MDIO) Interface */
 121 #define DMA_HW_FEAT_RWKSEL      0x00000200 /* PMT Remote Wakeup */
 122 #define DMA_HW_FEAT_MGKSEL      0x00000400 /* PMT Magic Packet */
 123 #define DMA_HW_FEAT_MMCSEL      0x00000800 /* RMON Module */
 124 #define DMA_HW_FEAT_TSVER1SEL   0x00001000 /* Only IEEE 1588-2002 Timestamp */
 125 #define DMA_HW_FEAT_TSVER2SEL   0x00002000 /* IEEE 1588-2008 Adv Timestamp */
 126 #define DMA_HW_FEAT_EEESEL      0x00004000 /* Energy Efficient Ethernet */
 127 #define DMA_HW_FEAT_AVSEL       0x00008000 /* AV Feature */
 128 #define DMA_HW_FEAT_TXCOESEL    0x00010000 /* Checksum Offload in Tx */
 129 #define DMA_HW_FEAT_RXTYP1COE   0x00020000 /* IP csum Offload(Type 1) in Rx */
 130 #define DMA_HW_FEAT_RXTYP2COE   0x00040000 /* IP csum Offload(Type 2) in Rx */
 131 #define DMA_HW_FEAT_RXFIFOSIZE  0x00080000 /* Rx FIFO > 2048 Bytes */
 132 #define DMA_HW_FEAT_RXCHCNT     0x00300000 /* No. of additional Rx Channels */
 133 #define DMA_HW_FEAT_TXCHCNT     0x00c00000 /* No. of additional Tx Channels */
 134 #define DMA_HW_FEAT_ENHDESSEL   0x01000000 /* Alternate (Enhanced Descriptor) */
 135 #define DMA_HW_FEAT_INTTSEN     0x02000000 /* Timestamping with Internal
 136                                               System Time */
 137 #define DMA_HW_FEAT_FLEXIPPSEN  0x04000000 /* Flexible PPS Output */
 138 #define DMA_HW_FEAT_SAVLANINS   0x08000000 /* Source Addr or VLAN Insertion */
 139 #define DMA_HW_FEAT_ACTPHYIF    0x70000000 /* Active/selected PHY interface */
 140
 141 enum rx_frame_status { /* IPC status */
 142         good_frame = 0,
 143         discard_frame = 1,
 144         csum_none = 2,
 145         llc_snap = 4,
 146 };
 147
 148 enum tx_dma_irq_status {
 149         tx_hard_error = 1,
 150         tx_hard_error_bump_tc = 2,
 151         handle_tx_rx = 3,
 152 };
 153
 154 /* DMA HW capabilities */
 155 struct dma_features {
 156         unsigned int mbps_10_100;
 157         unsigned int mbps_1000;
 158         unsigned int half_duplex;
 159         unsigned int hash_filter;
 160         unsigned int multi_addr;
 161         unsigned int pcs;
 162         unsigned int sma_mdio;
 163         unsigned int pmt_remote_wake_up;
 164         unsigned int pmt_magic_frame;
 165         unsigned int rmon;
 166         /* IEEE 1588-2002*/
 167         unsigned int time_stamp;
 168         /* IEEE 1588-2008*/
 169         unsigned int atime_stamp;
 170         /* 802.3az - Energy-Efficient Ethernet (EEE) */
 171         unsigned int eee;
 172         unsigned int av;
 173         /* TX and RX csum */
 174         unsigned int tx_coe;
 175         unsigned int rx_coe_type1;
 176         unsigned int rx_coe_type2;
 177         unsigned int rxfifo_over_2048;
 178         /* TX and RX number of channels */
 179         unsigned int number_rx_channel;
 180         unsigned int number_tx_channel;
 181         /* Alternate (enhanced) DESC mode*/
 182         unsigned int enh_desc;
 183 };
 184
 185 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
 186 #define BUF_SIZE_16KiB 16384
 187 #define BUF_SIZE_8KiB 8192
 188 #define BUF_SIZE_4KiB 4096
 189 #define BUF_SIZE_2KiB 2048
 190
 191 /* Power Down and WOL */
 192 #define PMT_NOT_SUPPORTED 0
 193 #define PMT_SUPPORTED 1
 194
 195 /* Common MAC defines */
 196 #define MAC_CTRL_REG            0x00000000      /* MAC Control */
 197 #define MAC_ENABLE_TX           0x00000008      /* Transmitter Enable */
 198 #define MAC_RNABLE_RX           0x00000004      /* Receiver Enable */
 199
 200 struct stmmac_desc_ops {
 201         /* DMA RX descriptor ring initialization */
 202         void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
 203                               int disable_rx_ic);
 204         /* DMA TX descriptor ring initialization */
 205         void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
 206
 207         /* Invoked by the xmit function to prepare the tx descriptor */
 208         void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
 209                                  int csum_flag);
 210         /* Set/get the owner of the descriptor */
 211         void (*set_tx_owner) (struct dma_desc *p);
 212         int (*get_tx_owner) (struct dma_desc *p);
 213         /* Invoked by the xmit function to close the tx descriptor */
 214         void (*close_tx_desc) (struct dma_desc *p);
 215         /* Clean the tx descriptor as soon as the tx irq is received */
 216         void (*release_tx_desc) (struct dma_desc *p);
 217         /* Clear interrupt on tx frame completion. When this bit is
 218          * set an interrupt happens as soon as the frame is transmitted */
 219         void (*clear_tx_ic) (struct dma_desc *p);
 220         /* Last tx segment reports the transmit status */
 221         int (*get_tx_ls) (struct dma_desc *p);
 222         /* Return the transmit status looking at the TDES1 */
 223         int (*tx_status) (void *data, struct stmmac_extra_stats *x,
 224                           struct dma_desc *p, void __iomem *ioaddr);
 225         /* Get the buffer size from the descriptor */
 226         int (*get_tx_len) (struct dma_desc *p);
 227         /* Handle extra events on specific interrupts hw dependent */
 228         int (*get_rx_owner) (struct dma_desc *p);
 229         void (*set_rx_owner) (struct dma_desc *p);
 230         /* Get the receive frame size */
 231         int (*get_rx_frame_len) (struct dma_desc *p);
 232         /* Return the reception status looking at the RDES1 */
 233         int (*rx_status) (void *data, struct stmmac_extra_stats *x,
 234                           struct dma_desc *p);
 235 };
 236
 237 struct stmmac_dma_ops {
 238         /* DMA core initialization */
 239         int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
 240         /* Dump DMA registers */
 241         void (*dump_regs) (void __iomem *ioaddr);
 242         /* Set tx/rx threshold in the csr6 register
 243          * An invalid value enables the store-and-forward mode */
 244         void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
 245         /* To track extra statistic (if supported) */
 246         void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
 247                                    void __iomem *ioaddr);
 248         void (*enable_dma_transmission) (void __iomem *ioaddr);
 249         void (*enable_dma_irq) (void __iomem *ioaddr);
 250         void (*disable_dma_irq) (void __iomem *ioaddr);
 251         void (*start_tx) (void __iomem *ioaddr);
 252         void (*stop_tx) (void __iomem *ioaddr);
 253         void (*start_rx) (void __iomem *ioaddr);
 254         void (*stop_rx) (void __iomem *ioaddr);
 255         int (*dma_interrupt) (void __iomem *ioaddr,
 256                               struct stmmac_extra_stats *x);
 257         /* If supported then get the optional core features */
 258         unsigned int (*get_hw_feature) (void __iomem *ioaddr);
 259 };
 260
 261 struct stmmac_ops {
 262         /* MAC core initialization */
 263         void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
 264         /* Support checksum offload engine */
 265         int  (*rx_coe) (void __iomem *ioaddr);
 266         /* Dump MAC registers */
 267         void (*dump_regs) (void __iomem *ioaddr);
 268         /* Handle extra events on specific interrupts hw dependent */
 269         void (*host_irq_status) (void __iomem *ioaddr);
 270         /* Multicast filter setting */
 271         void (*set_filter) (struct net_device *dev);
 272         /* Flow control setting */
 273         void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
 274                            unsigned int fc, unsigned int pause_time);
 275         /* Set power management mode (e.g. magic frame) */
 276         void (*pmt) (void __iomem *ioaddr, unsigned long mode);
 277         /* Set/Get Unicast MAC addresses */
 278         void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
 279                                unsigned int reg_n);
 280         void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
 281                                unsigned int reg_n);
 282 };
 283
 284 struct mac_link {
 285         int port;
 286         int duplex;
 287         int speed;
 288 };
 289
 290 struct mii_regs {
 291         unsigned int addr;      /* MII Address */
 292         unsigned int data;      /* MII Data */
 293 };
 294
 295 struct stmmac_ring_mode_ops {
 296         unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
 297         unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
 298         void (*refill_desc3) (int bfsize, struct dma_desc *p);
 299         void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p);
 300         void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr,
 301                                 unsigned int size);
 302         void (*clean_desc3) (struct dma_desc *p);
 303         int (*set_16kib_bfsize) (int mtu);
 304 };
 305
 306 struct mac_device_info {
 307         const struct stmmac_ops         *mac;
 308         const struct stmmac_desc_ops    *desc;
 309         const struct stmmac_dma_ops     *dma;
 310         const struct stmmac_ring_mode_ops       *ring;
 311         struct mii_regs mii;    /* MII register Addresses */
 312         struct mac_link link;
 313         unsigned int synopsys_uid;
 314 };
 315
 316 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
 317 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
 318
 319 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 320                                 unsigned int high, unsigned int low);
 321 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 322                                 unsigned int high, unsigned int low);
 323
 324 extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
 325
 326 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
 327 extern const struct stmmac_ring_mode_ops ring_mode_ops;