drivers/net/irda/w83977af_ir.h

   1 /*********************************************************************
   2  *
   3  * Filename:      w83977af_ir.h
   4  * Version:
   5  * Description:
   6  * Status:        Experimental.
   7  * Author:        Paul VanderSpek
   8  * Created at:    Thu Nov 19 13:55:34 1998
   9  * Modified at:   Tue Jan 11 13:08:19 2000
  10  * Modified by:   Dag Brattli <dagb@cs.uit.no>
  11  *
  12  *     Copyright (c) 1998-2000 Dag Brattli, All Rights Reserved.
  13  *
  14  *     This program is free software; you can redistribute it and/or
  15  *     modify it under the terms of the GNU General Public License as
  16  *     published by the Free Software Foundation; either version 2 of
  17  *     the License, or (at your option) any later version.
  18  *
  19  *     Neither Dag Brattli nor University of Tromsø admit liability nor
  20  *     provide warranty for any of this software. This material is
  21  *     provided "AS-IS" and at no charge.
  22  *
  23  ********************************************************************/
  24
  25 #ifndef W83977AF_IR_H
  26 #define W83977AF_IR_H
  27
  28 #include <asm/io.h>
  29 #include <linux/types.h>
  30
  31 /* Flags for configuration register CRF0 */
  32 #define ENBNKSEL        0x01
  33 #define APEDCRC         0x02
  34 #define TXW4C           0x04
  35 #define RXW4C           0x08
  36
  37 /* Bank 0 */
  38 #define RBR             0x00 /* Receiver buffer register */
  39 #define TBR             0x00 /* Transmitter buffer register */
  40
  41 #define ICR             0x01 /* Interrupt configuration register */
  42 #define ICR_ERBRI       0x01 /* Receiver buffer register interrupt */
  43 #define ICR_ETBREI      0x02 /* Transeiver empty interrupt */
  44 #define ICR_EUSRI       0x04//* IR status interrupt */
  45 #define ICR_EHSRI       0x04
  46 #define ICR_ETXURI      0x04 /* Tx underrun */
  47 #define ICR_EDMAI       0x10 /* DMA interrupt */
  48 #define ICR_ETXTHI      0x20 /* Transmitter threshold interrupt */
  49 #define ICR_EFSFI       0x40 /* Frame status FIFO interrupt */
  50 #define ICR_ETMRI       0x80 /* Timer interrupt */
  51
  52 #define UFR             0x02 /* FIFO control register */
  53 #define UFR_EN_FIFO     0x01 /* Enable FIFO's */
  54 #define UFR_RXF_RST     0x02 /* Reset Rx FIFO */
  55 #define UFR_TXF_RST     0x04 /* Reset Tx FIFO */
  56 #define UFR_RXTL        0x80 /* Rx FIFO threshold (set to 16) */
  57 #define UFR_TXTL        0x20 /* Tx FIFO threshold (set to 17) */
  58
  59 #define ISR             0x02 /* Interrupt status register */
  60 #define ISR_RXTH_I      0x01 /* Receive threshold interrupt */
  61 #define ISR_TXEMP_I     0x02 /* Transmitter empty interrupt */
  62 #define ISR_FEND_I      0x04
  63 #define ISR_DMA_I       0x10
  64 #define ISR_TXTH_I      0x20 /* Transmitter threshold interrupt */
  65 #define ISR_FSF_I       0x40
  66 #define ISR_TMR_I       0x80 /* Timer interrupt */
  67
  68 #define UCR             0x03 /* Uart control register */
  69 #define UCR_DLS8        0x03 /* 8N1 */
  70
  71 #define SSR             0x03 /* Sets select register */
  72 #define SET0            UCR_DLS8        /* Make sure we keep 8N1 */
  73 #define SET1            (0x80|UCR_DLS8) /* Make sure we keep 8N1 */
  74 #define SET2            0xE0
  75 #define SET3            0xE4
  76 #define SET4            0xE8
  77 #define SET5            0xEC
  78 #define SET6            0xF0
  79 #define SET7            0xF4
  80
  81 #define HCR             0x04
  82 #define HCR_MODE_MASK   ~(0xD0)
  83 #define HCR_SIR         0x60
  84 #define HCR_MIR_576     0x20
  85 #define HCR_MIR_1152    0x80
  86 #define HCR_FIR         0xA0
  87 #define HCR_EN_DMA      0x04
  88 #define HCR_EN_IRQ      0x08
  89 #define HCR_TX_WT       0x08
  90
  91 #define USR             0x05 /* IR status register */
  92 #define USR_RDR         0x01 /* Receive data ready */
  93 #define USR_TSRE        0x40 /* Transmitter empty? */
  94
  95 #define AUDR            0x07
  96 #define AUDR_SFEND      0x08 /* Set a frame end */
  97 #define AUDR_RXBSY      0x20 /* Rx busy */
  98 #define AUDR_UNDR       0x40 /* Transeiver underrun */
  99
 100 /* Set 2 */
 101 #define ABLL            0x00 /* Advanced baud rate divisor latch (low byte) */
 102 #define ABHL            0x01 /* Advanced baud rate divisor latch (high byte) */
 103
 104 #define ADCR1           0x02
 105 #define ADCR1_ADV_SL    0x01
 106 #define ADCR1_D_CHSW    0x08    /* the specs are wrong. its bit 3, not 4 */
 107 #define ADCR1_DMA_F     0x02
 108
 109 #define ADCR2           0x04
 110 #define ADCR2_TXFS32    0x01
 111 #define ADCR2_RXFS32    0x04
 112
 113 #define RXFDTH          0x07
 114
 115 /* Set 3 */
 116 #define AUID            0x00
 117
 118 /* Set 4 */
 119 #define TMRL            0x00 /* Timer value register (low byte) */
 120 #define TMRH            0x01 /* Timer value register (high byte) */
 121
 122 #define IR_MSL          0x02 /* Infrared mode select */
 123 #define IR_MSL_EN_TMR   0x01 /* Enable timer */
 124
 125 #define TFRLL           0x04 /* Transmitter frame length (low byte) */
 126 #define TFRLH           0x05 /* Transmitter frame length (high byte) */
 127 #define RFRLL           0x06 /* Receiver frame length (low byte) */
 128 #define RFRLH           0x07 /* Receiver frame length (high byte) */
 129
 130 /* Set 5 */
 131
 132 #define FS_FO           0x05 /* Frame status FIFO */
 133 #define FS_FO_FSFDR     0x80 /* Frame status FIFO data ready */
 134 #define FS_FO_LST_FR    0x40 /* Frame lost */
 135 #define FS_FO_MX_LEX    0x10 /* Max frame len exceeded */
 136 #define FS_FO_PHY_ERR   0x08 /* Physical layer error */
 137 #define FS_FO_CRC_ERR   0x04
 138 #define FS_FO_RX_OV     0x02 /* Receive overrun */
 139 #define FS_FO_FSF_OV    0x01 /* Frame status FIFO overrun */
 140 #define FS_FO_ERR_MSK   0x5f /* Error mask */
 141
 142 #define RFLFL           0x06
 143 #define RFLFH           0x07
 144
 145 /* Set 6 */
 146 #define IR_CFG2         0x00
 147 #define IR_CFG2_DIS_CRC 0x02
 148
 149 /* Set 7 */
 150 #define IRM_CR          0x07 /* Infrared module control register */
 151 #define IRM_CR_IRX_MSL  0x40
 152 #define IRM_CR_AF_MNT   0x80 /* Automatic format */
 153
 154 /* For storing entries in the status FIFO */
 155 struct st_fifo_entry {
 156         int status;
 157         int len;
 158 };
 159
 160 struct st_fifo {
 161         struct st_fifo_entry entries[10];
 162         int head;
 163         int tail;
 164         int len;
 165 };
 166
 167 /* Private data for each instance */
 168 struct w83977af_ir {
 169         struct st_fifo st_fifo;
 170
 171         int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
 172         int tx_len;          /* Number of frames in tx_buff */
 173
 174         struct net_device *netdev; /* Yes! we are some kind of netdevice */
 175
 176         struct irlap_cb    *irlap; /* The link layer we are binded to */
 177         struct qos_info     qos;   /* QoS capabilities for this device */
 178
 179         chipio_t io;               /* IrDA controller information */
 180         iobuff_t tx_buff;          /* Transmit buffer */
 181         iobuff_t rx_buff;          /* Receive buffer */
 182         dma_addr_t tx_buff_dma;
 183         dma_addr_t rx_buff_dma;
 184
 185         /* Note : currently locking is *very* incomplete, but this
 186          * will get you started. Check in nsc-ircc.c for a proper
 187          * locking strategy. - Jean II */
 188         spinlock_t lock;           /* For serializing operations */
 189
 190         __u32 new_speed;
 191 };
 192
 193 static inline void switch_bank( int iobase, int set)
 194 {
 195         outb(set, iobase+SSR);
 196 }
 197
 198 #endif