spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / wireless / b43 / radio_2059.h
blobe4d69e55e9fe84ac748f47e33b9d9a038886f74a
1 #ifndef B43_RADIO_2059_H_
2 #define B43_RADIO_2059_H_
4 #include <linux/types.h>
6 #include "phy_ht.h"
8 #define R2059_SYN 0x000
9 #define R2059_TXRX0 0x400
10 #define R2059_RXRX1 0x800
11 #define R2059_ALL 0xC00
13 /* Values for various registers uploaded on channel switching */
14 struct b43_phy_ht_channeltab_e_radio2059 {
15 /* The channel frequency in MHz */
16 u16 freq;
17 /* Values for radio registers */
18 u8 radio_syn16;
19 u8 radio_syn17;
20 u8 radio_syn22;
21 u8 radio_syn25;
22 u8 radio_syn27;
23 u8 radio_syn28;
24 u8 radio_syn29;
25 u8 radio_syn2c;
26 u8 radio_syn2d;
27 u8 radio_syn37;
28 u8 radio_syn41;
29 u8 radio_syn43;
30 u8 radio_syn47;
31 u8 radio_syn4a;
32 u8 radio_syn58;
33 u8 radio_syn5a;
34 u8 radio_syn6a;
35 u8 radio_syn6d;
36 u8 radio_syn6e;
37 u8 radio_syn92;
38 u8 radio_syn98;
39 u8 radio_rxtx4a;
40 u8 radio_rxtx58;
41 u8 radio_rxtx5a;
42 u8 radio_rxtx6a;
43 u8 radio_rxtx6d;
44 u8 radio_rxtx6e;
45 u8 radio_rxtx92;
46 u8 radio_rxtx98;
47 /* Values for PHY registers */
48 struct b43_phy_ht_channeltab_e_phy phy_regs;
51 const struct b43_phy_ht_channeltab_e_radio2059
52 *b43_phy_ht_get_channeltab_e_r2059(struct b43_wldev *dev, u16 freq);
54 #endif /* B43_RADIO_2059_H_ */