spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / wireless / b43 / tables_nphy.h
blob97038c4819304938a6d41fed53ae3b0d65ce5a6c
1 #ifndef B43_TABLES_NPHY_H_
2 #define B43_TABLES_NPHY_H_
4 #include <linux/types.h>
6 struct b43_phy_n_sfo_cfg {
7 u16 phy_bw1a;
8 u16 phy_bw2;
9 u16 phy_bw3;
10 u16 phy_bw4;
11 u16 phy_bw5;
12 u16 phy_bw6;
15 struct b43_wldev;
17 struct nphy_txiqcal_ladder {
18 u8 percent;
19 u8 g_env;
22 struct nphy_rf_control_override_rev2 {
23 u8 addr0;
24 u8 addr1;
25 u16 bmask;
26 u8 shift;
29 struct nphy_rf_control_override_rev3 {
30 u16 val_mask;
31 u8 val_shift;
32 u8 en_addr0;
33 u8 val_addr0;
34 u8 en_addr1;
35 u8 val_addr1;
38 struct nphy_gain_ctl_workaround_entry {
39 s8 lna1_gain[4];
40 s8 lna2_gain[4];
41 u8 gain_db[10];
42 u8 gain_bits[10];
44 u16 init_gain;
45 u16 rfseq_init[4];
47 u16 cliphi_gain;
48 u16 clipmd_gain;
49 u16 cliplo_gain;
51 u16 crsmin;
52 u16 crsminl;
53 u16 crsminu;
55 u16 nbclip;
56 u16 wlclip;
59 /* Get entry with workaround values for gain ctl. Does not return NULL. */
60 struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
61 struct b43_wldev *dev, bool ghz5, bool ext_lna);
64 /* The N-PHY tables. */
65 #define B43_NTAB_TYPEMASK 0xF0000000
66 #define B43_NTAB_8BIT 0x10000000
67 #define B43_NTAB_16BIT 0x20000000
68 #define B43_NTAB_32BIT 0x30000000
69 #define B43_NTAB8(table, offset) (((table) << 10) | (offset) | B43_NTAB_8BIT)
70 #define B43_NTAB16(table, offset) (((table) << 10) | (offset) | B43_NTAB_16BIT)
71 #define B43_NTAB32(table, offset) (((table) << 10) | (offset) | B43_NTAB_32BIT)
73 /* Static N-PHY tables */
74 #define B43_NTAB_FRAMESTRUCT B43_NTAB32(0x0A, 0x000) /* Frame Struct Table */
75 #define B43_NTAB_FRAMESTRUCT_SIZE 832
76 #define B43_NTAB_FRAMELT B43_NTAB8 (0x18, 0x000) /* Frame Lookup Table */
77 #define B43_NTAB_FRAMELT_SIZE 32
78 #define B43_NTAB_TMAP B43_NTAB32(0x0C, 0x000) /* T Map Table */
79 #define B43_NTAB_TMAP_SIZE 448
80 #define B43_NTAB_TDTRN B43_NTAB32(0x0E, 0x000) /* TDTRN Table */
81 #define B43_NTAB_TDTRN_SIZE 704
82 #define B43_NTAB_INTLEVEL B43_NTAB32(0x0D, 0x000) /* Int Level Table */
83 #define B43_NTAB_INTLEVEL_SIZE 7
84 #define B43_NTAB_PILOT B43_NTAB16(0x0B, 0x000) /* Pilot Table */
85 #define B43_NTAB_PILOT_SIZE 88
86 #define B43_NTAB_PILOTLT B43_NTAB32(0x14, 0x000) /* Pilot Lookup Table */
87 #define B43_NTAB_PILOTLT_SIZE 6
88 #define B43_NTAB_TDI20A0 B43_NTAB32(0x13, 0x080) /* TDI Table 20 Antenna 0 */
89 #define B43_NTAB_TDI20A0_SIZE 55
90 #define B43_NTAB_TDI20A1 B43_NTAB32(0x13, 0x100) /* TDI Table 20 Antenna 1 */
91 #define B43_NTAB_TDI20A1_SIZE 55
92 #define B43_NTAB_TDI40A0 B43_NTAB32(0x13, 0x280) /* TDI Table 40 Antenna 0 */
93 #define B43_NTAB_TDI40A0_SIZE 110
94 #define B43_NTAB_TDI40A1 B43_NTAB32(0x13, 0x300) /* TDI Table 40 Antenna 1 */
95 #define B43_NTAB_TDI40A1_SIZE 110
96 #define B43_NTAB_BDI B43_NTAB16(0x15, 0x000) /* BDI Table */
97 #define B43_NTAB_BDI_SIZE 6
98 #define B43_NTAB_CHANEST B43_NTAB32(0x16, 0x000) /* Channel Estimate Table */
99 #define B43_NTAB_CHANEST_SIZE 96
100 #define B43_NTAB_MCS B43_NTAB8 (0x12, 0x000) /* MCS Table */
101 #define B43_NTAB_MCS_SIZE 128
103 /* Volatile N-PHY tables */
104 #define B43_NTAB_NOISEVAR10 B43_NTAB32(0x10, 0x000) /* Noise Var Table 10 */
105 #define B43_NTAB_NOISEVAR10_SIZE 256
106 #define B43_NTAB_NOISEVAR11 B43_NTAB32(0x10, 0x080) /* Noise Var Table 11 */
107 #define B43_NTAB_NOISEVAR11_SIZE 256
108 #define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
109 #define B43_NTAB_C0_ESTPLT_SIZE 64
110 #define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
111 #define B43_NTAB_C1_ESTPLT_SIZE 64
112 #define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
113 #define B43_NTAB_C0_ADJPLT_SIZE 128
114 #define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
115 #define B43_NTAB_C1_ADJPLT_SIZE 128
116 #define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
117 #define B43_NTAB_C0_GAINCTL_SIZE 128
118 #define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
119 #define B43_NTAB_C1_GAINCTL_SIZE 128
120 #define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
121 #define B43_NTAB_C0_IQLT_SIZE 128
122 #define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
123 #define B43_NTAB_C1_IQLT_SIZE 128
124 #define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
125 #define B43_NTAB_C0_LOFEEDTH_SIZE 128
126 #define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
127 #define B43_NTAB_C1_LOFEEDTH_SIZE 128
129 /* Volatile N-PHY tables, PHY revision >= 3 */
130 #define B43_NTAB_ANT_SW_CTL_R3 B43_NTAB16( 9, 0) /* antenna software control */
132 /* Static N-PHY tables, PHY revision >= 3 */
133 #define B43_NTAB_FRAMESTRUCT_R3 B43_NTAB32(10, 0) /* frame struct */
134 #define B43_NTAB_PILOT_R3 B43_NTAB16(11, 0) /* pilot */
135 #define B43_NTAB_TMAP_R3 B43_NTAB32(12, 0) /* TM AP */
136 #define B43_NTAB_INTLEVEL_R3 B43_NTAB32(13, 0) /* INT LV */
137 #define B43_NTAB_TDTRN_R3 B43_NTAB32(14, 0) /* TD TRN */
138 #define B43_NTAB_NOISEVAR0_R3 B43_NTAB32(16, 0) /* noise variance 0 */
139 #define B43_NTAB_NOISEVAR1_R3 B43_NTAB32(16, 128) /* noise variance 1 */
140 #define B43_NTAB_MCS_R3 B43_NTAB16(18, 0) /* MCS */
141 #define B43_NTAB_TDI20A0_R3 B43_NTAB32(19, 128) /* TDI 20/0 */
142 #define B43_NTAB_TDI20A1_R3 B43_NTAB32(19, 256) /* TDI 20/1 */
143 #define B43_NTAB_TDI40A0_R3 B43_NTAB32(19, 640) /* TDI 40/0 */
144 #define B43_NTAB_TDI40A1_R3 B43_NTAB32(19, 768) /* TDI 40/1 */
145 #define B43_NTAB_PILOTLT_R3 B43_NTAB32(20, 0) /* PLT lookup */
146 #define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */
147 #define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */
148 #define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */
149 #define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
150 #define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */
151 #define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
152 #define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */
153 #define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
154 #define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */
155 #define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
156 #define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */
157 #define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */
159 #define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18
160 #define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18
161 #define B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_40_SIZE 18
162 #define B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_20_SIZE 18
163 #define B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3 11
164 #define B43_NTAB_TX_IQLO_CAL_STARTCOEFS 9
165 #define B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3 12
166 #define B43_NTAB_TX_IQLO_CAL_CMDS_RECAL 10
167 #define B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL 10
168 #define B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3 12
170 u32 b43_ntab_read(struct b43_wldev *dev, u32 offset);
171 void b43_ntab_read_bulk(struct b43_wldev *dev, u32 offset,
172 unsigned int nr_elements, void *_data);
173 void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value);
174 void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
175 unsigned int nr_elements, const void *_data);
177 void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev);
178 void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
180 extern const u32 b43_ntab_tx_gain_rev0_1_2[];
181 extern const u32 b43_ntab_tx_gain_rev3plus_2ghz[];
182 extern const u32 b43_ntab_tx_gain_rev3_5ghz[];
183 extern const u32 b43_ntab_tx_gain_rev4_5ghz[];
184 extern const u32 b43_ntab_tx_gain_rev5plus_5ghz[];
186 extern const u32 txpwrctrl_tx_gain_ipa[];
187 extern const u32 txpwrctrl_tx_gain_ipa_rev5[];
188 extern const u32 txpwrctrl_tx_gain_ipa_rev6[];
189 extern const u32 txpwrctrl_tx_gain_ipa_5g[];
190 extern const u16 tbl_iqcal_gainparams[2][9][8];
191 extern const struct nphy_txiqcal_ladder ladder_lo[];
192 extern const struct nphy_txiqcal_ladder ladder_iq[];
193 extern const u16 loscale[];
195 extern const u16 tbl_tx_iqlo_cal_loft_ladder_40[];
196 extern const u16 tbl_tx_iqlo_cal_loft_ladder_20[];
197 extern const u16 tbl_tx_iqlo_cal_iqimb_ladder_40[];
198 extern const u16 tbl_tx_iqlo_cal_iqimb_ladder_20[];
199 extern const u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[];
200 extern const u16 tbl_tx_iqlo_cal_startcoefs[];
201 extern const u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[];
202 extern const u16 tbl_tx_iqlo_cal_cmds_recal[];
203 extern const u16 tbl_tx_iqlo_cal_cmds_fullcal[];
204 extern const u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[];
205 extern const s16 tbl_tx_filter_coef_rev4[7][15];
207 extern const struct nphy_rf_control_override_rev2
208 tbl_rf_control_override_rev2[];
209 extern const struct nphy_rf_control_override_rev3
210 tbl_rf_control_override_rev3[];
212 #endif /* B43_TABLES_NPHY_H_ */