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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / wireless / b43legacy / main.c
blob75e70bce40f6b8eb896ebb348e24c0f32a4b1930
1 /*
2 *
3 * Broadcom B43legacy wireless driver
4 *
5 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
7 * Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
8 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11 *
12 * Some parts of the code in this file are derived from the ipw2200
13 * driver Copyright(c) 2003 - 2004 Intel Corporation.
14
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING. If not, write to
27 * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28 * Boston, MA 02110-1301, USA.
29 *
30 */
31
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/module.h>
35 #include <linux/if_arp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/workqueue.h>
39 #include <linux/sched.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/slab.h>
43 #include <net/dst.h>
44 #include <asm/unaligned.h>
45
46 #include "b43legacy.h"
47 #include "main.h"
48 #include "debugfs.h"
49 #include "phy.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "radio.h"
55
56
57 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE("b43legacy/ucode2.fw");
64 MODULE_FIRMWARE("b43legacy/ucode4.fw");
65
66 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
67 static int modparam_pio;
68 module_param_named(pio, modparam_pio, int, 0444);
69 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
70 #elif defined(CONFIG_B43LEGACY_DMA)
71 # define modparam_pio 0
72 #elif defined(CONFIG_B43LEGACY_PIO)
73 # define modparam_pio 1
74 #endif
75
76 static int modparam_bad_frames_preempt;
77 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
78 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
79 " Preemption");
80
81 static char modparam_fwpostfix[16];
82 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
83 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
84
85 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
86 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
87 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
88 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
89 SSB_DEVTABLE_END
90 };
91 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
92
93
94 /* Channel and ratetables are shared for all devices.
95 * They can't be const, because ieee80211 puts some precalculated
96 * data in there. This data is the same for all devices, so we don't
97 * get concurrency issues */
98 #define RATETAB_ENT(_rateid, _flags) \
99 { \
100 .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
101 .hw_value = (_rateid), \
102 .flags = (_flags), \
103 }
104 /*
105 * NOTE: When changing this, sync with xmit.c's
106 * b43legacy_plcp_get_bitrate_idx_* functions!
107 */
108 static struct ieee80211_rate __b43legacy_ratetable[] = {
109 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
110 RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
111 RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
112 RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
113 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
114 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
115 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
116 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
117 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
118 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
119 RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
120 RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
121 };
122 #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
123 #define b43legacy_b_ratetable_size 4
124 #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
125 #define b43legacy_g_ratetable_size 12
126
127 #define CHANTAB_ENT(_chanid, _freq) \
128 { \
129 .center_freq = (_freq), \
130 .hw_value = (_chanid), \
131 }
132 static struct ieee80211_channel b43legacy_bg_chantable[] = {
133 CHANTAB_ENT(1, 2412),
134 CHANTAB_ENT(2, 2417),
135 CHANTAB_ENT(3, 2422),
136 CHANTAB_ENT(4, 2427),
137 CHANTAB_ENT(5, 2432),
138 CHANTAB_ENT(6, 2437),
139 CHANTAB_ENT(7, 2442),
140 CHANTAB_ENT(8, 2447),
141 CHANTAB_ENT(9, 2452),
142 CHANTAB_ENT(10, 2457),
143 CHANTAB_ENT(11, 2462),
144 CHANTAB_ENT(12, 2467),
145 CHANTAB_ENT(13, 2472),
146 CHANTAB_ENT(14, 2484),
147 };
148
149 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
150 .channels = b43legacy_bg_chantable,
151 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
152 .bitrates = b43legacy_b_ratetable,
153 .n_bitrates = b43legacy_b_ratetable_size,
154 };
155
156 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
157 .channels = b43legacy_bg_chantable,
158 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
159 .bitrates = b43legacy_g_ratetable,
160 .n_bitrates = b43legacy_g_ratetable_size,
161 };
162
163 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
164 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
165 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
166 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
167
168
169 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
170 {
171 if (!wl || !wl->current_dev)
172 return 1;
173 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
174 return 1;
175 /* We are up and running.
176 * Ratelimit the messages to avoid DoS over the net. */
177 return net_ratelimit();
178 }
179
180 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
181 {
182 struct va_format vaf;
183 va_list args;
184
185 if (!b43legacy_ratelimit(wl))
186 return;
187
188 va_start(args, fmt);
189
190 vaf.fmt = fmt;
191 vaf.va = &args;
192
193 printk(KERN_INFO "b43legacy-%s: %pV",
194 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
195
196 va_end(args);
197 }
198
199 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
200 {
201 struct va_format vaf;
202 va_list args;
203
204 if (!b43legacy_ratelimit(wl))
205 return;
206
207 va_start(args, fmt);
208
209 vaf.fmt = fmt;
210 vaf.va = &args;
211
212 printk(KERN_ERR "b43legacy-%s ERROR: %pV",
213 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
214
215 va_end(args);
216 }
217
218 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
219 {
220 struct va_format vaf;
221 va_list args;
222
223 if (!b43legacy_ratelimit(wl))
224 return;
225
226 va_start(args, fmt);
227
228 vaf.fmt = fmt;
229 vaf.va = &args;
230
231 printk(KERN_WARNING "b43legacy-%s warning: %pV",
232 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
233
234 va_end(args);
235 }
236
237 #if B43legacy_DEBUG
238 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
239 {
240 struct va_format vaf;
241 va_list args;
242
243 va_start(args, fmt);
244
245 vaf.fmt = fmt;
246 vaf.va = &args;
247
248 printk(KERN_DEBUG "b43legacy-%s debug: %pV",
249 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
250
251 va_end(args);
252 }
253 #endif /* DEBUG */
254
255 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
256 u32 val)
257 {
258 u32 status;
259
260 B43legacy_WARN_ON(offset % 4 != 0);
261
262 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
263 if (status & B43legacy_MACCTL_BE)
264 val = swab32(val);
265
266 b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
267 mmiowb();
268 b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
269 }
270
271 static inline
272 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
273 u16 routing, u16 offset)
274 {
275 u32 control;
276
277 /* "offset" is the WORD offset. */
278
279 control = routing;
280 control <<= 16;
281 control |= offset;
282 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
283 }
284
285 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
286 u16 routing, u16 offset)
287 {
288 u32 ret;
289
290 if (routing == B43legacy_SHM_SHARED) {
291 B43legacy_WARN_ON((offset & 0x0001) != 0);
292 if (offset & 0x0003) {
293 /* Unaligned access */
294 b43legacy_shm_control_word(dev, routing, offset >> 2);
295 ret = b43legacy_read16(dev,
296 B43legacy_MMIO_SHM_DATA_UNALIGNED);
297 ret <<= 16;
298 b43legacy_shm_control_word(dev, routing,
299 (offset >> 2) + 1);
300 ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
301
302 return ret;
303 }
304 offset >>= 2;
305 }
306 b43legacy_shm_control_word(dev, routing, offset);
307 ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
308
309 return ret;
310 }
311
312 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
313 u16 routing, u16 offset)
314 {
315 u16 ret;
316
317 if (routing == B43legacy_SHM_SHARED) {
318 B43legacy_WARN_ON((offset & 0x0001) != 0);
319 if (offset & 0x0003) {
320 /* Unaligned access */
321 b43legacy_shm_control_word(dev, routing, offset >> 2);
322 ret = b43legacy_read16(dev,
323 B43legacy_MMIO_SHM_DATA_UNALIGNED);
324
325 return ret;
326 }
327 offset >>= 2;
328 }
329 b43legacy_shm_control_word(dev, routing, offset);
330 ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
331
332 return ret;
333 }
334
335 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
336 u16 routing, u16 offset,
337 u32 value)
338 {
339 if (routing == B43legacy_SHM_SHARED) {
340 B43legacy_WARN_ON((offset & 0x0001) != 0);
341 if (offset & 0x0003) {
342 /* Unaligned access */
343 b43legacy_shm_control_word(dev, routing, offset >> 2);
344 mmiowb();
345 b43legacy_write16(dev,
346 B43legacy_MMIO_SHM_DATA_UNALIGNED,
347 (value >> 16) & 0xffff);
348 mmiowb();
349 b43legacy_shm_control_word(dev, routing,
350 (offset >> 2) + 1);
351 mmiowb();
352 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
353 value & 0xffff);
354 return;
355 }
356 offset >>= 2;
357 }
358 b43legacy_shm_control_word(dev, routing, offset);
359 mmiowb();
360 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
361 }
362
363 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
364 u16 value)
365 {
366 if (routing == B43legacy_SHM_SHARED) {
367 B43legacy_WARN_ON((offset & 0x0001) != 0);
368 if (offset & 0x0003) {
369 /* Unaligned access */
370 b43legacy_shm_control_word(dev, routing, offset >> 2);
371 mmiowb();
372 b43legacy_write16(dev,
373 B43legacy_MMIO_SHM_DATA_UNALIGNED,
374 value);
375 return;
376 }
377 offset >>= 2;
378 }
379 b43legacy_shm_control_word(dev, routing, offset);
380 mmiowb();
381 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
382 }
383
384 /* Read HostFlags */
385 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
386 {
387 u32 ret;
388
389 ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
390 B43legacy_SHM_SH_HOSTFHI);
391 ret <<= 16;
392 ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
393 B43legacy_SHM_SH_HOSTFLO);
394
395 return ret;
396 }
397
398 /* Write HostFlags */
399 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
400 {
401 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
402 B43legacy_SHM_SH_HOSTFLO,
403 (value & 0x0000FFFF));
404 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
405 B43legacy_SHM_SH_HOSTFHI,
406 ((value & 0xFFFF0000) >> 16));
407 }
408
409 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
410 {
411 /* We need to be careful. As we read the TSF from multiple
412 * registers, we should take care of register overflows.
413 * In theory, the whole tsf read process should be atomic.
414 * We try to be atomic here, by restaring the read process,
415 * if any of the high registers changed (overflew).
416 */
417 if (dev->dev->id.revision >= 3) {
418 u32 low;
419 u32 high;
420 u32 high2;
421
422 do {
423 high = b43legacy_read32(dev,
424 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
425 low = b43legacy_read32(dev,
426 B43legacy_MMIO_REV3PLUS_TSF_LOW);
427 high2 = b43legacy_read32(dev,
428 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
429 } while (unlikely(high != high2));
430
431 *tsf = high;
432 *tsf <<= 32;
433 *tsf |= low;
434 } else {
435 u64 tmp;
436 u16 v0;
437 u16 v1;
438 u16 v2;
439 u16 v3;
440 u16 test1;
441 u16 test2;
442 u16 test3;
443
444 do {
445 v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
446 v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
447 v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
448 v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
449
450 test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
451 test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
452 test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
453 } while (v3 != test3 || v2 != test2 || v1 != test1);
454
455 *tsf = v3;
456 *tsf <<= 48;
457 tmp = v2;
458 tmp <<= 32;
459 *tsf |= tmp;
460 tmp = v1;
461 tmp <<= 16;
462 *tsf |= tmp;
463 *tsf |= v0;
464 }
465 }
466
467 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
468 {
469 u32 status;
470
471 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
472 status |= B43legacy_MACCTL_TBTTHOLD;
473 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
474 mmiowb();
475 }
476
477 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
478 {
479 u32 status;
480
481 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
482 status &= ~B43legacy_MACCTL_TBTTHOLD;
483 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
484 }
485
486 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
487 {
488 /* Be careful with the in-progress timer.
489 * First zero out the low register, so we have a full
490 * register-overflow duration to complete the operation.
491 */
492 if (dev->dev->id.revision >= 3) {
493 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
494 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
495
496 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
497 mmiowb();
498 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
499 hi);
500 mmiowb();
501 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
502 lo);
503 } else {
504 u16 v0 = (tsf & 0x000000000000FFFFULL);
505 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
506 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
507 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
508
509 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
510 mmiowb();
511 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
512 mmiowb();
513 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
514 mmiowb();
515 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
516 mmiowb();
517 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
518 }
519 }
520
521 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
522 {
523 b43legacy_time_lock(dev);
524 b43legacy_tsf_write_locked(dev, tsf);
525 b43legacy_time_unlock(dev);
526 }
527
528 static
529 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
530 u16 offset, const u8 *mac)
531 {
532 static const u8 zero_addr[ETH_ALEN] = { 0 };
533 u16 data;
534
535 if (!mac)
536 mac = zero_addr;
537
538 offset |= 0x0020;
539 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
540
541 data = mac[0];
542 data |= mac[1] << 8;
543 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
544 data = mac[2];
545 data |= mac[3] << 8;
546 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
547 data = mac[4];
548 data |= mac[5] << 8;
549 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
550 }
551
552 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
553 {
554 static const u8 zero_addr[ETH_ALEN] = { 0 };
555 const u8 *mac = dev->wl->mac_addr;
556 const u8 *bssid = dev->wl->bssid;
557 u8 mac_bssid[ETH_ALEN * 2];
558 int i;
559 u32 tmp;
560
561 if (!bssid)
562 bssid = zero_addr;
563 if (!mac)
564 mac = zero_addr;
565
566 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
567
568 memcpy(mac_bssid, mac, ETH_ALEN);
569 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
570
571 /* Write our MAC address and BSSID to template ram */
572 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
573 tmp = (u32)(mac_bssid[i + 0]);
574 tmp |= (u32)(mac_bssid[i + 1]) << 8;
575 tmp |= (u32)(mac_bssid[i + 2]) << 16;
576 tmp |= (u32)(mac_bssid[i + 3]) << 24;
577 b43legacy_ram_write(dev, 0x20 + i, tmp);
578 b43legacy_ram_write(dev, 0x78 + i, tmp);
579 b43legacy_ram_write(dev, 0x478 + i, tmp);
580 }
581 }
582
583 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
584 {
585 b43legacy_write_mac_bssid_templates(dev);
586 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
587 dev->wl->mac_addr);
588 }
589
590 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
591 u16 slot_time)
592 {
593 /* slot_time is in usec. */
594 if (dev->phy.type != B43legacy_PHYTYPE_G)
595 return;
596 b43legacy_write16(dev, 0x684, 510 + slot_time);
597 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
598 slot_time);
599 }
600
601 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
602 {
603 b43legacy_set_slot_time(dev, 9);
604 }
605
606 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
607 {
608 b43legacy_set_slot_time(dev, 20);
609 }
610
611 /* Synchronize IRQ top- and bottom-half.
612 * IRQs must be masked before calling this.
613 * This must not be called with the irq_lock held.
614 */
615 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
616 {
617 synchronize_irq(dev->dev->irq);
618 tasklet_kill(&dev->isr_tasklet);
619 }
620
621 /* DummyTransmission function, as documented on
622 * http://bcm-specs.sipsolutions.net/DummyTransmission
623 */
624 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
625 {
626 struct b43legacy_phy *phy = &dev->phy;
627 unsigned int i;
628 unsigned int max_loop;
629 u16 value;
630 u32 buffer[5] = {
631 0x00000000,
632 0x00D40000,
633 0x00000000,
634 0x01000000,
635 0x00000000,
636 };
637
638 switch (phy->type) {
639 case B43legacy_PHYTYPE_B:
640 case B43legacy_PHYTYPE_G:
641 max_loop = 0xFA;
642 buffer[0] = 0x000B846E;
643 break;
644 default:
645 B43legacy_BUG_ON(1);
646 return;
647 }
648
649 for (i = 0; i < 5; i++)
650 b43legacy_ram_write(dev, i * 4, buffer[i]);
651
652 /* dummy read follows */
653 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
654
655 b43legacy_write16(dev, 0x0568, 0x0000);
656 b43legacy_write16(dev, 0x07C0, 0x0000);
657 b43legacy_write16(dev, 0x050C, 0x0000);
658 b43legacy_write16(dev, 0x0508, 0x0000);
659 b43legacy_write16(dev, 0x050A, 0x0000);
660 b43legacy_write16(dev, 0x054C, 0x0000);
661 b43legacy_write16(dev, 0x056A, 0x0014);
662 b43legacy_write16(dev, 0x0568, 0x0826);
663 b43legacy_write16(dev, 0x0500, 0x0000);
664 b43legacy_write16(dev, 0x0502, 0x0030);
665
666 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
667 b43legacy_radio_write16(dev, 0x0051, 0x0017);
668 for (i = 0x00; i < max_loop; i++) {
669 value = b43legacy_read16(dev, 0x050E);
670 if (value & 0x0080)
671 break;
672 udelay(10);
673 }
674 for (i = 0x00; i < 0x0A; i++) {
675 value = b43legacy_read16(dev, 0x050E);
676 if (value & 0x0400)
677 break;
678 udelay(10);
679 }
680 for (i = 0x00; i < 0x0A; i++) {
681 value = b43legacy_read16(dev, 0x0690);
682 if (!(value & 0x0100))
683 break;
684 udelay(10);
685 }
686 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
687 b43legacy_radio_write16(dev, 0x0051, 0x0037);
688 }
689
690 /* Turn the Analog ON/OFF */
691 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
692 {
693 b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
694 }
695
696 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
697 {
698 u32 tmslow;
699 u32 macctl;
700
701 flags |= B43legacy_TMSLOW_PHYCLKEN;
702 flags |= B43legacy_TMSLOW_PHYRESET;
703 ssb_device_enable(dev->dev, flags);
704 msleep(2); /* Wait for the PLL to turn on. */
705
706 /* Now take the PHY out of Reset again */
707 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
708 tmslow |= SSB_TMSLOW_FGC;
709 tmslow &= ~B43legacy_TMSLOW_PHYRESET;
710 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
711 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
712 msleep(1);
713 tmslow &= ~SSB_TMSLOW_FGC;
714 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
715 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
716 msleep(1);
717
718 /* Turn Analog ON */
719 b43legacy_switch_analog(dev, 1);
720
721 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
722 macctl &= ~B43legacy_MACCTL_GMODE;
723 if (flags & B43legacy_TMSLOW_GMODE) {
724 macctl |= B43legacy_MACCTL_GMODE;
725 dev->phy.gmode = true;
726 } else
727 dev->phy.gmode = false;
728 macctl |= B43legacy_MACCTL_IHR_ENABLED;
729 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
730 }
731
732 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
733 {
734 u32 v0;
735 u32 v1;
736 u16 tmp;
737 struct b43legacy_txstatus stat;
738
739 while (1) {
740 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
741 if (!(v0 & 0x00000001))
742 break;
743 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
744
745 stat.cookie = (v0 >> 16);
746 stat.seq = (v1 & 0x0000FFFF);
747 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
748 tmp = (v0 & 0x0000FFFF);
749 stat.frame_count = ((tmp & 0xF000) >> 12);
750 stat.rts_count = ((tmp & 0x0F00) >> 8);
751 stat.supp_reason = ((tmp & 0x001C) >> 2);
752 stat.pm_indicated = !!(tmp & 0x0080);
753 stat.intermediate = !!(tmp & 0x0040);
754 stat.for_ampdu = !!(tmp & 0x0020);
755 stat.acked = !!(tmp & 0x0002);
756
757 b43legacy_handle_txstatus(dev, &stat);
758 }
759 }
760
761 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
762 {
763 u32 dummy;
764
765 if (dev->dev->id.revision < 5)
766 return;
767 /* Read all entries from the microcode TXstatus FIFO
768 * and throw them away.
769 */
770 while (1) {
771 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
772 if (!(dummy & 0x00000001))
773 break;
774 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
775 }
776 }
777
778 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
779 {
780 u32 val = 0;
781
782 val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
783 val <<= 16;
784 val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
785
786 return val;
787 }
788
789 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
790 {
791 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
792 (jssi & 0x0000FFFF));
793 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
794 (jssi & 0xFFFF0000) >> 16);
795 }
796
797 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
798 {
799 b43legacy_jssi_write(dev, 0x7F7F7F7F);
800 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
801 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
802 | B43legacy_MACCMD_BGNOISE);
803 B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
804 dev->phy.channel);
805 }
806
807 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
808 {
809 /* Top half of Link Quality calculation. */
810
811 if (dev->noisecalc.calculation_running)
812 return;
813 dev->noisecalc.channel_at_start = dev->phy.channel;
814 dev->noisecalc.calculation_running = true;
815 dev->noisecalc.nr_samples = 0;
816
817 b43legacy_generate_noise_sample(dev);
818 }
819
820 static void handle_irq_noise(struct b43legacy_wldev *dev)
821 {
822 struct b43legacy_phy *phy = &dev->phy;
823 u16 tmp;
824 u8 noise[4];
825 u8 i;
826 u8 j;
827 s32 average;
828
829 /* Bottom half of Link Quality calculation. */
830
831 B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
832 if (dev->noisecalc.channel_at_start != phy->channel)
833 goto drop_calculation;
834 *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
835 if (noise[0] == 0x7F || noise[1] == 0x7F ||
836 noise[2] == 0x7F || noise[3] == 0x7F)
837 goto generate_new;
838
839 /* Get the noise samples. */
840 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
841 i = dev->noisecalc.nr_samples;
842 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
843 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
844 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
845 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
846 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
847 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
848 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
849 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
850 dev->noisecalc.nr_samples++;
851 if (dev->noisecalc.nr_samples == 8) {
852 /* Calculate the Link Quality by the noise samples. */
853 average = 0;
854 for (i = 0; i < 8; i++) {
855 for (j = 0; j < 4; j++)
856 average += dev->noisecalc.samples[i][j];
857 }
858 average /= (8 * 4);
859 average *= 125;
860 average += 64;
861 average /= 128;
862 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
863 0x40C);
864 tmp = (tmp / 128) & 0x1F;
865 if (tmp >= 8)
866 average += 2;
867 else
868 average -= 25;
869 if (tmp == 8)
870 average -= 72;
871 else
872 average -= 48;
873
874 dev->stats.link_noise = average;
875 drop_calculation:
876 dev->noisecalc.calculation_running = false;
877 return;
878 }
879 generate_new:
880 b43legacy_generate_noise_sample(dev);
881 }
882
883 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
884 {
885 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
886 /* TODO: PS TBTT */
887 } else {
888 if (1/*FIXME: the last PSpoll frame was sent successfully */)
889 b43legacy_power_saving_ctl_bits(dev, -1, -1);
890 }
891 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
892 dev->dfq_valid = true;
893 }
894
895 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
896 {
897 if (dev->dfq_valid) {
898 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
899 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
900 | B43legacy_MACCMD_DFQ_VALID);
901 dev->dfq_valid = false;
902 }
903 }
904
905 static void handle_irq_pmq(struct b43legacy_wldev *dev)
906 {
907 u32 tmp;
908
909 /* TODO: AP mode. */
910
911 while (1) {
912 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
913 if (!(tmp & 0x00000008))
914 break;
915 }
916 /* 16bit write is odd, but correct. */
917 b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
918 }
919
920 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
921 const u8 *data, u16 size,
922 u16 ram_offset,
923 u16 shm_size_offset, u8 rate)
924 {
925 u32 i;
926 u32 tmp;
927 struct b43legacy_plcp_hdr4 plcp;
928
929 plcp.data = 0;
930 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
931 b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
932 ram_offset += sizeof(u32);
933 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
934 * So leave the first two bytes of the next write blank.
935 */
936 tmp = (u32)(data[0]) << 16;
937 tmp |= (u32)(data[1]) << 24;
938 b43legacy_ram_write(dev, ram_offset, tmp);
939 ram_offset += sizeof(u32);
940 for (i = 2; i < size; i += sizeof(u32)) {
941 tmp = (u32)(data[i + 0]);
942 if (i + 1 < size)
943 tmp |= (u32)(data[i + 1]) << 8;
944 if (i + 2 < size)
945 tmp |= (u32)(data[i + 2]) << 16;
946 if (i + 3 < size)
947 tmp |= (u32)(data[i + 3]) << 24;
948 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
949 }
950 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
951 size + sizeof(struct b43legacy_plcp_hdr6));
952 }
953
954 /* Convert a b43legacy antenna number value to the PHY TX control value. */
955 static u16 b43legacy_antenna_to_phyctl(int antenna)
956 {
957 switch (antenna) {
958 case B43legacy_ANTENNA0:
959 return B43legacy_TX4_PHY_ANT0;
960 case B43legacy_ANTENNA1:
961 return B43legacy_TX4_PHY_ANT1;
962 }
963 return B43legacy_TX4_PHY_ANTLAST;
964 }
965
966 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
967 u16 ram_offset,
968 u16 shm_size_offset)
969 {
970
971 unsigned int i, len, variable_len;
972 const struct ieee80211_mgmt *bcn;
973 const u8 *ie;
974 bool tim_found = false;
975 unsigned int rate;
976 u16 ctl;
977 int antenna;
978 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
979
980 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
981 len = min((size_t)dev->wl->current_beacon->len,
982 0x200 - sizeof(struct b43legacy_plcp_hdr6));
983 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
984
985 b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
986 shm_size_offset, rate);
987
988 /* Write the PHY TX control parameters. */
989 antenna = B43legacy_ANTENNA_DEFAULT;
990 antenna = b43legacy_antenna_to_phyctl(antenna);
991 ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
992 B43legacy_SHM_SH_BEACPHYCTL);
993 /* We can't send beacons with short preamble. Would get PHY errors. */
994 ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
995 ctl &= ~B43legacy_TX4_PHY_ANT;
996 ctl &= ~B43legacy_TX4_PHY_ENC;
997 ctl |= antenna;
998 ctl |= B43legacy_TX4_PHY_ENC_CCK;
999 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1000 B43legacy_SHM_SH_BEACPHYCTL, ctl);
1001
1002 /* Find the position of the TIM and the DTIM_period value
1003 * and write them to SHM. */
1004 ie = bcn->u.beacon.variable;
1005 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1006 for (i = 0; i < variable_len - 2; ) {
1007 uint8_t ie_id, ie_len;
1008
1009 ie_id = ie[i];
1010 ie_len = ie[i + 1];
1011 if (ie_id == 5) {
1012 u16 tim_position;
1013 u16 dtim_period;
1014 /* This is the TIM Information Element */
1015
1016 /* Check whether the ie_len is in the beacon data range. */
1017 if (variable_len < ie_len + 2 + i)
1018 break;
1019 /* A valid TIM is at least 4 bytes long. */
1020 if (ie_len < 4)
1021 break;
1022 tim_found = true;
1023
1024 tim_position = sizeof(struct b43legacy_plcp_hdr6);
1025 tim_position += offsetof(struct ieee80211_mgmt,
1026 u.beacon.variable);
1027 tim_position += i;
1028
1029 dtim_period = ie[i + 3];
1030
1031 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1032 B43legacy_SHM_SH_TIMPOS, tim_position);
1033 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1034 B43legacy_SHM_SH_DTIMP, dtim_period);
1035 break;
1036 }
1037 i += ie_len + 2;
1038 }
1039 if (!tim_found) {
1040 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1041 "beacon template packet. AP or IBSS operation "
1042 "may be broken.\n");
1043 } else
1044 b43legacydbg(dev->wl, "Updated beacon template\n");
1045 }
1046
1047 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1048 u16 shm_offset, u16 size,
1049 struct ieee80211_rate *rate)
1050 {
1051 struct b43legacy_plcp_hdr4 plcp;
1052 u32 tmp;
1053 __le16 dur;
1054
1055 plcp.data = 0;
1056 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1057 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1058 dev->wl->vif,
1059 size,
1060 rate);
1061 /* Write PLCP in two parts and timing for packet transfer */
1062 tmp = le32_to_cpu(plcp.data);
1063 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1064 tmp & 0xFFFF);
1065 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1066 tmp >> 16);
1067 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1068 le16_to_cpu(dur));
1069 }
1070
1071 /* Instead of using custom probe response template, this function
1072 * just patches custom beacon template by:
1073 * 1) Changing packet type
1074 * 2) Patching duration field
1075 * 3) Stripping TIM
1076 */
1077 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1078 u16 *dest_size,
1079 struct ieee80211_rate *rate)
1080 {
1081 const u8 *src_data;
1082 u8 *dest_data;
1083 u16 src_size, elem_size, src_pos, dest_pos;
1084 __le16 dur;
1085 struct ieee80211_hdr *hdr;
1086 size_t ie_start;
1087
1088 src_size = dev->wl->current_beacon->len;
1089 src_data = (const u8 *)dev->wl->current_beacon->data;
1090
1091 /* Get the start offset of the variable IEs in the packet. */
1092 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1093 B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1094 u.beacon.variable));
1095
1096 if (B43legacy_WARN_ON(src_size < ie_start))
1097 return NULL;
1098
1099 dest_data = kmalloc(src_size, GFP_ATOMIC);
1100 if (unlikely(!dest_data))
1101 return NULL;
1102
1103 /* Copy the static data and all Information Elements, except the TIM. */
1104 memcpy(dest_data, src_data, ie_start);
1105 src_pos = ie_start;
1106 dest_pos = ie_start;
1107 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1108 elem_size = src_data[src_pos + 1] + 2;
1109 if (src_data[src_pos] == 5) {
1110 /* This is the TIM. */
1111 continue;
1112 }
1113 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1114 dest_pos += elem_size;
1115 }
1116 *dest_size = dest_pos;
1117 hdr = (struct ieee80211_hdr *)dest_data;
1118
1119 /* Set the frame control. */
1120 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1121 IEEE80211_STYPE_PROBE_RESP);
1122 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1123 dev->wl->vif,
1124 *dest_size,
1125 rate);
1126 hdr->duration_id = dur;
1127
1128 return dest_data;
1129 }
1130
1131 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1132 u16 ram_offset,
1133 u16 shm_size_offset,
1134 struct ieee80211_rate *rate)
1135 {
1136 const u8 *probe_resp_data;
1137 u16 size;
1138
1139 size = dev->wl->current_beacon->len;
1140 probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1141 if (unlikely(!probe_resp_data))
1142 return;
1143
1144 /* Looks like PLCP headers plus packet timings are stored for
1145 * all possible basic rates
1146 */
1147 b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1148 &b43legacy_b_ratetable[0]);
1149 b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1150 &b43legacy_b_ratetable[1]);
1151 b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1152 &b43legacy_b_ratetable[2]);
1153 b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1154 &b43legacy_b_ratetable[3]);
1155
1156 size = min((size_t)size,
1157 0x200 - sizeof(struct b43legacy_plcp_hdr6));
1158 b43legacy_write_template_common(dev, probe_resp_data,
1159 size, ram_offset,
1160 shm_size_offset, rate->hw_value);
1161 kfree(probe_resp_data);
1162 }
1163
1164 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1165 {
1166 struct b43legacy_wl *wl = dev->wl;
1167
1168 if (wl->beacon0_uploaded)
1169 return;
1170 b43legacy_write_beacon_template(dev, 0x68, 0x18);
1171 /* FIXME: Probe resp upload doesn't really belong here,
1172 * but we don't use that feature anyway. */
1173 b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1174 &__b43legacy_ratetable[3]);
1175 wl->beacon0_uploaded = true;
1176 }
1177
1178 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1179 {
1180 struct b43legacy_wl *wl = dev->wl;
1181
1182 if (wl->beacon1_uploaded)
1183 return;
1184 b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1185 wl->beacon1_uploaded = true;
1186 }
1187
1188 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1189 {
1190 struct b43legacy_wl *wl = dev->wl;
1191 u32 cmd, beacon0_valid, beacon1_valid;
1192
1193 if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1194 return;
1195
1196 /* This is the bottom half of the asynchronous beacon update. */
1197
1198 /* Ignore interrupt in the future. */
1199 dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1200
1201 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1202 beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1203 beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1204
1205 /* Schedule interrupt manually, if busy. */
1206 if (beacon0_valid && beacon1_valid) {
1207 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1208 dev->irq_mask |= B43legacy_IRQ_BEACON;
1209 return;
1210 }
1211
1212 if (unlikely(wl->beacon_templates_virgin)) {
1213 /* We never uploaded a beacon before.
1214 * Upload both templates now, but only mark one valid. */
1215 wl->beacon_templates_virgin = false;
1216 b43legacy_upload_beacon0(dev);
1217 b43legacy_upload_beacon1(dev);
1218 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1219 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1220 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1221 } else {
1222 if (!beacon0_valid) {
1223 b43legacy_upload_beacon0(dev);
1224 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1225 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1226 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1227 } else if (!beacon1_valid) {
1228 b43legacy_upload_beacon1(dev);
1229 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1230 cmd |= B43legacy_MACCMD_BEACON1_VALID;
1231 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1232 }
1233 }
1234 }
1235
1236 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1237 {
1238 struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1239 beacon_update_trigger);
1240 struct b43legacy_wldev *dev;
1241
1242 mutex_lock(&wl->mutex);
1243 dev = wl->current_dev;
1244 if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1245 spin_lock_irq(&wl->irq_lock);
1246 /* Update beacon right away or defer to IRQ. */
1247 handle_irq_beacon(dev);
1248 /* The handler might have updated the IRQ mask. */
1249 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1250 dev->irq_mask);
1251 mmiowb();
1252 spin_unlock_irq(&wl->irq_lock);
1253 }
1254 mutex_unlock(&wl->mutex);
1255 }
1256
1257 /* Asynchronously update the packet templates in template RAM.
1258 * Locking: Requires wl->irq_lock to be locked. */
1259 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1260 {
1261 struct sk_buff *beacon;
1262 /* This is the top half of the ansynchronous beacon update. The bottom
1263 * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1264 * sending an invalid beacon. This can happen for example, if the
1265 * firmware transmits a beacon while we are updating it. */
1266
1267 /* We could modify the existing beacon and set the aid bit in the TIM
1268 * field, but that would probably require resizing and moving of data
1269 * within the beacon template. Simply request a new beacon and let
1270 * mac80211 do the hard work. */
1271 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1272 if (unlikely(!beacon))
1273 return;
1274
1275 if (wl->current_beacon)
1276 dev_kfree_skb_any(wl->current_beacon);
1277 wl->current_beacon = beacon;
1278 wl->beacon0_uploaded = false;
1279 wl->beacon1_uploaded = false;
1280 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1281 }
1282
1283 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1284 u16 beacon_int)
1285 {
1286 b43legacy_time_lock(dev);
1287 if (dev->dev->id.revision >= 3) {
1288 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1289 (beacon_int << 16));
1290 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1291 (beacon_int << 10));
1292 } else {
1293 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1294 b43legacy_write16(dev, 0x610, beacon_int);
1295 }
1296 b43legacy_time_unlock(dev);
1297 b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1298 }
1299
1300 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1301 {
1302 }
1303
1304 /* Interrupt handler bottom-half */
1305 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1306 {
1307 u32 reason;
1308 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1309 u32 merged_dma_reason = 0;
1310 int i;
1311 unsigned long flags;
1312
1313 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1314
1315 B43legacy_WARN_ON(b43legacy_status(dev) <
1316 B43legacy_STAT_INITIALIZED);
1317
1318 reason = dev->irq_reason;
1319 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1320 dma_reason[i] = dev->dma_reason[i];
1321 merged_dma_reason |= dma_reason[i];
1322 }
1323
1324 if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1325 b43legacyerr(dev->wl, "MAC transmission error\n");
1326
1327 if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1328 b43legacyerr(dev->wl, "PHY transmission error\n");
1329 rmb();
1330 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1331 b43legacyerr(dev->wl, "Too many PHY TX errors, "
1332 "restarting the controller\n");
1333 b43legacy_controller_restart(dev, "PHY TX errors");
1334 }
1335 }
1336
1337 if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1338 B43legacy_DMAIRQ_NONFATALMASK))) {
1339 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1340 b43legacyerr(dev->wl, "Fatal DMA error: "
1341 "0x%08X, 0x%08X, 0x%08X, "
1342 "0x%08X, 0x%08X, 0x%08X\n",
1343 dma_reason[0], dma_reason[1],
1344 dma_reason[2], dma_reason[3],
1345 dma_reason[4], dma_reason[5]);
1346 b43legacy_controller_restart(dev, "DMA error");
1347 mmiowb();
1348 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1349 return;
1350 }
1351 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1352 b43legacyerr(dev->wl, "DMA error: "
1353 "0x%08X, 0x%08X, 0x%08X, "
1354 "0x%08X, 0x%08X, 0x%08X\n",
1355 dma_reason[0], dma_reason[1],
1356 dma_reason[2], dma_reason[3],
1357 dma_reason[4], dma_reason[5]);
1358 }
1359
1360 if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1361 handle_irq_ucode_debug(dev);
1362 if (reason & B43legacy_IRQ_TBTT_INDI)
1363 handle_irq_tbtt_indication(dev);
1364 if (reason & B43legacy_IRQ_ATIM_END)
1365 handle_irq_atim_end(dev);
1366 if (reason & B43legacy_IRQ_BEACON)
1367 handle_irq_beacon(dev);
1368 if (reason & B43legacy_IRQ_PMQ)
1369 handle_irq_pmq(dev);
1370 if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1371 ;/*TODO*/
1372 if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1373 handle_irq_noise(dev);
1374
1375 /* Check the DMA reason registers for received data. */
1376 if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1377 if (b43legacy_using_pio(dev))
1378 b43legacy_pio_rx(dev->pio.queue0);
1379 else
1380 b43legacy_dma_rx(dev->dma.rx_ring0);
1381 }
1382 B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1383 B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1384 if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1385 if (b43legacy_using_pio(dev))
1386 b43legacy_pio_rx(dev->pio.queue3);
1387 else
1388 b43legacy_dma_rx(dev->dma.rx_ring3);
1389 }
1390 B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1391 B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1392
1393 if (reason & B43legacy_IRQ_TX_OK)
1394 handle_irq_transmit_status(dev);
1395
1396 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1397 mmiowb();
1398 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1399 }
1400
1401 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1402 u16 base, int queueidx)
1403 {
1404 u16 rxctl;
1405
1406 rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1407 if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1408 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1409 else
1410 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1411 }
1412
1413 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1414 {
1415 if (b43legacy_using_pio(dev) &&
1416 (dev->dev->id.revision < 3) &&
1417 (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1418 /* Apply a PIO specific workaround to the dma_reasons */
1419 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1420 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1421 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1422 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1423 }
1424
1425 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1426
1427 b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1428 dev->dma_reason[0]);
1429 b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1430 dev->dma_reason[1]);
1431 b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1432 dev->dma_reason[2]);
1433 b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1434 dev->dma_reason[3]);
1435 b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1436 dev->dma_reason[4]);
1437 b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1438 dev->dma_reason[5]);
1439 }
1440
1441 /* Interrupt handler top-half */
1442 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1443 {
1444 irqreturn_t ret = IRQ_NONE;
1445 struct b43legacy_wldev *dev = dev_id;
1446 u32 reason;
1447
1448 B43legacy_WARN_ON(!dev);
1449
1450 spin_lock(&dev->wl->irq_lock);
1451
1452 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1453 /* This can only happen on shared IRQ lines. */
1454 goto out;
1455 reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1456 if (reason == 0xffffffff) /* shared IRQ */
1457 goto out;
1458 ret = IRQ_HANDLED;
1459 reason &= dev->irq_mask;
1460 if (!reason)
1461 goto out;
1462
1463 dev->dma_reason[0] = b43legacy_read32(dev,
1464 B43legacy_MMIO_DMA0_REASON)
1465 & 0x0001DC00;
1466 dev->dma_reason[1] = b43legacy_read32(dev,
1467 B43legacy_MMIO_DMA1_REASON)
1468 & 0x0000DC00;
1469 dev->dma_reason[2] = b43legacy_read32(dev,
1470 B43legacy_MMIO_DMA2_REASON)
1471 & 0x0000DC00;
1472 dev->dma_reason[3] = b43legacy_read32(dev,
1473 B43legacy_MMIO_DMA3_REASON)
1474 & 0x0001DC00;
1475 dev->dma_reason[4] = b43legacy_read32(dev,
1476 B43legacy_MMIO_DMA4_REASON)
1477 & 0x0000DC00;
1478 dev->dma_reason[5] = b43legacy_read32(dev,
1479 B43legacy_MMIO_DMA5_REASON)
1480 & 0x0000DC00;
1481
1482 b43legacy_interrupt_ack(dev, reason);
1483 /* Disable all IRQs. They are enabled again in the bottom half. */
1484 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1485 /* Save the reason code and call our bottom half. */
1486 dev->irq_reason = reason;
1487 tasklet_schedule(&dev->isr_tasklet);
1488 out:
1489 mmiowb();
1490 spin_unlock(&dev->wl->irq_lock);
1491
1492 return ret;
1493 }
1494
1495 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1496 {
1497 release_firmware(dev->fw.ucode);
1498 dev->fw.ucode = NULL;
1499 release_firmware(dev->fw.pcm);
1500 dev->fw.pcm = NULL;
1501 release_firmware(dev->fw.initvals);
1502 dev->fw.initvals = NULL;
1503 release_firmware(dev->fw.initvals_band);
1504 dev->fw.initvals_band = NULL;
1505 }
1506
1507 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1508 {
1509 b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1510 "Drivers/b43#devicefirmware "
1511 "and download the correct firmware (version 3).\n");
1512 }
1513
1514 static int do_request_fw(struct b43legacy_wldev *dev,
1515 const char *name,
1516 const struct firmware **fw)
1517 {
1518 char path[sizeof(modparam_fwpostfix) + 32];
1519 struct b43legacy_fw_header *hdr;
1520 u32 size;
1521 int err;
1522
1523 if (!name)
1524 return 0;
1525
1526 snprintf(path, ARRAY_SIZE(path),
1527 "b43legacy%s/%s.fw",
1528 modparam_fwpostfix, name);
1529 err = request_firmware(fw, path, dev->dev->dev);
1530 if (err) {
1531 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1532 "or load failed.\n", path);
1533 return err;
1534 }
1535 if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1536 goto err_format;
1537 hdr = (struct b43legacy_fw_header *)((*fw)->data);
1538 switch (hdr->type) {
1539 case B43legacy_FW_TYPE_UCODE:
1540 case B43legacy_FW_TYPE_PCM:
1541 size = be32_to_cpu(hdr->size);
1542 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1543 goto err_format;
1544 /* fallthrough */
1545 case B43legacy_FW_TYPE_IV:
1546 if (hdr->ver != 1)
1547 goto err_format;
1548 break;
1549 default:
1550 goto err_format;
1551 }
1552
1553 return err;
1554
1555 err_format:
1556 b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1557 return -EPROTO;
1558 }
1559
1560 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1561 {
1562 struct b43legacy_firmware *fw = &dev->fw;
1563 const u8 rev = dev->dev->id.revision;
1564 const char *filename;
1565 int err;
1566
1567 /* do dummy read */
1568 ssb_read32(dev->dev, SSB_TMSHIGH);
1569 if (!fw->ucode) {
1570 if (rev == 2)
1571 filename = "ucode2";
1572 else if (rev == 4)
1573 filename = "ucode4";
1574 else
1575 filename = "ucode5";
1576 err = do_request_fw(dev, filename, &fw->ucode);
1577 if (err)
1578 goto err_load;
1579 }
1580 if (!fw->pcm) {
1581 if (rev < 5)
1582 filename = "pcm4";
1583 else
1584 filename = "pcm5";
1585 err = do_request_fw(dev, filename, &fw->pcm);
1586 if (err)
1587 goto err_load;
1588 }
1589 if (!fw->initvals) {
1590 switch (dev->phy.type) {
1591 case B43legacy_PHYTYPE_B:
1592 case B43legacy_PHYTYPE_G:
1593 if ((rev >= 5) && (rev <= 10))
1594 filename = "b0g0initvals5";
1595 else if (rev == 2 || rev == 4)
1596 filename = "b0g0initvals2";
1597 else
1598 goto err_no_initvals;
1599 break;
1600 default:
1601 goto err_no_initvals;
1602 }
1603 err = do_request_fw(dev, filename, &fw->initvals);
1604 if (err)
1605 goto err_load;
1606 }
1607 if (!fw->initvals_band) {
1608 switch (dev->phy.type) {
1609 case B43legacy_PHYTYPE_B:
1610 case B43legacy_PHYTYPE_G:
1611 if ((rev >= 5) && (rev <= 10))
1612 filename = "b0g0bsinitvals5";
1613 else if (rev >= 11)
1614 filename = NULL;
1615 else if (rev == 2 || rev == 4)
1616 filename = NULL;
1617 else
1618 goto err_no_initvals;
1619 break;
1620 default:
1621 goto err_no_initvals;
1622 }
1623 err = do_request_fw(dev, filename, &fw->initvals_band);
1624 if (err)
1625 goto err_load;
1626 }
1627
1628 return 0;
1629
1630 err_load:
1631 b43legacy_print_fw_helptext(dev->wl);
1632 goto error;
1633
1634 err_no_initvals:
1635 err = -ENODEV;
1636 b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1637 "core rev %u\n", dev->phy.type, rev);
1638 goto error;
1639
1640 error:
1641 b43legacy_release_firmware(dev);
1642 return err;
1643 }
1644
1645 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1646 {
1647 struct wiphy *wiphy = dev->wl->hw->wiphy;
1648 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1649 const __be32 *data;
1650 unsigned int i;
1651 unsigned int len;
1652 u16 fwrev;
1653 u16 fwpatch;
1654 u16 fwdate;
1655 u16 fwtime;
1656 u32 tmp, macctl;
1657 int err = 0;
1658
1659 /* Jump the microcode PSM to offset 0 */
1660 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1661 B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1662 macctl |= B43legacy_MACCTL_PSM_JMP0;
1663 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1664 /* Zero out all microcode PSM registers and shared memory. */
1665 for (i = 0; i < 64; i++)
1666 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1667 for (i = 0; i < 4096; i += 2)
1668 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1669
1670 /* Upload Microcode. */
1671 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1672 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1673 b43legacy_shm_control_word(dev,
1674 B43legacy_SHM_UCODE |
1675 B43legacy_SHM_AUTOINC_W,
1676 0x0000);
1677 for (i = 0; i < len; i++) {
1678 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1679 be32_to_cpu(data[i]));
1680 udelay(10);
1681 }
1682
1683 if (dev->fw.pcm) {
1684 /* Upload PCM data. */
1685 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1686 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1687 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1688 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1689 /* No need for autoinc bit in SHM_HW */
1690 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1691 for (i = 0; i < len; i++) {
1692 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1693 be32_to_cpu(data[i]));
1694 udelay(10);
1695 }
1696 }
1697
1698 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1699 B43legacy_IRQ_ALL);
1700
1701 /* Start the microcode PSM */
1702 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1703 macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1704 macctl |= B43legacy_MACCTL_PSM_RUN;
1705 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1706
1707 /* Wait for the microcode to load and respond */
1708 i = 0;
1709 while (1) {
1710 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1711 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1712 break;
1713 i++;
1714 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1715 b43legacyerr(dev->wl, "Microcode not responding\n");
1716 b43legacy_print_fw_helptext(dev->wl);
1717 err = -ENODEV;
1718 goto error;
1719 }
1720 msleep_interruptible(50);
1721 if (signal_pending(current)) {
1722 err = -EINTR;
1723 goto error;
1724 }
1725 }
1726 /* dummy read follows */
1727 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1728
1729 /* Get and check the revisions. */
1730 fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1731 B43legacy_SHM_SH_UCODEREV);
1732 fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1733 B43legacy_SHM_SH_UCODEPATCH);
1734 fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1735 B43legacy_SHM_SH_UCODEDATE);
1736 fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1737 B43legacy_SHM_SH_UCODETIME);
1738
1739 if (fwrev > 0x128) {
1740 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1741 " Only firmware from binary drivers version 3.x"
1742 " is supported. You must change your firmware"
1743 " files.\n");
1744 b43legacy_print_fw_helptext(dev->wl);
1745 err = -EOPNOTSUPP;
1746 goto error;
1747 }
1748 b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1749 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1750 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1751 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1752 fwtime & 0x1F);
1753
1754 dev->fw.rev = fwrev;
1755 dev->fw.patch = fwpatch;
1756
1757 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
1758 dev->fw.rev, dev->fw.patch);
1759 wiphy->hw_version = dev->dev->id.coreid;
1760
1761 return 0;
1762
1763 error:
1764 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1765 macctl &= ~B43legacy_MACCTL_PSM_RUN;
1766 macctl |= B43legacy_MACCTL_PSM_JMP0;
1767 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1768
1769 return err;
1770 }
1771
1772 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1773 const struct b43legacy_iv *ivals,
1774 size_t count,
1775 size_t array_size)
1776 {
1777 const struct b43legacy_iv *iv;
1778 u16 offset;
1779 size_t i;
1780 bool bit32;
1781
1782 BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1783 iv = ivals;
1784 for (i = 0; i < count; i++) {
1785 if (array_size < sizeof(iv->offset_size))
1786 goto err_format;
1787 array_size -= sizeof(iv->offset_size);
1788 offset = be16_to_cpu(iv->offset_size);
1789 bit32 = !!(offset & B43legacy_IV_32BIT);
1790 offset &= B43legacy_IV_OFFSET_MASK;
1791 if (offset >= 0x1000)
1792 goto err_format;
1793 if (bit32) {
1794 u32 value;
1795
1796 if (array_size < sizeof(iv->data.d32))
1797 goto err_format;
1798 array_size -= sizeof(iv->data.d32);
1799
1800 value = get_unaligned_be32(&iv->data.d32);
1801 b43legacy_write32(dev, offset, value);
1802
1803 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1804 sizeof(__be16) +
1805 sizeof(__be32));
1806 } else {
1807 u16 value;
1808
1809 if (array_size < sizeof(iv->data.d16))
1810 goto err_format;
1811 array_size -= sizeof(iv->data.d16);
1812
1813 value = be16_to_cpu(iv->data.d16);
1814 b43legacy_write16(dev, offset, value);
1815
1816 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1817 sizeof(__be16) +
1818 sizeof(__be16));
1819 }
1820 }
1821 if (array_size)
1822 goto err_format;
1823
1824 return 0;
1825
1826 err_format:
1827 b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1828 b43legacy_print_fw_helptext(dev->wl);
1829
1830 return -EPROTO;
1831 }
1832
1833 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1834 {
1835 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1836 const struct b43legacy_fw_header *hdr;
1837 struct b43legacy_firmware *fw = &dev->fw;
1838 const struct b43legacy_iv *ivals;
1839 size_t count;
1840 int err;
1841
1842 hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1843 ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1844 count = be32_to_cpu(hdr->size);
1845 err = b43legacy_write_initvals(dev, ivals, count,
1846 fw->initvals->size - hdr_len);
1847 if (err)
1848 goto out;
1849 if (fw->initvals_band) {
1850 hdr = (const struct b43legacy_fw_header *)
1851 (fw->initvals_band->data);
1852 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1853 + hdr_len);
1854 count = be32_to_cpu(hdr->size);
1855 err = b43legacy_write_initvals(dev, ivals, count,
1856 fw->initvals_band->size - hdr_len);
1857 if (err)
1858 goto out;
1859 }
1860 out:
1861
1862 return err;
1863 }
1864
1865 /* Initialize the GPIOs
1866 * http://bcm-specs.sipsolutions.net/GPIO
1867 */
1868 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1869 {
1870 struct ssb_bus *bus = dev->dev->bus;
1871 struct ssb_device *gpiodev, *pcidev = NULL;
1872 u32 mask;
1873 u32 set;
1874
1875 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1876 b43legacy_read32(dev,
1877 B43legacy_MMIO_MACCTL)
1878 & 0xFFFF3FFF);
1879
1880 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1881 b43legacy_read16(dev,
1882 B43legacy_MMIO_GPIO_MASK)
1883 | 0x000F);
1884
1885 mask = 0x0000001F;
1886 set = 0x0000000F;
1887 if (dev->dev->bus->chip_id == 0x4301) {
1888 mask |= 0x0060;
1889 set |= 0x0060;
1890 }
1891 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1892 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1893 b43legacy_read16(dev,
1894 B43legacy_MMIO_GPIO_MASK)
1895 | 0x0200);
1896 mask |= 0x0200;
1897 set |= 0x0200;
1898 }
1899 if (dev->dev->id.revision >= 2)
1900 mask |= 0x0010; /* FIXME: This is redundant. */
1901
1902 #ifdef CONFIG_SSB_DRIVER_PCICORE
1903 pcidev = bus->pcicore.dev;
1904 #endif
1905 gpiodev = bus->chipco.dev ? : pcidev;
1906 if (!gpiodev)
1907 return 0;
1908 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1909 (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1910 & mask) | set);
1911
1912 return 0;
1913 }
1914
1915 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1916 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1917 {
1918 struct ssb_bus *bus = dev->dev->bus;
1919 struct ssb_device *gpiodev, *pcidev = NULL;
1920
1921 #ifdef CONFIG_SSB_DRIVER_PCICORE
1922 pcidev = bus->pcicore.dev;
1923 #endif
1924 gpiodev = bus->chipco.dev ? : pcidev;
1925 if (!gpiodev)
1926 return;
1927 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1928 }
1929
1930 /* http://bcm-specs.sipsolutions.net/EnableMac */
1931 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1932 {
1933 dev->mac_suspended--;
1934 B43legacy_WARN_ON(dev->mac_suspended < 0);
1935 B43legacy_WARN_ON(irqs_disabled());
1936 if (dev->mac_suspended == 0) {
1937 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1938 b43legacy_read32(dev,
1939 B43legacy_MMIO_MACCTL)
1940 | B43legacy_MACCTL_ENABLED);
1941 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1942 B43legacy_IRQ_MAC_SUSPENDED);
1943 /* the next two are dummy reads */
1944 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1945 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1946 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1947
1948 /* Re-enable IRQs. */
1949 spin_lock_irq(&dev->wl->irq_lock);
1950 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1951 dev->irq_mask);
1952 spin_unlock_irq(&dev->wl->irq_lock);
1953 }
1954 }
1955
1956 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1957 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1958 {
1959 int i;
1960 u32 tmp;
1961
1962 might_sleep();
1963 B43legacy_WARN_ON(irqs_disabled());
1964 B43legacy_WARN_ON(dev->mac_suspended < 0);
1965
1966 if (dev->mac_suspended == 0) {
1967 /* Mask IRQs before suspending MAC. Otherwise
1968 * the MAC stays busy and won't suspend. */
1969 spin_lock_irq(&dev->wl->irq_lock);
1970 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1971 spin_unlock_irq(&dev->wl->irq_lock);
1972 b43legacy_synchronize_irq(dev);
1973
1974 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1975 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1976 b43legacy_read32(dev,
1977 B43legacy_MMIO_MACCTL)
1978 & ~B43legacy_MACCTL_ENABLED);
1979 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1980 for (i = 40; i; i--) {
1981 tmp = b43legacy_read32(dev,
1982 B43legacy_MMIO_GEN_IRQ_REASON);
1983 if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1984 goto out;
1985 msleep(1);
1986 }
1987 b43legacyerr(dev->wl, "MAC suspend failed\n");
1988 }
1989 out:
1990 dev->mac_suspended++;
1991 }
1992
1993 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1994 {
1995 struct b43legacy_wl *wl = dev->wl;
1996 u32 ctl;
1997 u16 cfp_pretbtt;
1998
1999 ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2000 /* Reset status to STA infrastructure mode. */
2001 ctl &= ~B43legacy_MACCTL_AP;
2002 ctl &= ~B43legacy_MACCTL_KEEP_CTL;
2003 ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
2004 ctl &= ~B43legacy_MACCTL_KEEP_BAD;
2005 ctl &= ~B43legacy_MACCTL_PROMISC;
2006 ctl &= ~B43legacy_MACCTL_BEACPROMISC;
2007 ctl |= B43legacy_MACCTL_INFRA;
2008
2009 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
2010 ctl |= B43legacy_MACCTL_AP;
2011 else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
2012 ctl &= ~B43legacy_MACCTL_INFRA;
2013
2014 if (wl->filter_flags & FIF_CONTROL)
2015 ctl |= B43legacy_MACCTL_KEEP_CTL;
2016 if (wl->filter_flags & FIF_FCSFAIL)
2017 ctl |= B43legacy_MACCTL_KEEP_BAD;
2018 if (wl->filter_flags & FIF_PLCPFAIL)
2019 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
2020 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2021 ctl |= B43legacy_MACCTL_PROMISC;
2022 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2023 ctl |= B43legacy_MACCTL_BEACPROMISC;
2024
2025 /* Workaround: On old hardware the HW-MAC-address-filter
2026 * doesn't work properly, so always run promisc in filter
2027 * it in software. */
2028 if (dev->dev->id.revision <= 4)
2029 ctl |= B43legacy_MACCTL_PROMISC;
2030
2031 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2032
2033 cfp_pretbtt = 2;
2034 if ((ctl & B43legacy_MACCTL_INFRA) &&
2035 !(ctl & B43legacy_MACCTL_AP)) {
2036 if (dev->dev->bus->chip_id == 0x4306 &&
2037 dev->dev->bus->chip_rev == 3)
2038 cfp_pretbtt = 100;
2039 else
2040 cfp_pretbtt = 50;
2041 }
2042 b43legacy_write16(dev, 0x612, cfp_pretbtt);
2043 }
2044
2045 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2046 u16 rate,
2047 int is_ofdm)
2048 {
2049 u16 offset;
2050
2051 if (is_ofdm) {
2052 offset = 0x480;
2053 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2054 } else {
2055 offset = 0x4C0;
2056 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2057 }
2058 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2059 b43legacy_shm_read16(dev,
2060 B43legacy_SHM_SHARED, offset));
2061 }
2062
2063 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2064 {
2065 switch (dev->phy.type) {
2066 case B43legacy_PHYTYPE_G:
2067 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2068 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2069 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2070 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2071 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2072 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2073 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2074 /* fallthrough */
2075 case B43legacy_PHYTYPE_B:
2076 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2077 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2078 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2079 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2080 break;
2081 default:
2082 B43legacy_BUG_ON(1);
2083 }
2084 }
2085
2086 /* Set the TX-Antenna for management frames sent by firmware. */
2087 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2088 int antenna)
2089 {
2090 u16 ant = 0;
2091 u16 tmp;
2092
2093 switch (antenna) {
2094 case B43legacy_ANTENNA0:
2095 ant |= B43legacy_TX4_PHY_ANT0;
2096 break;
2097 case B43legacy_ANTENNA1:
2098 ant |= B43legacy_TX4_PHY_ANT1;
2099 break;
2100 case B43legacy_ANTENNA_AUTO:
2101 ant |= B43legacy_TX4_PHY_ANTLAST;
2102 break;
2103 default:
2104 B43legacy_BUG_ON(1);
2105 }
2106
2107 /* FIXME We also need to set the other flags of the PHY control
2108 * field somewhere. */
2109
2110 /* For Beacons */
2111 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2112 B43legacy_SHM_SH_BEACPHYCTL);
2113 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2114 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2115 B43legacy_SHM_SH_BEACPHYCTL, tmp);
2116 /* For ACK/CTS */
2117 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2118 B43legacy_SHM_SH_ACKCTSPHYCTL);
2119 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2120 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2121 B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2122 /* For Probe Resposes */
2123 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2124 B43legacy_SHM_SH_PRPHYCTL);
2125 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2126 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2127 B43legacy_SHM_SH_PRPHYCTL, tmp);
2128 }
2129
2130 /* This is the opposite of b43legacy_chip_init() */
2131 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2132 {
2133 b43legacy_radio_turn_off(dev, 1);
2134 b43legacy_gpio_cleanup(dev);
2135 /* firmware is released later */
2136 }
2137
2138 /* Initialize the chip
2139 * http://bcm-specs.sipsolutions.net/ChipInit
2140 */
2141 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2142 {
2143 struct b43legacy_phy *phy = &dev->phy;
2144 int err;
2145 int tmp;
2146 u32 value32, macctl;
2147 u16 value16;
2148
2149 /* Initialize the MAC control */
2150 macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2151 if (dev->phy.gmode)
2152 macctl |= B43legacy_MACCTL_GMODE;
2153 macctl |= B43legacy_MACCTL_INFRA;
2154 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2155
2156 err = b43legacy_request_firmware(dev);
2157 if (err)
2158 goto out;
2159 err = b43legacy_upload_microcode(dev);
2160 if (err)
2161 goto out; /* firmware is released later */
2162
2163 err = b43legacy_gpio_init(dev);
2164 if (err)
2165 goto out; /* firmware is released later */
2166
2167 err = b43legacy_upload_initvals(dev);
2168 if (err)
2169 goto err_gpio_clean;
2170 b43legacy_radio_turn_on(dev);
2171
2172 b43legacy_write16(dev, 0x03E6, 0x0000);
2173 err = b43legacy_phy_init(dev);
2174 if (err)
2175 goto err_radio_off;
2176
2177 /* Select initial Interference Mitigation. */
2178 tmp = phy->interfmode;
2179 phy->interfmode = B43legacy_INTERFMODE_NONE;
2180 b43legacy_radio_set_interference_mitigation(dev, tmp);
2181
2182 b43legacy_phy_set_antenna_diversity(dev);
2183 b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2184
2185 if (phy->type == B43legacy_PHYTYPE_B) {
2186 value16 = b43legacy_read16(dev, 0x005E);
2187 value16 |= 0x0004;
2188 b43legacy_write16(dev, 0x005E, value16);
2189 }
2190 b43legacy_write32(dev, 0x0100, 0x01000000);
2191 if (dev->dev->id.revision < 5)
2192 b43legacy_write32(dev, 0x010C, 0x01000000);
2193
2194 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2195 value32 &= ~B43legacy_MACCTL_INFRA;
2196 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2197 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2198 value32 |= B43legacy_MACCTL_INFRA;
2199 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2200
2201 if (b43legacy_using_pio(dev)) {
2202 b43legacy_write32(dev, 0x0210, 0x00000100);
2203 b43legacy_write32(dev, 0x0230, 0x00000100);
2204 b43legacy_write32(dev, 0x0250, 0x00000100);
2205 b43legacy_write32(dev, 0x0270, 0x00000100);
2206 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2207 0x0000);
2208 }
2209
2210 /* Probe Response Timeout value */
2211 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2212 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2213
2214 /* Initially set the wireless operation mode. */
2215 b43legacy_adjust_opmode(dev);
2216
2217 if (dev->dev->id.revision < 3) {
2218 b43legacy_write16(dev, 0x060E, 0x0000);
2219 b43legacy_write16(dev, 0x0610, 0x8000);
2220 b43legacy_write16(dev, 0x0604, 0x0000);
2221 b43legacy_write16(dev, 0x0606, 0x0200);
2222 } else {
2223 b43legacy_write32(dev, 0x0188, 0x80000000);
2224 b43legacy_write32(dev, 0x018C, 0x02000000);
2225 }
2226 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2227 b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2228 b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2229 b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2230 b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2231 b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2232 b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2233
2234 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2235 value32 |= B43legacy_TMSLOW_MACPHYCLKEN;
2236 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2237
2238 b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2239 dev->dev->bus->chipco.fast_pwrup_delay);
2240
2241 /* PHY TX errors counter. */
2242 atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2243
2244 B43legacy_WARN_ON(err != 0);
2245 b43legacydbg(dev->wl, "Chip initialized\n");
2246 out:
2247 return err;
2248
2249 err_radio_off:
2250 b43legacy_radio_turn_off(dev, 1);
2251 err_gpio_clean:
2252 b43legacy_gpio_cleanup(dev);
2253 goto out;
2254 }
2255
2256 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2257 {
2258 struct b43legacy_phy *phy = &dev->phy;
2259
2260 if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2261 return;
2262
2263 b43legacy_mac_suspend(dev);
2264 b43legacy_phy_lo_g_measure(dev);
2265 b43legacy_mac_enable(dev);
2266 }
2267
2268 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2269 {
2270 b43legacy_phy_lo_mark_all_unused(dev);
2271 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2272 b43legacy_mac_suspend(dev);
2273 b43legacy_calc_nrssi_slope(dev);
2274 b43legacy_mac_enable(dev);
2275 }
2276 }
2277
2278 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2279 {
2280 /* Update device statistics. */
2281 b43legacy_calculate_link_quality(dev);
2282 }
2283
2284 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2285 {
2286 b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2287
2288 atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2289 wmb();
2290 }
2291
2292 static void do_periodic_work(struct b43legacy_wldev *dev)
2293 {
2294 unsigned int state;
2295
2296 state = dev->periodic_state;
2297 if (state % 8 == 0)
2298 b43legacy_periodic_every120sec(dev);
2299 if (state % 4 == 0)
2300 b43legacy_periodic_every60sec(dev);
2301 if (state % 2 == 0)
2302 b43legacy_periodic_every30sec(dev);
2303 b43legacy_periodic_every15sec(dev);
2304 }
2305
2306 /* Periodic work locking policy:
2307 * The whole periodic work handler is protected by
2308 * wl->mutex. If another lock is needed somewhere in the
2309 * pwork callchain, it's acquired in-place, where it's needed.
2310 */
2311 static void b43legacy_periodic_work_handler(struct work_struct *work)
2312 {
2313 struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2314 periodic_work.work);
2315 struct b43legacy_wl *wl = dev->wl;
2316 unsigned long delay;
2317
2318 mutex_lock(&wl->mutex);
2319
2320 if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2321 goto out;
2322 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2323 goto out_requeue;
2324
2325 do_periodic_work(dev);
2326
2327 dev->periodic_state++;
2328 out_requeue:
2329 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2330 delay = msecs_to_jiffies(50);
2331 else
2332 delay = round_jiffies_relative(HZ * 15);
2333 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2334 out:
2335 mutex_unlock(&wl->mutex);
2336 }
2337
2338 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2339 {
2340 struct delayed_work *work = &dev->periodic_work;
2341
2342 dev->periodic_state = 0;
2343 INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2344 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2345 }
2346
2347 /* Validate access to the chip (SHM) */
2348 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2349 {
2350 u32 value;
2351 u32 shm_backup;
2352
2353 shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2354 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2355 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2356 0xAA5555AA)
2357 goto error;
2358 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2359 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2360 0x55AAAA55)
2361 goto error;
2362 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2363
2364 value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2365 if ((value | B43legacy_MACCTL_GMODE) !=
2366 (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2367 goto error;
2368
2369 value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2370 if (value)
2371 goto error;
2372
2373 return 0;
2374 error:
2375 b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2376 return -ENODEV;
2377 }
2378
2379 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2380 {
2381 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2382 B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2383 dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2384 0x0056);
2385 /* KTP is a word address, but we address SHM bytewise.
2386 * So multiply by two.
2387 */
2388 dev->ktp *= 2;
2389 if (dev->dev->id.revision >= 5)
2390 /* Number of RCMTA address slots */
2391 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2392 dev->max_nr_keys - 8);
2393 }
2394
2395 #ifdef CONFIG_B43LEGACY_HWRNG
2396 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2397 {
2398 struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2399 unsigned long flags;
2400
2401 /* Don't take wl->mutex here, as it could deadlock with
2402 * hwrng internal locking. It's not needed to take
2403 * wl->mutex here, anyway. */
2404
2405 spin_lock_irqsave(&wl->irq_lock, flags);
2406 *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2407 spin_unlock_irqrestore(&wl->irq_lock, flags);
2408
2409 return (sizeof(u16));
2410 }
2411 #endif
2412
2413 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2414 {
2415 #ifdef CONFIG_B43LEGACY_HWRNG
2416 if (wl->rng_initialized)
2417 hwrng_unregister(&wl->rng);
2418 #endif
2419 }
2420
2421 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2422 {
2423 int err = 0;
2424
2425 #ifdef CONFIG_B43LEGACY_HWRNG
2426 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2427 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2428 wl->rng.name = wl->rng_name;
2429 wl->rng.data_read = b43legacy_rng_read;
2430 wl->rng.priv = (unsigned long)wl;
2431 wl->rng_initialized = 1;
2432 err = hwrng_register(&wl->rng);
2433 if (err) {
2434 wl->rng_initialized = 0;
2435 b43legacyerr(wl, "Failed to register the random "
2436 "number generator (%d)\n", err);
2437 }
2438
2439 #endif
2440 return err;
2441 }
2442
2443 static void b43legacy_tx_work(struct work_struct *work)
2444 {
2445 struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
2446 tx_work);
2447 struct b43legacy_wldev *dev;
2448 struct sk_buff *skb;
2449 int queue_num;
2450 int err = 0;
2451
2452 mutex_lock(&wl->mutex);
2453 dev = wl->current_dev;
2454 if (unlikely(!dev || b43legacy_status(dev) < B43legacy_STAT_STARTED)) {
2455 mutex_unlock(&wl->mutex);
2456 return;
2457 }
2458
2459 for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) {
2460 while (skb_queue_len(&wl->tx_queue[queue_num])) {
2461 skb = skb_dequeue(&wl->tx_queue[queue_num]);
2462 if (b43legacy_using_pio(dev))
2463 err = b43legacy_pio_tx(dev, skb);
2464 else
2465 err = b43legacy_dma_tx(dev, skb);
2466 if (err == -ENOSPC) {
2467 wl->tx_queue_stopped[queue_num] = 1;
2468 ieee80211_stop_queue(wl->hw, queue_num);
2469 skb_queue_head(&wl->tx_queue[queue_num], skb);
2470 break;
2471 }
2472 if (unlikely(err))
2473 dev_kfree_skb(skb); /* Drop it */
2474 err = 0;
2475 }
2476
2477 if (!err)
2478 wl->tx_queue_stopped[queue_num] = 0;
2479 }
2480
2481 mutex_unlock(&wl->mutex);
2482 }
2483
2484 static void b43legacy_op_tx(struct ieee80211_hw *hw,
2485 struct sk_buff *skb)
2486 {
2487 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2488
2489 if (unlikely(skb->len < 2 + 2 + 6)) {
2490 /* Too short, this can't be a valid frame. */
2491 dev_kfree_skb_any(skb);
2492 return;
2493 }
2494 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags);
2495
2496 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
2497 if (!wl->tx_queue_stopped[skb->queue_mapping])
2498 ieee80211_queue_work(wl->hw, &wl->tx_work);
2499 else
2500 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
2501 }
2502
2503 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
2504 struct ieee80211_vif *vif, u16 queue,
2505 const struct ieee80211_tx_queue_params *params)
2506 {
2507 return 0;
2508 }
2509
2510 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2511 struct ieee80211_low_level_stats *stats)
2512 {
2513 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2514 unsigned long flags;
2515
2516 spin_lock_irqsave(&wl->irq_lock, flags);
2517 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2518 spin_unlock_irqrestore(&wl->irq_lock, flags);
2519
2520 return 0;
2521 }
2522
2523 static const char *phymode_to_string(unsigned int phymode)
2524 {
2525 switch (phymode) {
2526 case B43legacy_PHYMODE_B:
2527 return "B";
2528 case B43legacy_PHYMODE_G:
2529 return "G";
2530 default:
2531 B43legacy_BUG_ON(1);
2532 }
2533 return "";
2534 }
2535
2536 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2537 unsigned int phymode,
2538 struct b43legacy_wldev **dev,
2539 bool *gmode)
2540 {
2541 struct b43legacy_wldev *d;
2542
2543 list_for_each_entry(d, &wl->devlist, list) {
2544 if (d->phy.possible_phymodes & phymode) {
2545 /* Ok, this device supports the PHY-mode.
2546 * Set the gmode bit. */
2547 *gmode = true;
2548 *dev = d;
2549
2550 return 0;
2551 }
2552 }
2553
2554 return -ESRCH;
2555 }
2556
2557 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2558 {
2559 struct ssb_device *sdev = dev->dev;
2560 u32 tmslow;
2561
2562 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2563 tmslow &= ~B43legacy_TMSLOW_GMODE;
2564 tmslow |= B43legacy_TMSLOW_PHYRESET;
2565 tmslow |= SSB_TMSLOW_FGC;
2566 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2567 msleep(1);
2568
2569 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2570 tmslow &= ~SSB_TMSLOW_FGC;
2571 tmslow |= B43legacy_TMSLOW_PHYRESET;
2572 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2573 msleep(1);
2574 }
2575
2576 /* Expects wl->mutex locked */
2577 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2578 unsigned int new_mode)
2579 {
2580 struct b43legacy_wldev *uninitialized_var(up_dev);
2581 struct b43legacy_wldev *down_dev;
2582 int err;
2583 bool gmode = false;
2584 int prev_status;
2585
2586 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2587 if (err) {
2588 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2589 phymode_to_string(new_mode));
2590 return err;
2591 }
2592 if ((up_dev == wl->current_dev) &&
2593 (!!wl->current_dev->phy.gmode == !!gmode))
2594 /* This device is already running. */
2595 return 0;
2596 b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2597 phymode_to_string(new_mode));
2598 down_dev = wl->current_dev;
2599
2600 prev_status = b43legacy_status(down_dev);
2601 /* Shutdown the currently running core. */
2602 if (prev_status >= B43legacy_STAT_STARTED)
2603 b43legacy_wireless_core_stop(down_dev);
2604 if (prev_status >= B43legacy_STAT_INITIALIZED)
2605 b43legacy_wireless_core_exit(down_dev);
2606
2607 if (down_dev != up_dev)
2608 /* We switch to a different core, so we put PHY into
2609 * RESET on the old core. */
2610 b43legacy_put_phy_into_reset(down_dev);
2611
2612 /* Now start the new core. */
2613 up_dev->phy.gmode = gmode;
2614 if (prev_status >= B43legacy_STAT_INITIALIZED) {
2615 err = b43legacy_wireless_core_init(up_dev);
2616 if (err) {
2617 b43legacyerr(wl, "Fatal: Could not initialize device"
2618 " for newly selected %s-PHY mode\n",
2619 phymode_to_string(new_mode));
2620 goto init_failure;
2621 }
2622 }
2623 if (prev_status >= B43legacy_STAT_STARTED) {
2624 err = b43legacy_wireless_core_start(up_dev);
2625 if (err) {
2626 b43legacyerr(wl, "Fatal: Coult not start device for "
2627 "newly selected %s-PHY mode\n",
2628 phymode_to_string(new_mode));
2629 b43legacy_wireless_core_exit(up_dev);
2630 goto init_failure;
2631 }
2632 }
2633 B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2634
2635 b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2636
2637 wl->current_dev = up_dev;
2638
2639 return 0;
2640 init_failure:
2641 /* Whoops, failed to init the new core. No core is operating now. */
2642 wl->current_dev = NULL;
2643 return err;
2644 }
2645
2646 /* Write the short and long frame retry limit values. */
2647 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2648 unsigned int short_retry,
2649 unsigned int long_retry)
2650 {
2651 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2652 * the chip-internal counter. */
2653 short_retry = min(short_retry, (unsigned int)0xF);
2654 long_retry = min(long_retry, (unsigned int)0xF);
2655
2656 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2657 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2658 }
2659
2660 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2661 u32 changed)
2662 {
2663 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2664 struct b43legacy_wldev *dev;
2665 struct b43legacy_phy *phy;
2666 struct ieee80211_conf *conf = &hw->conf;
2667 unsigned long flags;
2668 unsigned int new_phymode = 0xFFFF;
2669 int antenna_tx;
2670 int err = 0;
2671
2672 antenna_tx = B43legacy_ANTENNA_DEFAULT;
2673
2674 mutex_lock(&wl->mutex);
2675 dev = wl->current_dev;
2676 phy = &dev->phy;
2677
2678 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2679 b43legacy_set_retry_limits(dev,
2680 conf->short_frame_max_tx_count,
2681 conf->long_frame_max_tx_count);
2682 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2683 if (!changed)
2684 goto out_unlock_mutex;
2685
2686 /* Switch the PHY mode (if necessary). */
2687 switch (conf->channel->band) {
2688 case IEEE80211_BAND_2GHZ:
2689 if (phy->type == B43legacy_PHYTYPE_B)
2690 new_phymode = B43legacy_PHYMODE_B;
2691 else
2692 new_phymode = B43legacy_PHYMODE_G;
2693 break;
2694 default:
2695 B43legacy_WARN_ON(1);
2696 }
2697 err = b43legacy_switch_phymode(wl, new_phymode);
2698 if (err)
2699 goto out_unlock_mutex;
2700
2701 /* Disable IRQs while reconfiguring the device.
2702 * This makes it possible to drop the spinlock throughout
2703 * the reconfiguration process. */
2704 spin_lock_irqsave(&wl->irq_lock, flags);
2705 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2706 spin_unlock_irqrestore(&wl->irq_lock, flags);
2707 goto out_unlock_mutex;
2708 }
2709 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2710 spin_unlock_irqrestore(&wl->irq_lock, flags);
2711 b43legacy_synchronize_irq(dev);
2712
2713 /* Switch to the requested channel.
2714 * The firmware takes care of races with the TX handler. */
2715 if (conf->channel->hw_value != phy->channel)
2716 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2717
2718 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
2719
2720 /* Adjust the desired TX power level. */
2721 if (conf->power_level != 0) {
2722 if (conf->power_level != phy->power_level) {
2723 phy->power_level = conf->power_level;
2724 b43legacy_phy_xmitpower(dev);
2725 }
2726 }
2727
2728 /* Antennas for RX and management frame TX. */
2729 b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2730
2731 if (wl->radio_enabled != phy->radio_on) {
2732 if (wl->radio_enabled) {
2733 b43legacy_radio_turn_on(dev);
2734 b43legacyinfo(dev->wl, "Radio turned on by software\n");
2735 if (!dev->radio_hw_enable)
2736 b43legacyinfo(dev->wl, "The hardware RF-kill"
2737 " button still turns the radio"
2738 " physically off. Press the"
2739 " button to turn it on.\n");
2740 } else {
2741 b43legacy_radio_turn_off(dev, 0);
2742 b43legacyinfo(dev->wl, "Radio turned off by"
2743 " software\n");
2744 }
2745 }
2746
2747 spin_lock_irqsave(&wl->irq_lock, flags);
2748 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2749 mmiowb();
2750 spin_unlock_irqrestore(&wl->irq_lock, flags);
2751 out_unlock_mutex:
2752 mutex_unlock(&wl->mutex);
2753
2754 return err;
2755 }
2756
2757 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2758 {
2759 struct ieee80211_supported_band *sband =
2760 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2761 struct ieee80211_rate *rate;
2762 int i;
2763 u16 basic, direct, offset, basic_offset, rateptr;
2764
2765 for (i = 0; i < sband->n_bitrates; i++) {
2766 rate = &sband->bitrates[i];
2767
2768 if (b43legacy_is_cck_rate(rate->hw_value)) {
2769 direct = B43legacy_SHM_SH_CCKDIRECT;
2770 basic = B43legacy_SHM_SH_CCKBASIC;
2771 offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2772 offset &= 0xF;
2773 } else {
2774 direct = B43legacy_SHM_SH_OFDMDIRECT;
2775 basic = B43legacy_SHM_SH_OFDMBASIC;
2776 offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2777 offset &= 0xF;
2778 }
2779
2780 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2781
2782 if (b43legacy_is_cck_rate(rate->hw_value)) {
2783 basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2784 basic_offset &= 0xF;
2785 } else {
2786 basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2787 basic_offset &= 0xF;
2788 }
2789
2790 /*
2791 * Get the pointer that we need to point to
2792 * from the direct map
2793 */
2794 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2795 direct + 2 * basic_offset);
2796 /* and write it to the basic map */
2797 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2798 basic + 2 * offset, rateptr);
2799 }
2800 }
2801
2802 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2803 struct ieee80211_vif *vif,
2804 struct ieee80211_bss_conf *conf,
2805 u32 changed)
2806 {
2807 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2808 struct b43legacy_wldev *dev;
2809 unsigned long flags;
2810
2811 mutex_lock(&wl->mutex);
2812 B43legacy_WARN_ON(wl->vif != vif);
2813
2814 dev = wl->current_dev;
2815
2816 /* Disable IRQs while reconfiguring the device.
2817 * This makes it possible to drop the spinlock throughout
2818 * the reconfiguration process. */
2819 spin_lock_irqsave(&wl->irq_lock, flags);
2820 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2821 spin_unlock_irqrestore(&wl->irq_lock, flags);
2822 goto out_unlock_mutex;
2823 }
2824 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2825
2826 if (changed & BSS_CHANGED_BSSID) {
2827 b43legacy_synchronize_irq(dev);
2828
2829 if (conf->bssid)
2830 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2831 else
2832 memset(wl->bssid, 0, ETH_ALEN);
2833 }
2834
2835 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2836 if (changed & BSS_CHANGED_BEACON &&
2837 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2838 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2839 b43legacy_update_templates(wl);
2840
2841 if (changed & BSS_CHANGED_BSSID)
2842 b43legacy_write_mac_bssid_templates(dev);
2843 }
2844 spin_unlock_irqrestore(&wl->irq_lock, flags);
2845
2846 b43legacy_mac_suspend(dev);
2847
2848 if (changed & BSS_CHANGED_BEACON_INT &&
2849 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2850 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2851 b43legacy_set_beacon_int(dev, conf->beacon_int);
2852
2853 if (changed & BSS_CHANGED_BASIC_RATES)
2854 b43legacy_update_basic_rates(dev, conf->basic_rates);
2855
2856 if (changed & BSS_CHANGED_ERP_SLOT) {
2857 if (conf->use_short_slot)
2858 b43legacy_short_slot_timing_enable(dev);
2859 else
2860 b43legacy_short_slot_timing_disable(dev);
2861 }
2862
2863 b43legacy_mac_enable(dev);
2864
2865 spin_lock_irqsave(&wl->irq_lock, flags);
2866 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2867 /* XXX: why? */
2868 mmiowb();
2869 spin_unlock_irqrestore(&wl->irq_lock, flags);
2870 out_unlock_mutex:
2871 mutex_unlock(&wl->mutex);
2872 }
2873
2874 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2875 unsigned int changed,
2876 unsigned int *fflags,u64 multicast)
2877 {
2878 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2879 struct b43legacy_wldev *dev = wl->current_dev;
2880 unsigned long flags;
2881
2882 if (!dev) {
2883 *fflags = 0;
2884 return;
2885 }
2886
2887 spin_lock_irqsave(&wl->irq_lock, flags);
2888 *fflags &= FIF_PROMISC_IN_BSS |
2889 FIF_ALLMULTI |
2890 FIF_FCSFAIL |
2891 FIF_PLCPFAIL |
2892 FIF_CONTROL |
2893 FIF_OTHER_BSS |
2894 FIF_BCN_PRBRESP_PROMISC;
2895
2896 changed &= FIF_PROMISC_IN_BSS |
2897 FIF_ALLMULTI |
2898 FIF_FCSFAIL |
2899 FIF_PLCPFAIL |
2900 FIF_CONTROL |
2901 FIF_OTHER_BSS |
2902 FIF_BCN_PRBRESP_PROMISC;
2903
2904 wl->filter_flags = *fflags;
2905
2906 if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2907 b43legacy_adjust_opmode(dev);
2908 spin_unlock_irqrestore(&wl->irq_lock, flags);
2909 }
2910
2911 /* Locking: wl->mutex */
2912 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2913 {
2914 struct b43legacy_wl *wl = dev->wl;
2915 unsigned long flags;
2916 int queue_num;
2917
2918 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2919 return;
2920
2921 /* Disable and sync interrupts. We must do this before than
2922 * setting the status to INITIALIZED, as the interrupt handler
2923 * won't care about IRQs then. */
2924 spin_lock_irqsave(&wl->irq_lock, flags);
2925 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2926 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2927 spin_unlock_irqrestore(&wl->irq_lock, flags);
2928 b43legacy_synchronize_irq(dev);
2929
2930 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2931
2932 mutex_unlock(&wl->mutex);
2933 /* Must unlock as it would otherwise deadlock. No races here.
2934 * Cancel the possibly running self-rearming periodic work. */
2935 cancel_delayed_work_sync(&dev->periodic_work);
2936 cancel_work_sync(&wl->tx_work);
2937 mutex_lock(&wl->mutex);
2938
2939 /* Drain all TX queues. */
2940 for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) {
2941 while (skb_queue_len(&wl->tx_queue[queue_num]))
2942 dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num]));
2943 }
2944
2945 b43legacy_mac_suspend(dev);
2946 free_irq(dev->dev->irq, dev);
2947 b43legacydbg(wl, "Wireless interface stopped\n");
2948 }
2949
2950 /* Locking: wl->mutex */
2951 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2952 {
2953 int err;
2954
2955 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2956
2957 drain_txstatus_queue(dev);
2958 err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2959 IRQF_SHARED, KBUILD_MODNAME, dev);
2960 if (err) {
2961 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2962 dev->dev->irq);
2963 goto out;
2964 }
2965 /* We are ready to run. */
2966 ieee80211_wake_queues(dev->wl->hw);
2967 b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2968
2969 /* Start data flow (TX/RX) */
2970 b43legacy_mac_enable(dev);
2971 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2972
2973 /* Start maintenance work */
2974 b43legacy_periodic_tasks_setup(dev);
2975
2976 b43legacydbg(dev->wl, "Wireless interface started\n");
2977 out:
2978 return err;
2979 }
2980
2981 /* Get PHY and RADIO versioning numbers */
2982 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2983 {
2984 struct b43legacy_phy *phy = &dev->phy;
2985 u32 tmp;
2986 u8 analog_type;
2987 u8 phy_type;
2988 u8 phy_rev;
2989 u16 radio_manuf;
2990 u16 radio_ver;
2991 u16 radio_rev;
2992 int unsupported = 0;
2993
2994 /* Get PHY versioning */
2995 tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2996 analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2997 >> B43legacy_PHYVER_ANALOG_SHIFT;
2998 phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2999 phy_rev = (tmp & B43legacy_PHYVER_VERSION);
3000 switch (phy_type) {
3001 case B43legacy_PHYTYPE_B:
3002 if (phy_rev != 2 && phy_rev != 4
3003 && phy_rev != 6 && phy_rev != 7)
3004 unsupported = 1;
3005 break;
3006 case B43legacy_PHYTYPE_G:
3007 if (phy_rev > 8)
3008 unsupported = 1;
3009 break;
3010 default:
3011 unsupported = 1;
3012 }
3013 if (unsupported) {
3014 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
3015 "(Analog %u, Type %u, Revision %u)\n",
3016 analog_type, phy_type, phy_rev);
3017 return -EOPNOTSUPP;
3018 }
3019 b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3020 analog_type, phy_type, phy_rev);
3021
3022
3023 /* Get RADIO versioning */
3024 if (dev->dev->bus->chip_id == 0x4317) {
3025 if (dev->dev->bus->chip_rev == 0)
3026 tmp = 0x3205017F;
3027 else if (dev->dev->bus->chip_rev == 1)
3028 tmp = 0x4205017F;
3029 else
3030 tmp = 0x5205017F;
3031 } else {
3032 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
3033 B43legacy_RADIOCTL_ID);
3034 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
3035 tmp <<= 16;
3036 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
3037 B43legacy_RADIOCTL_ID);
3038 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
3039 }
3040 radio_manuf = (tmp & 0x00000FFF);
3041 radio_ver = (tmp & 0x0FFFF000) >> 12;
3042 radio_rev = (tmp & 0xF0000000) >> 28;
3043 switch (phy_type) {
3044 case B43legacy_PHYTYPE_B:
3045 if ((radio_ver & 0xFFF0) != 0x2050)
3046 unsupported = 1;
3047 break;
3048 case B43legacy_PHYTYPE_G:
3049 if (radio_ver != 0x2050)
3050 unsupported = 1;
3051 break;
3052 default:
3053 B43legacy_BUG_ON(1);
3054 }
3055 if (unsupported) {
3056 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3057 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3058 radio_manuf, radio_ver, radio_rev);
3059 return -EOPNOTSUPP;
3060 }
3061 b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3062 " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3063
3064
3065 phy->radio_manuf = radio_manuf;
3066 phy->radio_ver = radio_ver;
3067 phy->radio_rev = radio_rev;
3068
3069 phy->analog = analog_type;
3070 phy->type = phy_type;
3071 phy->rev = phy_rev;
3072
3073 return 0;
3074 }
3075
3076 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3077 struct b43legacy_phy *phy)
3078 {
3079 struct b43legacy_lopair *lo;
3080 int i;
3081
3082 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3083 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3084
3085 /* Assume the radio is enabled. If it's not enabled, the state will
3086 * immediately get fixed on the first periodic work run. */
3087 dev->radio_hw_enable = true;
3088
3089 phy->savedpctlreg = 0xFFFF;
3090 phy->aci_enable = false;
3091 phy->aci_wlan_automatic = false;
3092 phy->aci_hw_rssi = false;
3093
3094 lo = phy->_lo_pairs;
3095 if (lo)
3096 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3097 B43legacy_LO_COUNT);
3098 phy->max_lb_gain = 0;
3099 phy->trsw_rx_gain = 0;
3100
3101 /* Set default attenuation values. */
3102 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3103 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3104 phy->txctl1 = b43legacy_default_txctl1(dev);
3105 phy->txpwr_offset = 0;
3106
3107 /* NRSSI */
3108 phy->nrssislope = 0;
3109 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3110 phy->nrssi[i] = -1000;
3111 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3112 phy->nrssi_lt[i] = i;
3113
3114 phy->lofcal = 0xFFFF;
3115 phy->initval = 0xFFFF;
3116
3117 phy->interfmode = B43legacy_INTERFMODE_NONE;
3118 phy->channel = 0xFF;
3119 }
3120
3121 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3122 {
3123 /* Flags */
3124 dev->dfq_valid = false;
3125
3126 /* Stats */
3127 memset(&dev->stats, 0, sizeof(dev->stats));
3128
3129 setup_struct_phy_for_init(dev, &dev->phy);
3130
3131 /* IRQ related flags */
3132 dev->irq_reason = 0;
3133 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3134 dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
3135
3136 dev->mac_suspended = 1;
3137
3138 /* Noise calculation context */
3139 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3140 }
3141
3142 static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3143 bool idle) {
3144 u16 pu_delay = 1050;
3145
3146 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3147 pu_delay = 500;
3148 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3149 pu_delay = max(pu_delay, (u16)2400);
3150
3151 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3152 B43legacy_SHM_SH_SPUWKUP, pu_delay);
3153 }
3154
3155 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3156 static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3157 {
3158 u16 pretbtt;
3159
3160 /* The time value is in microseconds. */
3161 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3162 pretbtt = 2;
3163 else
3164 pretbtt = 250;
3165 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3166 B43legacy_SHM_SH_PRETBTT, pretbtt);
3167 b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3168 }
3169
3170 /* Shutdown a wireless core */
3171 /* Locking: wl->mutex */
3172 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3173 {
3174 struct b43legacy_phy *phy = &dev->phy;
3175 u32 macctl;
3176
3177 B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3178 if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3179 return;
3180 b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3181
3182 /* Stop the microcode PSM. */
3183 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3184 macctl &= ~B43legacy_MACCTL_PSM_RUN;
3185 macctl |= B43legacy_MACCTL_PSM_JMP0;
3186 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3187
3188 b43legacy_leds_exit(dev);
3189 b43legacy_rng_exit(dev->wl);
3190 b43legacy_pio_free(dev);
3191 b43legacy_dma_free(dev);
3192 b43legacy_chip_exit(dev);
3193 b43legacy_radio_turn_off(dev, 1);
3194 b43legacy_switch_analog(dev, 0);
3195 if (phy->dyn_tssi_tbl)
3196 kfree(phy->tssi2dbm);
3197 kfree(phy->lo_control);
3198 phy->lo_control = NULL;
3199 if (dev->wl->current_beacon) {
3200 dev_kfree_skb_any(dev->wl->current_beacon);
3201 dev->wl->current_beacon = NULL;
3202 }
3203
3204 ssb_device_disable(dev->dev, 0);
3205 ssb_bus_may_powerdown(dev->dev->bus);
3206 }
3207
3208 static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3209 {
3210 struct b43legacy_phy *phy = &dev->phy;
3211 int i;
3212
3213 /* Set default attenuation values. */
3214 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3215 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3216 phy->txctl1 = b43legacy_default_txctl1(dev);
3217 phy->txctl2 = 0xFFFF;
3218 phy->txpwr_offset = 0;
3219
3220 /* NRSSI */
3221 phy->nrssislope = 0;
3222 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3223 phy->nrssi[i] = -1000;
3224 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3225 phy->nrssi_lt[i] = i;
3226
3227 phy->lofcal = 0xFFFF;
3228 phy->initval = 0xFFFF;
3229
3230 phy->aci_enable = false;
3231 phy->aci_wlan_automatic = false;
3232 phy->aci_hw_rssi = false;
3233
3234 phy->antenna_diversity = 0xFFFF;
3235 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3236 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3237
3238 /* Flags */
3239 phy->calibrated = 0;
3240
3241 if (phy->_lo_pairs)
3242 memset(phy->_lo_pairs, 0,
3243 sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3244 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3245 }
3246
3247 /* Initialize a wireless core */
3248 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3249 {
3250 struct b43legacy_wl *wl = dev->wl;
3251 struct ssb_bus *bus = dev->dev->bus;
3252 struct b43legacy_phy *phy = &dev->phy;
3253 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3254 int err;
3255 u32 hf;
3256 u32 tmp;
3257
3258 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3259
3260 err = ssb_bus_powerup(bus, 0);
3261 if (err)
3262 goto out;
3263 if (!ssb_device_is_enabled(dev->dev)) {
3264 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3265 b43legacy_wireless_core_reset(dev, tmp);
3266 }
3267
3268 if ((phy->type == B43legacy_PHYTYPE_B) ||
3269 (phy->type == B43legacy_PHYTYPE_G)) {
3270 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3271 * B43legacy_LO_COUNT,
3272 GFP_KERNEL);
3273 if (!phy->_lo_pairs)
3274 return -ENOMEM;
3275 }
3276 setup_struct_wldev_for_init(dev);
3277
3278 err = b43legacy_phy_init_tssi2dbm_table(dev);
3279 if (err)
3280 goto err_kfree_lo_control;
3281
3282 /* Enable IRQ routing to this device. */
3283 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3284
3285 prepare_phy_data_for_init(dev);
3286 b43legacy_phy_calibrate(dev);
3287 err = b43legacy_chip_init(dev);
3288 if (err)
3289 goto err_kfree_tssitbl;
3290 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3291 B43legacy_SHM_SH_WLCOREREV,
3292 dev->dev->id.revision);
3293 hf = b43legacy_hf_read(dev);
3294 if (phy->type == B43legacy_PHYTYPE_G) {
3295 hf |= B43legacy_HF_SYMW;
3296 if (phy->rev == 1)
3297 hf |= B43legacy_HF_GDCW;
3298 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
3299 hf |= B43legacy_HF_OFDMPABOOST;
3300 } else if (phy->type == B43legacy_PHYTYPE_B) {
3301 hf |= B43legacy_HF_SYMW;
3302 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3303 hf &= ~B43legacy_HF_GDCW;
3304 }
3305 b43legacy_hf_write(dev, hf);
3306
3307 b43legacy_set_retry_limits(dev,
3308 B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3309 B43legacy_DEFAULT_LONG_RETRY_LIMIT);
3310
3311 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3312 0x0044, 3);
3313 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3314 0x0046, 2);
3315
3316 /* Disable sending probe responses from firmware.
3317 * Setting the MaxTime to one usec will always trigger
3318 * a timeout, so we never send any probe resp.
3319 * A timeout of zero is infinite. */
3320 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3321 B43legacy_SHM_SH_PRMAXTIME, 1);
3322
3323 b43legacy_rate_memory_init(dev);
3324
3325 /* Minimum Contention Window */
3326 if (phy->type == B43legacy_PHYTYPE_B)
3327 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3328 0x0003, 31);
3329 else
3330 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3331 0x0003, 15);
3332 /* Maximum Contention Window */
3333 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3334 0x0004, 1023);
3335
3336 do {
3337 if (b43legacy_using_pio(dev))
3338 err = b43legacy_pio_init(dev);
3339 else {
3340 err = b43legacy_dma_init(dev);
3341 if (!err)
3342 b43legacy_qos_init(dev);
3343 }
3344 } while (err == -EAGAIN);
3345 if (err)
3346 goto err_chip_exit;
3347
3348 b43legacy_set_synth_pu_delay(dev, 1);
3349
3350 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3351 b43legacy_upload_card_macaddress(dev);
3352 b43legacy_security_init(dev);
3353 b43legacy_rng_init(wl);
3354
3355 ieee80211_wake_queues(dev->wl->hw);
3356 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3357
3358 b43legacy_leds_init(dev);
3359 out:
3360 return err;
3361
3362 err_chip_exit:
3363 b43legacy_chip_exit(dev);
3364 err_kfree_tssitbl:
3365 if (phy->dyn_tssi_tbl)
3366 kfree(phy->tssi2dbm);
3367 err_kfree_lo_control:
3368 kfree(phy->lo_control);
3369 phy->lo_control = NULL;
3370 ssb_bus_may_powerdown(bus);
3371 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3372 return err;
3373 }
3374
3375 static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3376 struct ieee80211_vif *vif)
3377 {
3378 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3379 struct b43legacy_wldev *dev;
3380 unsigned long flags;
3381 int err = -EOPNOTSUPP;
3382
3383 /* TODO: allow WDS/AP devices to coexist */
3384
3385 if (vif->type != NL80211_IFTYPE_AP &&
3386 vif->type != NL80211_IFTYPE_STATION &&
3387 vif->type != NL80211_IFTYPE_WDS &&
3388 vif->type != NL80211_IFTYPE_ADHOC)
3389 return -EOPNOTSUPP;
3390
3391 mutex_lock(&wl->mutex);
3392 if (wl->operating)
3393 goto out_mutex_unlock;
3394
3395 b43legacydbg(wl, "Adding Interface type %d\n", vif->type);
3396
3397 dev = wl->current_dev;
3398 wl->operating = true;
3399 wl->vif = vif;
3400 wl->if_type = vif->type;
3401 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
3402
3403 spin_lock_irqsave(&wl->irq_lock, flags);
3404 b43legacy_adjust_opmode(dev);
3405 b43legacy_set_pretbtt(dev);
3406 b43legacy_set_synth_pu_delay(dev, 0);
3407 b43legacy_upload_card_macaddress(dev);
3408 spin_unlock_irqrestore(&wl->irq_lock, flags);
3409
3410 err = 0;
3411 out_mutex_unlock:
3412 mutex_unlock(&wl->mutex);
3413
3414 return err;
3415 }
3416
3417 static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3418 struct ieee80211_vif *vif)
3419 {
3420 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3421 struct b43legacy_wldev *dev = wl->current_dev;
3422 unsigned long flags;
3423
3424 b43legacydbg(wl, "Removing Interface type %d\n", vif->type);
3425
3426 mutex_lock(&wl->mutex);
3427
3428 B43legacy_WARN_ON(!wl->operating);
3429 B43legacy_WARN_ON(wl->vif != vif);
3430 wl->vif = NULL;
3431
3432 wl->operating = false;
3433
3434 spin_lock_irqsave(&wl->irq_lock, flags);
3435 b43legacy_adjust_opmode(dev);
3436 memset(wl->mac_addr, 0, ETH_ALEN);
3437 b43legacy_upload_card_macaddress(dev);
3438 spin_unlock_irqrestore(&wl->irq_lock, flags);
3439
3440 mutex_unlock(&wl->mutex);
3441 }
3442
3443 static int b43legacy_op_start(struct ieee80211_hw *hw)
3444 {
3445 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3446 struct b43legacy_wldev *dev = wl->current_dev;
3447 int did_init = 0;
3448 int err = 0;
3449
3450 /* Kill all old instance specific information to make sure
3451 * the card won't use it in the short timeframe between start
3452 * and mac80211 reconfiguring it. */
3453 memset(wl->bssid, 0, ETH_ALEN);
3454 memset(wl->mac_addr, 0, ETH_ALEN);
3455 wl->filter_flags = 0;
3456 wl->beacon0_uploaded = false;
3457 wl->beacon1_uploaded = false;
3458 wl->beacon_templates_virgin = true;
3459 wl->radio_enabled = true;
3460
3461 mutex_lock(&wl->mutex);
3462
3463 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3464 err = b43legacy_wireless_core_init(dev);
3465 if (err)
3466 goto out_mutex_unlock;
3467 did_init = 1;
3468 }
3469
3470 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3471 err = b43legacy_wireless_core_start(dev);
3472 if (err) {
3473 if (did_init)
3474 b43legacy_wireless_core_exit(dev);
3475 goto out_mutex_unlock;
3476 }
3477 }
3478
3479 wiphy_rfkill_start_polling(hw->wiphy);
3480
3481 out_mutex_unlock:
3482 mutex_unlock(&wl->mutex);
3483
3484 return err;
3485 }
3486
3487 static void b43legacy_op_stop(struct ieee80211_hw *hw)
3488 {
3489 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3490 struct b43legacy_wldev *dev = wl->current_dev;
3491
3492 cancel_work_sync(&(wl->beacon_update_trigger));
3493
3494 mutex_lock(&wl->mutex);
3495 if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3496 b43legacy_wireless_core_stop(dev);
3497 b43legacy_wireless_core_exit(dev);
3498 wl->radio_enabled = false;
3499 mutex_unlock(&wl->mutex);
3500 }
3501
3502 static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
3503 struct ieee80211_sta *sta, bool set)
3504 {
3505 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3506 unsigned long flags;
3507
3508 spin_lock_irqsave(&wl->irq_lock, flags);
3509 b43legacy_update_templates(wl);
3510 spin_unlock_irqrestore(&wl->irq_lock, flags);
3511
3512 return 0;
3513 }
3514
3515 static int b43legacy_op_get_survey(struct ieee80211_hw *hw, int idx,
3516 struct survey_info *survey)
3517 {
3518 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3519 struct b43legacy_wldev *dev = wl->current_dev;
3520 struct ieee80211_conf *conf = &hw->conf;
3521
3522 if (idx != 0)
3523 return -ENOENT;
3524
3525 survey->channel = conf->channel;
3526 survey->filled = SURVEY_INFO_NOISE_DBM;
3527 survey->noise = dev->stats.link_noise;
3528
3529 return 0;
3530 }
3531
3532 static const struct ieee80211_ops b43legacy_hw_ops = {
3533 .tx = b43legacy_op_tx,
3534 .conf_tx = b43legacy_op_conf_tx,
3535 .add_interface = b43legacy_op_add_interface,
3536 .remove_interface = b43legacy_op_remove_interface,
3537 .config = b43legacy_op_dev_config,
3538 .bss_info_changed = b43legacy_op_bss_info_changed,
3539 .configure_filter = b43legacy_op_configure_filter,
3540 .get_stats = b43legacy_op_get_stats,
3541 .start = b43legacy_op_start,
3542 .stop = b43legacy_op_stop,
3543 .set_tim = b43legacy_op_beacon_set_tim,
3544 .get_survey = b43legacy_op_get_survey,
3545 .rfkill_poll = b43legacy_rfkill_poll,
3546 };
3547
3548 /* Hard-reset the chip. Do not call this directly.
3549 * Use b43legacy_controller_restart()
3550 */
3551 static void b43legacy_chip_reset(struct work_struct *work)
3552 {
3553 struct b43legacy_wldev *dev =
3554 container_of(work, struct b43legacy_wldev, restart_work);
3555 struct b43legacy_wl *wl = dev->wl;
3556 int err = 0;
3557 int prev_status;
3558
3559 mutex_lock(&wl->mutex);
3560
3561 prev_status = b43legacy_status(dev);
3562 /* Bring the device down... */
3563 if (prev_status >= B43legacy_STAT_STARTED)
3564 b43legacy_wireless_core_stop(dev);
3565 if (prev_status >= B43legacy_STAT_INITIALIZED)
3566 b43legacy_wireless_core_exit(dev);
3567
3568 /* ...and up again. */
3569 if (prev_status >= B43legacy_STAT_INITIALIZED) {
3570 err = b43legacy_wireless_core_init(dev);
3571 if (err)
3572 goto out;
3573 }
3574 if (prev_status >= B43legacy_STAT_STARTED) {
3575 err = b43legacy_wireless_core_start(dev);
3576 if (err) {
3577 b43legacy_wireless_core_exit(dev);
3578 goto out;
3579 }
3580 }
3581 out:
3582 if (err)
3583 wl->current_dev = NULL; /* Failed to init the dev. */
3584 mutex_unlock(&wl->mutex);
3585 if (err)
3586 b43legacyerr(wl, "Controller restart FAILED\n");
3587 else
3588 b43legacyinfo(wl, "Controller restarted\n");
3589 }
3590
3591 static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3592 int have_bphy,
3593 int have_gphy)
3594 {
3595 struct ieee80211_hw *hw = dev->wl->hw;
3596 struct b43legacy_phy *phy = &dev->phy;
3597
3598 phy->possible_phymodes = 0;
3599 if (have_bphy) {
3600 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3601 &b43legacy_band_2GHz_BPHY;
3602 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3603 }
3604
3605 if (have_gphy) {
3606 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3607 &b43legacy_band_2GHz_GPHY;
3608 phy->possible_phymodes |= B43legacy_PHYMODE_G;
3609 }
3610
3611 return 0;
3612 }
3613
3614 static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3615 {
3616 /* We release firmware that late to not be required to re-request
3617 * is all the time when we reinit the core. */
3618 b43legacy_release_firmware(dev);
3619 }
3620
3621 static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3622 {
3623 struct b43legacy_wl *wl = dev->wl;
3624 struct ssb_bus *bus = dev->dev->bus;
3625 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
3626 int err;
3627 int have_bphy = 0;
3628 int have_gphy = 0;
3629 u32 tmp;
3630
3631 /* Do NOT do any device initialization here.
3632 * Do it in wireless_core_init() instead.
3633 * This function is for gathering basic information about the HW, only.
3634 * Also some structs may be set up here. But most likely you want to
3635 * have that in core_init(), too.
3636 */
3637
3638 err = ssb_bus_powerup(bus, 0);
3639 if (err) {
3640 b43legacyerr(wl, "Bus powerup failed\n");
3641 goto out;
3642 }
3643 /* Get the PHY type. */
3644 if (dev->dev->id.revision >= 5) {
3645 u32 tmshigh;
3646
3647 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3648 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3649 if (!have_gphy)
3650 have_bphy = 1;
3651 } else if (dev->dev->id.revision == 4)
3652 have_gphy = 1;
3653 else
3654 have_bphy = 1;
3655
3656 dev->phy.gmode = (have_gphy || have_bphy);
3657 dev->phy.radio_on = true;
3658 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3659 b43legacy_wireless_core_reset(dev, tmp);
3660
3661 err = b43legacy_phy_versioning(dev);
3662 if (err)
3663 goto err_powerdown;
3664 /* Check if this device supports multiband. */
3665 if (!pdev ||
3666 (pdev->device != 0x4312 &&
3667 pdev->device != 0x4319 &&
3668 pdev->device != 0x4324)) {
3669 /* No multiband support. */
3670 have_bphy = 0;
3671 have_gphy = 0;
3672 switch (dev->phy.type) {
3673 case B43legacy_PHYTYPE_B:
3674 have_bphy = 1;
3675 break;
3676 case B43legacy_PHYTYPE_G:
3677 have_gphy = 1;
3678 break;
3679 default:
3680 B43legacy_BUG_ON(1);
3681 }
3682 }
3683 dev->phy.gmode = (have_gphy || have_bphy);
3684 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3685 b43legacy_wireless_core_reset(dev, tmp);
3686
3687 err = b43legacy_validate_chipaccess(dev);
3688 if (err)
3689 goto err_powerdown;
3690 err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3691 if (err)
3692 goto err_powerdown;
3693
3694 /* Now set some default "current_dev" */
3695 if (!wl->current_dev)
3696 wl->current_dev = dev;
3697 INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3698
3699 b43legacy_radio_turn_off(dev, 1);
3700 b43legacy_switch_analog(dev, 0);
3701 ssb_device_disable(dev->dev, 0);
3702 ssb_bus_may_powerdown(bus);
3703
3704 out:
3705 return err;
3706
3707 err_powerdown:
3708 ssb_bus_may_powerdown(bus);
3709 return err;
3710 }
3711
3712 static void b43legacy_one_core_detach(struct ssb_device *dev)
3713 {
3714 struct b43legacy_wldev *wldev;
3715 struct b43legacy_wl *wl;
3716
3717 /* Do not cancel ieee80211-workqueue based work here.
3718 * See comment in b43legacy_remove(). */
3719
3720 wldev = ssb_get_drvdata(dev);
3721 wl = wldev->wl;
3722 b43legacy_debugfs_remove_device(wldev);
3723 b43legacy_wireless_core_detach(wldev);
3724 list_del(&wldev->list);
3725 wl->nr_devs--;
3726 ssb_set_drvdata(dev, NULL);
3727 kfree(wldev);
3728 }
3729
3730 static int b43legacy_one_core_attach(struct ssb_device *dev,
3731 struct b43legacy_wl *wl)
3732 {
3733 struct b43legacy_wldev *wldev;
3734 int err = -ENOMEM;
3735
3736 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3737 if (!wldev)
3738 goto out;
3739
3740 wldev->dev = dev;
3741 wldev->wl = wl;
3742 b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3743 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3744 tasklet_init(&wldev->isr_tasklet,
3745 (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3746 (unsigned long)wldev);
3747 if (modparam_pio)
3748 wldev->__using_pio = true;
3749 INIT_LIST_HEAD(&wldev->list);
3750
3751 err = b43legacy_wireless_core_attach(wldev);
3752 if (err)
3753 goto err_kfree_wldev;
3754
3755 list_add(&wldev->list, &wl->devlist);
3756 wl->nr_devs++;
3757 ssb_set_drvdata(dev, wldev);
3758 b43legacy_debugfs_add_device(wldev);
3759 out:
3760 return err;
3761
3762 err_kfree_wldev:
3763 kfree(wldev);
3764 return err;
3765 }
3766
3767 static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3768 {
3769 /* boardflags workarounds */
3770 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3771 bus->boardinfo.type == 0x4E &&
3772 bus->boardinfo.rev > 0x40)
3773 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
3774 }
3775
3776 static void b43legacy_wireless_exit(struct ssb_device *dev,
3777 struct b43legacy_wl *wl)
3778 {
3779 struct ieee80211_hw *hw = wl->hw;
3780
3781 ssb_set_devtypedata(dev, NULL);
3782 ieee80211_free_hw(hw);
3783 }
3784
3785 static int b43legacy_wireless_init(struct ssb_device *dev)
3786 {
3787 struct ssb_sprom *sprom = &dev->bus->sprom;
3788 struct ieee80211_hw *hw;
3789 struct b43legacy_wl *wl;
3790 int err = -ENOMEM;
3791 int queue_num;
3792
3793 b43legacy_sprom_fixup(dev->bus);
3794
3795 hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3796 if (!hw) {
3797 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3798 goto out;
3799 }
3800
3801 /* fill hw info */
3802 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3803 IEEE80211_HW_SIGNAL_DBM;
3804 hw->wiphy->interface_modes =
3805 BIT(NL80211_IFTYPE_AP) |
3806 BIT(NL80211_IFTYPE_STATION) |
3807 BIT(NL80211_IFTYPE_WDS) |
3808 BIT(NL80211_IFTYPE_ADHOC);
3809 hw->queues = 1; /* FIXME: hardware has more queues */
3810 hw->max_rates = 2;
3811 SET_IEEE80211_DEV(hw, dev->dev);
3812 if (is_valid_ether_addr(sprom->et1mac))
3813 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3814 else
3815 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3816
3817 /* Get and initialize struct b43legacy_wl */
3818 wl = hw_to_b43legacy_wl(hw);
3819 memset(wl, 0, sizeof(*wl));
3820 wl->hw = hw;
3821 spin_lock_init(&wl->irq_lock);
3822 spin_lock_init(&wl->leds_lock);
3823 mutex_init(&wl->mutex);
3824 INIT_LIST_HEAD(&wl->devlist);
3825 INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work);
3826 INIT_WORK(&wl->tx_work, b43legacy_tx_work);
3827
3828 /* Initialize queues and flags. */
3829 for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) {
3830 skb_queue_head_init(&wl->tx_queue[queue_num]);
3831 wl->tx_queue_stopped[queue_num] = 0;
3832 }
3833
3834 ssb_set_devtypedata(dev, wl);
3835 b43legacyinfo(wl, "Broadcom %04X WLAN found (core revision %u)\n",
3836 dev->bus->chip_id, dev->id.revision);
3837 err = 0;
3838 out:
3839 return err;
3840 }
3841
3842 static int b43legacy_probe(struct ssb_device *dev,
3843 const struct ssb_device_id *id)
3844 {
3845 struct b43legacy_wl *wl;
3846 int err;
3847 int first = 0;
3848
3849 wl = ssb_get_devtypedata(dev);
3850 if (!wl) {
3851 /* Probing the first core - setup common struct b43legacy_wl */
3852 first = 1;
3853 err = b43legacy_wireless_init(dev);
3854 if (err)
3855 goto out;
3856 wl = ssb_get_devtypedata(dev);
3857 B43legacy_WARN_ON(!wl);
3858 }
3859 err = b43legacy_one_core_attach(dev, wl);
3860 if (err)
3861 goto err_wireless_exit;
3862
3863 if (first) {
3864 err = ieee80211_register_hw(wl->hw);
3865 if (err)
3866 goto err_one_core_detach;
3867 }
3868
3869 out:
3870 return err;
3871
3872 err_one_core_detach:
3873 b43legacy_one_core_detach(dev);
3874 err_wireless_exit:
3875 if (first)
3876 b43legacy_wireless_exit(dev, wl);
3877 return err;
3878 }
3879
3880 static void b43legacy_remove(struct ssb_device *dev)
3881 {
3882 struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3883 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3884
3885 /* We must cancel any work here before unregistering from ieee80211,
3886 * as the ieee80211 unreg will destroy the workqueue. */
3887 cancel_work_sync(&wldev->restart_work);
3888
3889 B43legacy_WARN_ON(!wl);
3890 if (wl->current_dev == wldev)
3891 ieee80211_unregister_hw(wl->hw);
3892
3893 b43legacy_one_core_detach(dev);
3894
3895 if (list_empty(&wl->devlist))
3896 /* Last core on the chip unregistered.
3897 * We can destroy common struct b43legacy_wl.
3898 */
3899 b43legacy_wireless_exit(dev, wl);
3900 }
3901
3902 /* Perform a hardware reset. This can be called from any context. */
3903 void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3904 const char *reason)
3905 {
3906 /* Must avoid requeueing, if we are in shutdown. */
3907 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3908 return;
3909 b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
3910 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
3911 }
3912
3913 #ifdef CONFIG_PM
3914
3915 static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3916 {
3917 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3918 struct b43legacy_wl *wl = wldev->wl;
3919
3920 b43legacydbg(wl, "Suspending...\n");
3921
3922 mutex_lock(&wl->mutex);
3923 wldev->suspend_init_status = b43legacy_status(wldev);
3924 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3925 b43legacy_wireless_core_stop(wldev);
3926 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3927 b43legacy_wireless_core_exit(wldev);
3928 mutex_unlock(&wl->mutex);
3929
3930 b43legacydbg(wl, "Device suspended.\n");
3931
3932 return 0;
3933 }
3934
3935 static int b43legacy_resume(struct ssb_device *dev)
3936 {
3937 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3938 struct b43legacy_wl *wl = wldev->wl;
3939 int err = 0;
3940
3941 b43legacydbg(wl, "Resuming...\n");
3942
3943 mutex_lock(&wl->mutex);
3944 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3945 err = b43legacy_wireless_core_init(wldev);
3946 if (err) {
3947 b43legacyerr(wl, "Resume failed at core init\n");
3948 goto out;
3949 }
3950 }
3951 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3952 err = b43legacy_wireless_core_start(wldev);
3953 if (err) {
3954 b43legacy_wireless_core_exit(wldev);
3955 b43legacyerr(wl, "Resume failed at core start\n");
3956 goto out;
3957 }
3958 }
3959
3960 b43legacydbg(wl, "Device resumed.\n");
3961 out:
3962 mutex_unlock(&wl->mutex);
3963 return err;
3964 }
3965
3966 #else /* CONFIG_PM */
3967 # define b43legacy_suspend NULL
3968 # define b43legacy_resume NULL
3969 #endif /* CONFIG_PM */
3970
3971 static struct ssb_driver b43legacy_ssb_driver = {
3972 .name = KBUILD_MODNAME,
3973 .id_table = b43legacy_ssb_tbl,
3974 .probe = b43legacy_probe,
3975 .remove = b43legacy_remove,
3976 .suspend = b43legacy_suspend,
3977 .resume = b43legacy_resume,
3978 };
3979
3980 static void b43legacy_print_driverinfo(void)
3981 {
3982 const char *feat_pci = "", *feat_leds = "",
3983 *feat_pio = "", *feat_dma = "";
3984
3985 #ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3986 feat_pci = "P";
3987 #endif
3988 #ifdef CONFIG_B43LEGACY_LEDS
3989 feat_leds = "L";
3990 #endif
3991 #ifdef CONFIG_B43LEGACY_PIO
3992 feat_pio = "I";
3993 #endif
3994 #ifdef CONFIG_B43LEGACY_DMA
3995 feat_dma = "D";
3996 #endif
3997 printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
3998 "[ Features: %s%s%s%s ]\n",
3999 feat_pci, feat_leds, feat_pio, feat_dma);
4000 }
4001
4002 static int __init b43legacy_init(void)
4003 {
4004 int err;
4005
4006 b43legacy_debugfs_init();
4007
4008 err = ssb_driver_register(&b43legacy_ssb_driver);
4009 if (err)
4010 goto err_dfs_exit;
4011
4012 b43legacy_print_driverinfo();
4013
4014 return err;
4015
4016 err_dfs_exit:
4017 b43legacy_debugfs_exit();
4018 return err;
4019 }
4020
4021 static void __exit b43legacy_exit(void)
4022 {
4023 ssb_driver_unregister(&b43legacy_ssb_driver);
4024 b43legacy_debugfs_exit();
4025 }
4026
4027 module_init(b43legacy_init)
4028 module_exit(b43legacy_exit)