spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / wireless / brcm80211 / brcmsmac / phy / phy_lcn.h
blobf4a8ab09da4314dc97bd85246b3534da475c5bcb
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _BRCM_PHY_LCN_H_
18 #define _BRCM_PHY_LCN_H_
20 #include <types.h>
22 struct brcms_phy_lcnphy {
23 int lcnphy_txrf_sp_9_override;
24 u8 lcnphy_full_cal_channel;
25 u8 lcnphy_cal_counter;
26 u16 lcnphy_cal_temper;
27 bool lcnphy_recal;
29 u8 lcnphy_rc_cap;
30 u32 lcnphy_mcs20_po;
32 u8 lcnphy_tr_isolation_mid;
33 u8 lcnphy_tr_isolation_low;
34 u8 lcnphy_tr_isolation_hi;
36 u8 lcnphy_bx_arch;
37 u8 lcnphy_rx_power_offset;
38 u8 lcnphy_rssi_vf;
39 u8 lcnphy_rssi_vc;
40 u8 lcnphy_rssi_gs;
41 u8 lcnphy_tssi_val;
42 u8 lcnphy_rssi_vf_lowtemp;
43 u8 lcnphy_rssi_vc_lowtemp;
44 u8 lcnphy_rssi_gs_lowtemp;
46 u8 lcnphy_rssi_vf_hightemp;
47 u8 lcnphy_rssi_vc_hightemp;
48 u8 lcnphy_rssi_gs_hightemp;
50 s16 lcnphy_pa0b0;
51 s16 lcnphy_pa0b1;
52 s16 lcnphy_pa0b2;
54 u16 lcnphy_rawtempsense;
55 u8 lcnphy_measPower;
56 u8 lcnphy_tempsense_slope;
57 u8 lcnphy_freqoffset_corr;
58 u8 lcnphy_tempsense_option;
59 u8 lcnphy_tempcorrx;
60 bool lcnphy_iqcal_swp_dis;
61 bool lcnphy_hw_iqcal_en;
62 uint lcnphy_bandedge_corr;
63 bool lcnphy_spurmod;
64 u16 lcnphy_tssi_tx_cnt;
65 u16 lcnphy_tssi_idx;
66 u16 lcnphy_tssi_npt;
68 u16 lcnphy_target_tx_freq;
69 s8 lcnphy_tx_power_idx_override;
70 u16 lcnphy_noise_samples;
72 u32 lcnphy_papdRxGnIdx;
73 u32 lcnphy_papd_rxGnCtrl_init;
75 u32 lcnphy_gain_idx_14_lowword;
76 u32 lcnphy_gain_idx_14_hiword;
77 u32 lcnphy_gain_idx_27_lowword;
78 u32 lcnphy_gain_idx_27_hiword;
79 s16 lcnphy_ofdmgainidxtableoffset;
80 s16 lcnphy_dsssgainidxtableoffset;
81 u32 lcnphy_tr_R_gain_val;
82 u32 lcnphy_tr_T_gain_val;
83 s8 lcnphy_input_pwr_offset_db;
84 u16 lcnphy_Med_Low_Gain_db;
85 u16 lcnphy_Very_Low_Gain_db;
86 s8 lcnphy_lastsensed_temperature;
87 s8 lcnphy_pkteng_rssi_slope;
88 u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES];
89 u8 lcnphy_volt_winner;
90 u8 lcnphy_volt_low;
91 u8 lcnphy_54_48_36_24mbps_backoff;
92 u8 lcnphy_11n_backoff;
93 u8 lcnphy_lowerofdm;
94 u8 lcnphy_cck;
95 u8 lcnphy_psat_2pt3_detected;
96 s32 lcnphy_lowest_Re_div_Im;
97 s8 lcnphy_final_papd_cal_idx;
98 u16 lcnphy_extstxctrl4;
99 u16 lcnphy_extstxctrl0;
100 u16 lcnphy_extstxctrl1;
101 s16 lcnphy_cck_dig_filt_type;
102 s16 lcnphy_ofdm_dig_filt_type;
103 struct lcnphy_cal_results lcnphy_cal_results;
105 u8 lcnphy_psat_pwr;
106 u8 lcnphy_psat_indx;
107 s32 lcnphy_min_phase;
108 u8 lcnphy_final_idx;
109 u8 lcnphy_start_idx;
110 u8 lcnphy_current_index;
111 u16 lcnphy_logen_buf_1;
112 u16 lcnphy_local_ovr_2;
113 u16 lcnphy_local_oval_6;
114 u16 lcnphy_local_oval_5;
115 u16 lcnphy_logen_mixer_1;
117 u8 lcnphy_aci_stat;
118 uint lcnphy_aci_start_time;
119 s8 lcnphy_tx_power_offset[TXP_NUM_RATES];
121 #endif /* _BRCM_PHY_LCN_H_ */