spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / wireless / mwifiex / decl.h
blobae17ce02a3d0f074d24924a39f54a8a59748f30f
1 /*
2 * Marvell Wireless LAN device driver: generic data structures and APIs
4 * Copyright (C) 2011, Marvell International Ltd.
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
20 #ifndef _MWIFIEX_DECL_H_
21 #define _MWIFIEX_DECL_H_
23 #undef pr_fmt
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/wait.h>
27 #include <linux/timer.h>
28 #include <linux/ieee80211.h>
31 #define MWIFIEX_MAX_BSS_NUM (1)
33 #define MWIFIEX_MIN_DATA_HEADER_LEN 36 /* sizeof(mwifiex_txpd)
34 * + 4 byte alignment
37 #define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED 2
38 #define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED 16
40 #define MWIFIEX_AMPDU_DEF_TXWINSIZE 32
41 #define MWIFIEX_AMPDU_DEF_RXWINSIZE 16
42 #define MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT 0xffff
44 #define MWIFIEX_RATE_INDEX_HRDSSS0 0
45 #define MWIFIEX_RATE_INDEX_HRDSSS3 3
46 #define MWIFIEX_RATE_INDEX_OFDM0 4
47 #define MWIFIEX_RATE_INDEX_OFDM7 11
48 #define MWIFIEX_RATE_INDEX_MCS0 12
50 #define MWIFIEX_RATE_BITMAP_OFDM0 16
51 #define MWIFIEX_RATE_BITMAP_OFDM7 23
52 #define MWIFIEX_RATE_BITMAP_MCS0 32
53 #define MWIFIEX_RATE_BITMAP_MCS127 159
55 #define MWIFIEX_RX_DATA_BUF_SIZE (4 * 1024)
57 #define MWIFIEX_RTS_MIN_VALUE (0)
58 #define MWIFIEX_RTS_MAX_VALUE (2347)
59 #define MWIFIEX_FRAG_MIN_VALUE (256)
60 #define MWIFIEX_FRAG_MAX_VALUE (2346)
62 #define MWIFIEX_SDIO_BLOCK_SIZE 256
64 #define MWIFIEX_BUF_FLAG_REQUEUED_PKT BIT(0)
66 enum mwifiex_bss_type {
67 MWIFIEX_BSS_TYPE_STA = 0,
68 MWIFIEX_BSS_TYPE_UAP = 1,
69 MWIFIEX_BSS_TYPE_ANY = 0xff,
72 enum mwifiex_bss_role {
73 MWIFIEX_BSS_ROLE_STA = 0,
74 MWIFIEX_BSS_ROLE_UAP = 1,
75 MWIFIEX_BSS_ROLE_ANY = 0xff,
78 #define BSS_ROLE_BIT_MASK BIT(0)
80 #define GET_BSS_ROLE(priv) ((priv)->bss_role & BSS_ROLE_BIT_MASK)
82 enum mwifiex_data_frame_type {
83 MWIFIEX_DATA_FRAME_TYPE_ETH_II = 0,
84 MWIFIEX_DATA_FRAME_TYPE_802_11,
87 struct mwifiex_fw_image {
88 u8 *helper_buf;
89 u32 helper_len;
90 u8 *fw_buf;
91 u32 fw_len;
94 struct mwifiex_802_11_ssid {
95 u32 ssid_len;
96 u8 ssid[IEEE80211_MAX_SSID_LEN];
99 struct mwifiex_wait_queue {
100 wait_queue_head_t wait;
101 int status;
104 struct mwifiex_rxinfo {
105 u8 bss_index;
106 struct sk_buff *parent;
107 u8 use_count;
110 struct mwifiex_txinfo {
111 u32 status_code;
112 u8 flags;
113 u8 bss_index;
116 enum mwifiex_wmm_ac_e {
117 WMM_AC_BK,
118 WMM_AC_BE,
119 WMM_AC_VI,
120 WMM_AC_VO
121 } __packed;
122 #endif /* !_MWIFIEX_DECL_H_ */