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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / wireless / rtlwifi / pci.c
blobb588ca83571418ec114907b2c05c195be884f00b
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include <linux/export.h>
31 #include "wifi.h"
32 #include "core.h"
33 #include "pci.h"
34 #include "base.h"
35 #include "ps.h"
36 #include "efuse.h"
37
38 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
39 PCI_VENDOR_ID_INTEL,
40 PCI_VENDOR_ID_ATI,
41 PCI_VENDOR_ID_AMD,
42 PCI_VENDOR_ID_SI
43 };
44
45 static const u8 ac_to_hwq[] = {
46 VO_QUEUE,
47 VI_QUEUE,
48 BE_QUEUE,
49 BK_QUEUE
50 };
51
52 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
53 struct sk_buff *skb)
54 {
55 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
56 __le16 fc = rtl_get_fc(skb);
57 u8 queue_index = skb_get_queue_mapping(skb);
58
59 if (unlikely(ieee80211_is_beacon(fc)))
60 return BEACON_QUEUE;
61 if (ieee80211_is_mgmt(fc))
62 return MGNT_QUEUE;
63 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
64 if (ieee80211_is_nullfunc(fc))
65 return HIGH_QUEUE;
66
67 return ac_to_hwq[queue_index];
68 }
69
70 /* Update PCI dependent default settings*/
71 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
72 {
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
75 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
76 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
77 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
78 u8 init_aspm;
79
80 ppsc->reg_rfps_level = 0;
81 ppsc->support_aspm = false;
82
83 /*Update PCI ASPM setting */
84 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
85 switch (rtlpci->const_pci_aspm) {
86 case 0:
87 /*No ASPM */
88 break;
89
90 case 1:
91 /*ASPM dynamically enabled/disable. */
92 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
93 break;
94
95 case 2:
96 /*ASPM with Clock Req dynamically enabled/disable. */
97 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
98 RT_RF_OFF_LEVL_CLK_REQ);
99 break;
100
101 case 3:
102 /*
103 * Always enable ASPM and Clock Req
104 * from initialization to halt.
105 * */
106 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
107 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
108 RT_RF_OFF_LEVL_CLK_REQ);
109 break;
110
111 case 4:
112 /*
113 * Always enable ASPM without Clock Req
114 * from initialization to halt.
115 * */
116 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
117 RT_RF_OFF_LEVL_CLK_REQ);
118 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
119 break;
120 }
121
122 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
123
124 /*Update Radio OFF setting */
125 switch (rtlpci->const_hwsw_rfoff_d3) {
126 case 1:
127 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
128 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
129 break;
130
131 case 2:
132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
135 break;
136
137 case 3:
138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
139 break;
140 }
141
142 /*Set HW definition to determine if it supports ASPM. */
143 switch (rtlpci->const_support_pciaspm) {
144 case 0:{
145 /*Not support ASPM. */
146 bool support_aspm = false;
147 ppsc->support_aspm = support_aspm;
148 break;
149 }
150 case 1:{
151 /*Support ASPM. */
152 bool support_aspm = true;
153 bool support_backdoor = true;
154 ppsc->support_aspm = support_aspm;
155
156 /*if (priv->oem_id == RT_CID_TOSHIBA &&
157 !priv->ndis_adapter.amd_l1_patch)
158 support_backdoor = false; */
159
160 ppsc->support_backdoor = support_backdoor;
161
162 break;
163 }
164 case 2:
165 /*ASPM value set by chipset. */
166 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
167 bool support_aspm = true;
168 ppsc->support_aspm = support_aspm;
169 }
170 break;
171 default:
172 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
173 ("switch case not process\n"));
174 break;
175 }
176
177 /* toshiba aspm issue, toshiba will set aspm selfly
178 * so we should not set aspm in driver */
179 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
180 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
181 init_aspm == 0x43)
182 ppsc->support_aspm = false;
183 }
184
185 static bool _rtl_pci_platform_switch_device_pci_aspm(
186 struct ieee80211_hw *hw,
187 u8 value)
188 {
189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191
192 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
193 value |= 0x40;
194
195 pci_write_config_byte(rtlpci->pdev, 0x80, value);
196
197 return false;
198 }
199
200 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
201 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
202 {
203 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
204 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
205
206 pci_write_config_byte(rtlpci->pdev, 0x81, value);
207
208 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
209 udelay(100);
210
211 return true;
212 }
213
214 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
215 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
216 {
217 struct rtl_priv *rtlpriv = rtl_priv(hw);
218 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
219 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
220 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
221 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
222 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
223 /*Retrieve original configuration settings. */
224 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
225 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
226 pcibridge_linkctrlreg;
227 u16 aspmlevel = 0;
228 u8 tmp_u1b = 0;
229
230 if (!ppsc->support_aspm)
231 return;
232
233 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
234 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
235 ("PCI(Bridge) UNKNOWN.\n"));
236
237 return;
238 }
239
240 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
241 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
242 _rtl_pci_switch_clk_req(hw, 0x0);
243 }
244
245 /*for promising device will in L0 state after an I/O. */
246 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
247
248 /*Set corresponding value. */
249 aspmlevel |= BIT(0) | BIT(1);
250 linkctrl_reg &= ~aspmlevel;
251 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
252
253 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
254 udelay(50);
255
256 /*4 Disable Pci Bridge ASPM */
257 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
258 pcibridge_linkctrlreg);
259
260 udelay(50);
261 }
262
263 /*
264 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
265 *power saving We should follow the sequence to enable
266 *RTL8192SE first then enable Pci Bridge ASPM
267 *or the system will show bluescreen.
268 */
269 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
270 {
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
272 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
273 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
274 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
275 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
276 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
277 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
278 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
279 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
280 u16 aspmlevel;
281 u8 u_pcibridge_aspmsetting;
282 u8 u_device_aspmsetting;
283
284 if (!ppsc->support_aspm)
285 return;
286
287 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
288 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
289 ("PCI(Bridge) UNKNOWN.\n"));
290 return;
291 }
292
293 /*4 Enable Pci Bridge ASPM */
294
295 u_pcibridge_aspmsetting =
296 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
297 rtlpci->const_hostpci_aspm_setting;
298
299 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
300 u_pcibridge_aspmsetting &= ~BIT(0);
301
302 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
303 u_pcibridge_aspmsetting);
304
305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
306 ("PlatformEnableASPM():PciBridge busnumber[%x], "
307 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
308 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
309 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
310 u_pcibridge_aspmsetting));
311
312 udelay(50);
313
314 /*Get ASPM level (with/without Clock Req) */
315 aspmlevel = rtlpci->const_devicepci_aspm_setting;
316 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
317
318 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
319 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
320
321 u_device_aspmsetting |= aspmlevel;
322
323 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
324
325 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
326 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
327 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
328 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
329 }
330 udelay(100);
331 }
332
333 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
334 {
335 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
336
337 bool status = false;
338 u8 offset_e0;
339 unsigned offset_e4;
340
341 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
342
343 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
344
345 if (offset_e0 == 0xA0) {
346 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
347 if (offset_e4 & BIT(23))
348 status = true;
349 }
350
351 return status;
352 }
353
354 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
355 {
356 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
357 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
358 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
359 u8 linkctrl_reg;
360 u8 num4bbytes;
361
362 num4bbytes = (capabilityoffset + 0x10) / 4;
363
364 /*Read Link Control Register */
365 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
366
367 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
368 }
369
370 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
371 struct ieee80211_hw *hw)
372 {
373 struct rtl_priv *rtlpriv = rtl_priv(hw);
374 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
375
376 u8 tmp;
377 int pos;
378 u8 linkctrl_reg;
379
380 /*Link Control Register */
381 pos = pci_pcie_cap(pdev);
382 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
383 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
384
385 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
386 ("Link Control Register =%x\n",
387 pcipriv->ndis_adapter.linkctrl_reg));
388
389 pci_read_config_byte(pdev, 0x98, &tmp);
390 tmp |= BIT(4);
391 pci_write_config_byte(pdev, 0x98, tmp);
392
393 tmp = 0x17;
394 pci_write_config_byte(pdev, 0x70f, tmp);
395 }
396
397 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
398 {
399 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
400
401 _rtl_pci_update_default_setting(hw);
402
403 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
404 /*Always enable ASPM & Clock Req. */
405 rtl_pci_enable_aspm(hw);
406 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
407 }
408
409 }
410
411 static void _rtl_pci_io_handler_init(struct device *dev,
412 struct ieee80211_hw *hw)
413 {
414 struct rtl_priv *rtlpriv = rtl_priv(hw);
415
416 rtlpriv->io.dev = dev;
417
418 rtlpriv->io.write8_async = pci_write8_async;
419 rtlpriv->io.write16_async = pci_write16_async;
420 rtlpriv->io.write32_async = pci_write32_async;
421
422 rtlpriv->io.read8_sync = pci_read8_sync;
423 rtlpriv->io.read16_sync = pci_read16_sync;
424 rtlpriv->io.read32_sync = pci_read32_sync;
425
426 }
427
428 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
429 {
430 }
431
432 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
433 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
434 {
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
437 u8 additionlen = FCS_LEN;
438 struct sk_buff *next_skb;
439
440 /* here open is 4, wep/tkip is 8, aes is 12*/
441 if (info->control.hw_key)
442 additionlen += info->control.hw_key->icv_len;
443
444 /* The most skb num is 6 */
445 tcb_desc->empkt_num = 0;
446 spin_lock_bh(&rtlpriv->locks.waitq_lock);
447 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
448 struct ieee80211_tx_info *next_info;
449
450 next_info = IEEE80211_SKB_CB(next_skb);
451 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
452 tcb_desc->empkt_len[tcb_desc->empkt_num] =
453 next_skb->len + additionlen;
454 tcb_desc->empkt_num++;
455 } else {
456 break;
457 }
458
459 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
460 next_skb))
461 break;
462
463 if (tcb_desc->empkt_num >= 5)
464 break;
465 }
466 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
467
468 return true;
469 }
470
471 /* just for early mode now */
472 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
473 {
474 struct rtl_priv *rtlpriv = rtl_priv(hw);
475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
476 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
477 struct sk_buff *skb = NULL;
478 struct ieee80211_tx_info *info = NULL;
479 int tid;
480
481 if (!rtlpriv->rtlhal.earlymode_enable)
482 return;
483
484 /* we juse use em for BE/BK/VI/VO */
485 for (tid = 7; tid >= 0; tid--) {
486 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
487 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
488 while (!mac->act_scanning &&
489 rtlpriv->psc.rfpwr_state == ERFON) {
490 struct rtl_tcb_desc tcb_desc;
491 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
492
493 spin_lock_bh(&rtlpriv->locks.waitq_lock);
494 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
495 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
496 skb = skb_dequeue(&mac->skb_waitq[tid]);
497 } else {
498 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
499 break;
500 }
501 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
502
503 /* Some macaddr can't do early mode. like
504 * multicast/broadcast/no_qos data */
505 info = IEEE80211_SKB_CB(skb);
506 if (info->flags & IEEE80211_TX_CTL_AMPDU)
507 _rtl_update_earlymode_info(hw, skb,
508 &tcb_desc, tid);
509
510 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
511 }
512 }
513 }
514
515
516 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
517 {
518 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
520
521 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
522
523 while (skb_queue_len(&ring->queue)) {
524 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
525 struct sk_buff *skb;
526 struct ieee80211_tx_info *info;
527 __le16 fc;
528 u8 tid;
529
530 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
531 HW_DESC_OWN);
532
533 /*
534 *beacon packet will only use the first
535 *descriptor defautly,and the own may not
536 *be cleared by the hardware
537 */
538 if (own)
539 return;
540 ring->idx = (ring->idx + 1) % ring->entries;
541
542 skb = __skb_dequeue(&ring->queue);
543 pci_unmap_single(rtlpci->pdev,
544 rtlpriv->cfg->ops->
545 get_desc((u8 *) entry, true,
546 HW_DESC_TXBUFF_ADDR),
547 skb->len, PCI_DMA_TODEVICE);
548
549 /* remove early mode header */
550 if (rtlpriv->rtlhal.earlymode_enable)
551 skb_pull(skb, EM_HDR_LEN);
552
553 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
554 ("new ring->idx:%d, "
555 "free: skb_queue_len:%d, free: seq:%x\n",
556 ring->idx,
557 skb_queue_len(&ring->queue),
558 *(u16 *) (skb->data + 22)));
559
560 if (prio == TXCMD_QUEUE) {
561 dev_kfree_skb(skb);
562 goto tx_status_ok;
563
564 }
565
566 /* for sw LPS, just after NULL skb send out, we can
567 * sure AP kown we are sleeped, our we should not let
568 * rf to sleep*/
569 fc = rtl_get_fc(skb);
570 if (ieee80211_is_nullfunc(fc)) {
571 if (ieee80211_has_pm(fc)) {
572 rtlpriv->mac80211.offchan_delay = true;
573 rtlpriv->psc.state_inap = true;
574 } else {
575 rtlpriv->psc.state_inap = false;
576 }
577 }
578
579 /* update tid tx pkt num */
580 tid = rtl_get_tid(skb);
581 if (tid <= 7)
582 rtlpriv->link_info.tidtx_inperiod[tid]++;
583
584 info = IEEE80211_SKB_CB(skb);
585 ieee80211_tx_info_clear_status(info);
586
587 info->flags |= IEEE80211_TX_STAT_ACK;
588 /*info->status.rates[0].count = 1; */
589
590 ieee80211_tx_status_irqsafe(hw, skb);
591
592 if ((ring->entries - skb_queue_len(&ring->queue))
593 == 2) {
594
595 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
596 ("more desc left, wake"
597 "skb_queue@%d,ring->idx = %d,"
598 "skb_queue_len = 0x%d\n",
599 prio, ring->idx,
600 skb_queue_len(&ring->queue)));
601
602 ieee80211_wake_queue(hw,
603 skb_get_queue_mapping
604 (skb));
605 }
606 tx_status_ok:
607 skb = NULL;
608 }
609
610 if (((rtlpriv->link_info.num_rx_inperiod +
611 rtlpriv->link_info.num_tx_inperiod) > 8) ||
612 (rtlpriv->link_info.num_rx_inperiod > 2)) {
613 schedule_work(&rtlpriv->works.lps_leave_work);
614 }
615 }
616
617 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
618 struct ieee80211_rx_status rx_status)
619 {
620 struct rtl_priv *rtlpriv = rtl_priv(hw);
621 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
622 __le16 fc = rtl_get_fc(skb);
623 bool unicast = false;
624 struct sk_buff *uskb = NULL;
625 u8 *pdata;
626
627
628 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
629
630 if (is_broadcast_ether_addr(hdr->addr1)) {
631 ;/*TODO*/
632 } else if (is_multicast_ether_addr(hdr->addr1)) {
633 ;/*TODO*/
634 } else {
635 unicast = true;
636 rtlpriv->stats.rxbytesunicast += skb->len;
637 }
638
639 rtl_is_special_data(hw, skb, false);
640
641 if (ieee80211_is_data(fc)) {
642 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
643
644 if (unicast)
645 rtlpriv->link_info.num_rx_inperiod++;
646 }
647
648 /* for sw lps */
649 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
650 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
651 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
652 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
653 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
654 return;
655
656 if (unlikely(!rtl_action_proc(hw, skb, false)))
657 return;
658
659 uskb = dev_alloc_skb(skb->len + 128);
660 if (!uskb)
661 return; /* exit if allocation failed */
662 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
663 pdata = (u8 *)skb_put(uskb, skb->len);
664 memcpy(pdata, skb->data, skb->len);
665
666 ieee80211_rx_irqsafe(hw, uskb);
667 }
668
669 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
670 {
671 struct rtl_priv *rtlpriv = rtl_priv(hw);
672 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
673 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
674
675 struct ieee80211_rx_status rx_status = { 0 };
676 unsigned int count = rtlpci->rxringcount;
677 u8 own;
678 u8 tmp_one;
679 u32 bufferaddress;
680
681 struct rtl_stats stats = {
682 .signal = 0,
683 .noise = -98,
684 .rate = 0,
685 };
686 int index = rtlpci->rx_ring[rx_queue_idx].idx;
687
688 /*RX NORMAL PKT */
689 while (count--) {
690 /*rx descriptor */
691 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
692 index];
693 /*rx pkt */
694 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
695 index];
696 struct sk_buff *new_skb = NULL;
697
698 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
699 false, HW_DESC_OWN);
700
701 /*wait data to be filled by hardware */
702 if (own)
703 break;
704
705 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
706 &rx_status,
707 (u8 *) pdesc, skb);
708
709 if (stats.crc || stats.hwerror)
710 goto done;
711
712 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
713 if (unlikely(!new_skb)) {
714 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
715 DBG_DMESG,
716 ("can't alloc skb for rx\n"));
717 goto done;
718 }
719
720 pci_unmap_single(rtlpci->pdev,
721 *((dma_addr_t *) skb->cb),
722 rtlpci->rxbuffersize,
723 PCI_DMA_FROMDEVICE);
724
725 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
726 HW_DESC_RXPKT_LEN));
727 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
728
729 /*
730 * NOTICE This can not be use for mac80211,
731 * this is done in mac80211 code,
732 * if you done here sec DHCP will fail
733 * skb_trim(skb, skb->len - 4);
734 */
735
736 _rtl_receive_one(hw, skb, rx_status);
737
738 if (((rtlpriv->link_info.num_rx_inperiod +
739 rtlpriv->link_info.num_tx_inperiod) > 8) ||
740 (rtlpriv->link_info.num_rx_inperiod > 2)) {
741 schedule_work(&rtlpriv->works.lps_leave_work);
742 }
743
744 dev_kfree_skb_any(skb);
745 skb = new_skb;
746
747 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
748 *((dma_addr_t *) skb->cb) =
749 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
750 rtlpci->rxbuffersize,
751 PCI_DMA_FROMDEVICE);
752
753 done:
754 bufferaddress = (*((dma_addr_t *)skb->cb));
755 tmp_one = 1;
756 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
757 HW_DESC_RXBUFF_ADDR,
758 (u8 *)&bufferaddress);
759 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
760 HW_DESC_RXPKT_LEN,
761 (u8 *)&rtlpci->rxbuffersize);
762
763 if (index == rtlpci->rxringcount - 1)
764 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
765 HW_DESC_RXERO,
766 (u8 *)&tmp_one);
767
768 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
769 (u8 *)&tmp_one);
770
771 index = (index + 1) % rtlpci->rxringcount;
772 }
773
774 rtlpci->rx_ring[rx_queue_idx].idx = index;
775 }
776
777 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
778 {
779 struct ieee80211_hw *hw = dev_id;
780 struct rtl_priv *rtlpriv = rtl_priv(hw);
781 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
782 unsigned long flags;
783 u32 inta = 0;
784 u32 intb = 0;
785 irqreturn_t ret = IRQ_HANDLED;
786
787 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
788
789 /*read ISR: 4/8bytes */
790 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
791
792 /*Shared IRQ or HW disappared */
793 if (!inta || inta == 0xffff) {
794 ret = IRQ_NONE;
795 goto done;
796 }
797
798 /*<1> beacon related */
799 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
800 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
801 ("beacon ok interrupt!\n"));
802 }
803
804 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
805 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
806 ("beacon err interrupt!\n"));
807 }
808
809 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
810 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
811 ("beacon interrupt!\n"));
812 }
813
814 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
815 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
816 ("prepare beacon for interrupt!\n"));
817 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
818 }
819
820 /*<3> Tx related */
821 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
822 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
823
824 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
825 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
826 ("Manage ok interrupt!\n"));
827 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
828 }
829
830 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
831 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
832 ("HIGH_QUEUE ok interrupt!\n"));
833 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
834 }
835
836 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
837 rtlpriv->link_info.num_tx_inperiod++;
838
839 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
840 ("BK Tx OK interrupt!\n"));
841 _rtl_pci_tx_isr(hw, BK_QUEUE);
842 }
843
844 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
845 rtlpriv->link_info.num_tx_inperiod++;
846
847 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
848 ("BE TX OK interrupt!\n"));
849 _rtl_pci_tx_isr(hw, BE_QUEUE);
850 }
851
852 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
853 rtlpriv->link_info.num_tx_inperiod++;
854
855 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
856 ("VI TX OK interrupt!\n"));
857 _rtl_pci_tx_isr(hw, VI_QUEUE);
858 }
859
860 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
861 rtlpriv->link_info.num_tx_inperiod++;
862
863 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
864 ("Vo TX OK interrupt!\n"));
865 _rtl_pci_tx_isr(hw, VO_QUEUE);
866 }
867
868 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
869 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
870 rtlpriv->link_info.num_tx_inperiod++;
871
872 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
873 ("CMD TX OK interrupt!\n"));
874 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
875 }
876 }
877
878 /*<2> Rx related */
879 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
880 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
881 _rtl_pci_rx_interrupt(hw);
882 }
883
884 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
885 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
886 ("rx descriptor unavailable!\n"));
887 _rtl_pci_rx_interrupt(hw);
888 }
889
890 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
891 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
892 _rtl_pci_rx_interrupt(hw);
893 }
894
895 if (rtlpriv->rtlhal.earlymode_enable)
896 tasklet_schedule(&rtlpriv->works.irq_tasklet);
897
898 done:
899 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
900 return ret;
901 }
902
903 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
904 {
905 _rtl_pci_tx_chk_waitq(hw);
906 }
907
908 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
909 {
910 struct rtl_priv *rtlpriv = rtl_priv(hw);
911 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
912 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
913 struct rtl8192_tx_ring *ring = NULL;
914 struct ieee80211_hdr *hdr = NULL;
915 struct ieee80211_tx_info *info = NULL;
916 struct sk_buff *pskb = NULL;
917 struct rtl_tx_desc *pdesc = NULL;
918 struct rtl_tcb_desc tcb_desc;
919 u8 temp_one = 1;
920
921 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
922 ring = &rtlpci->tx_ring[BEACON_QUEUE];
923 pskb = __skb_dequeue(&ring->queue);
924 if (pskb) {
925 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
926 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
927 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
928 pskb->len, PCI_DMA_TODEVICE);
929 kfree_skb(pskb);
930 }
931
932 /*NB: the beacon data buffer must be 32-bit aligned. */
933 pskb = ieee80211_beacon_get(hw, mac->vif);
934 if (pskb == NULL)
935 return;
936 hdr = rtl_get_hdr(pskb);
937 info = IEEE80211_SKB_CB(pskb);
938 pdesc = &ring->desc[0];
939 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
940 info, pskb, BEACON_QUEUE, &tcb_desc);
941
942 __skb_queue_tail(&ring->queue, pskb);
943
944 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
945 (u8 *)&temp_one);
946
947 return;
948 }
949
950 static void rtl_lps_leave_work_callback(struct work_struct *work)
951 {
952 struct rtl_works *rtlworks =
953 container_of(work, struct rtl_works, lps_leave_work);
954 struct ieee80211_hw *hw = rtlworks->hw;
955
956 rtl_lps_leave(hw);
957 }
958
959 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
960 {
961 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
962 u8 i;
963
964 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
965 rtlpci->txringcount[i] = RT_TXDESC_NUM;
966
967 /*
968 *we just alloc 2 desc for beacon queue,
969 *because we just need first desc in hw beacon.
970 */
971 rtlpci->txringcount[BEACON_QUEUE] = 2;
972
973 /*
974 *BE queue need more descriptor for performance
975 *consideration or, No more tx desc will happen,
976 *and may cause mac80211 mem leakage.
977 */
978 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
979
980 rtlpci->rxbuffersize = 9100; /*2048/1024; */
981 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
982 }
983
984 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
985 struct pci_dev *pdev)
986 {
987 struct rtl_priv *rtlpriv = rtl_priv(hw);
988 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
989 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
990 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
991
992 rtlpci->up_first_time = true;
993 rtlpci->being_init_adapter = false;
994
995 rtlhal->hw = hw;
996 rtlpci->pdev = pdev;
997
998 /*Tx/Rx related var */
999 _rtl_pci_init_trx_var(hw);
1000
1001 /*IBSS*/ mac->beacon_interval = 100;
1002
1003 /*AMPDU*/
1004 mac->min_space_cfg = 0;
1005 mac->max_mss_density = 0;
1006 /*set sane AMPDU defaults */
1007 mac->current_ampdu_density = 7;
1008 mac->current_ampdu_factor = 3;
1009
1010 /*QOS*/
1011 rtlpci->acm_method = eAcmWay2_SW;
1012
1013 /*task */
1014 tasklet_init(&rtlpriv->works.irq_tasklet,
1015 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1016 (unsigned long)hw);
1017 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1018 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1019 (unsigned long)hw);
1020 INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
1021 }
1022
1023 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1024 unsigned int prio, unsigned int entries)
1025 {
1026 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1027 struct rtl_priv *rtlpriv = rtl_priv(hw);
1028 struct rtl_tx_desc *ring;
1029 dma_addr_t dma;
1030 u32 nextdescaddress;
1031 int i;
1032
1033 ring = pci_alloc_consistent(rtlpci->pdev,
1034 sizeof(*ring) * entries, &dma);
1035
1036 if (!ring || (unsigned long)ring & 0xFF) {
1037 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1038 ("Cannot allocate TX ring (prio = %d)\n", prio));
1039 return -ENOMEM;
1040 }
1041
1042 memset(ring, 0, sizeof(*ring) * entries);
1043 rtlpci->tx_ring[prio].desc = ring;
1044 rtlpci->tx_ring[prio].dma = dma;
1045 rtlpci->tx_ring[prio].idx = 0;
1046 rtlpci->tx_ring[prio].entries = entries;
1047 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1048
1049 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1050 ("queue:%d, ring_addr:%p\n", prio, ring));
1051
1052 for (i = 0; i < entries; i++) {
1053 nextdescaddress = (u32) dma +
1054 ((i + 1) % entries) *
1055 sizeof(*ring);
1056
1057 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1058 true, HW_DESC_TX_NEXTDESC_ADDR,
1059 (u8 *)&nextdescaddress);
1060 }
1061
1062 return 0;
1063 }
1064
1065 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1066 {
1067 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1068 struct rtl_priv *rtlpriv = rtl_priv(hw);
1069 struct rtl_rx_desc *entry = NULL;
1070 int i, rx_queue_idx;
1071 u8 tmp_one = 1;
1072
1073 /*
1074 *rx_queue_idx 0:RX_MPDU_QUEUE
1075 *rx_queue_idx 1:RX_CMD_QUEUE
1076 */
1077 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1078 rx_queue_idx++) {
1079 rtlpci->rx_ring[rx_queue_idx].desc =
1080 pci_alloc_consistent(rtlpci->pdev,
1081 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1082 desc) * rtlpci->rxringcount,
1083 &rtlpci->rx_ring[rx_queue_idx].dma);
1084
1085 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1086 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1087 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1088 ("Cannot allocate RX ring\n"));
1089 return -ENOMEM;
1090 }
1091
1092 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1093 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1094 rtlpci->rxringcount);
1095
1096 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1097
1098 /* If amsdu_8k is disabled, set buffersize to 4096. This
1099 * change will reduce memory fragmentation.
1100 */
1101 if (rtlpci->rxbuffersize > 4096 &&
1102 rtlpriv->rtlhal.disable_amsdu_8k)
1103 rtlpci->rxbuffersize = 4096;
1104
1105 for (i = 0; i < rtlpci->rxringcount; i++) {
1106 struct sk_buff *skb =
1107 dev_alloc_skb(rtlpci->rxbuffersize);
1108 u32 bufferaddress;
1109 if (!skb)
1110 return 0;
1111 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1112
1113 /*skb->dev = dev; */
1114
1115 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1116
1117 /*
1118 *just set skb->cb to mapping addr
1119 *for pci_unmap_single use
1120 */
1121 *((dma_addr_t *) skb->cb) =
1122 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1123 rtlpci->rxbuffersize,
1124 PCI_DMA_FROMDEVICE);
1125
1126 bufferaddress = (*((dma_addr_t *)skb->cb));
1127 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1128 HW_DESC_RXBUFF_ADDR,
1129 (u8 *)&bufferaddress);
1130 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1131 HW_DESC_RXPKT_LEN,
1132 (u8 *)&rtlpci->
1133 rxbuffersize);
1134 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1135 HW_DESC_RXOWN,
1136 (u8 *)&tmp_one);
1137 }
1138
1139 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1140 HW_DESC_RXERO, (u8 *)&tmp_one);
1141 }
1142 return 0;
1143 }
1144
1145 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1146 unsigned int prio)
1147 {
1148 struct rtl_priv *rtlpriv = rtl_priv(hw);
1149 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1150 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1151
1152 while (skb_queue_len(&ring->queue)) {
1153 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1154 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1155
1156 pci_unmap_single(rtlpci->pdev,
1157 rtlpriv->cfg->
1158 ops->get_desc((u8 *) entry, true,
1159 HW_DESC_TXBUFF_ADDR),
1160 skb->len, PCI_DMA_TODEVICE);
1161 kfree_skb(skb);
1162 ring->idx = (ring->idx + 1) % ring->entries;
1163 }
1164
1165 if (ring->desc) {
1166 pci_free_consistent(rtlpci->pdev,
1167 sizeof(*ring->desc) * ring->entries,
1168 ring->desc, ring->dma);
1169 ring->desc = NULL;
1170 }
1171 }
1172
1173 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1174 {
1175 int i, rx_queue_idx;
1176
1177 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1178 /*rx_queue_idx 1:RX_CMD_QUEUE */
1179 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1180 rx_queue_idx++) {
1181 for (i = 0; i < rtlpci->rxringcount; i++) {
1182 struct sk_buff *skb =
1183 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1184 if (!skb)
1185 continue;
1186
1187 pci_unmap_single(rtlpci->pdev,
1188 *((dma_addr_t *) skb->cb),
1189 rtlpci->rxbuffersize,
1190 PCI_DMA_FROMDEVICE);
1191 kfree_skb(skb);
1192 }
1193
1194 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1195 pci_free_consistent(rtlpci->pdev,
1196 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1197 desc) * rtlpci->rxringcount,
1198 rtlpci->rx_ring[rx_queue_idx].desc,
1199 rtlpci->rx_ring[rx_queue_idx].dma);
1200 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1201 }
1202 }
1203 }
1204
1205 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1206 {
1207 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1208 int ret;
1209 int i;
1210
1211 ret = _rtl_pci_init_rx_ring(hw);
1212 if (ret)
1213 return ret;
1214
1215 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1216 ret = _rtl_pci_init_tx_ring(hw, i,
1217 rtlpci->txringcount[i]);
1218 if (ret)
1219 goto err_free_rings;
1220 }
1221
1222 return 0;
1223
1224 err_free_rings:
1225 _rtl_pci_free_rx_ring(rtlpci);
1226
1227 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1228 if (rtlpci->tx_ring[i].desc)
1229 _rtl_pci_free_tx_ring(hw, i);
1230
1231 return 1;
1232 }
1233
1234 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1235 {
1236 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1237 u32 i;
1238
1239 /*free rx rings */
1240 _rtl_pci_free_rx_ring(rtlpci);
1241
1242 /*free tx rings */
1243 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1244 _rtl_pci_free_tx_ring(hw, i);
1245
1246 return 0;
1247 }
1248
1249 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1250 {
1251 struct rtl_priv *rtlpriv = rtl_priv(hw);
1252 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1253 int i, rx_queue_idx;
1254 unsigned long flags;
1255 u8 tmp_one = 1;
1256
1257 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1258 /*rx_queue_idx 1:RX_CMD_QUEUE */
1259 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1260 rx_queue_idx++) {
1261 /*
1262 *force the rx_ring[RX_MPDU_QUEUE/
1263 *RX_CMD_QUEUE].idx to the first one
1264 */
1265 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1266 struct rtl_rx_desc *entry = NULL;
1267
1268 for (i = 0; i < rtlpci->rxringcount; i++) {
1269 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1270 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1271 false,
1272 HW_DESC_RXOWN,
1273 (u8 *)&tmp_one);
1274 }
1275 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1276 }
1277 }
1278
1279 /*
1280 *after reset, release previous pending packet,
1281 *and force the tx idx to the first one
1282 */
1283 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1284 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1285 if (rtlpci->tx_ring[i].desc) {
1286 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1287
1288 while (skb_queue_len(&ring->queue)) {
1289 struct rtl_tx_desc *entry =
1290 &ring->desc[ring->idx];
1291 struct sk_buff *skb =
1292 __skb_dequeue(&ring->queue);
1293
1294 pci_unmap_single(rtlpci->pdev,
1295 rtlpriv->cfg->ops->
1296 get_desc((u8 *)
1297 entry,
1298 true,
1299 HW_DESC_TXBUFF_ADDR),
1300 skb->len, PCI_DMA_TODEVICE);
1301 kfree_skb(skb);
1302 ring->idx = (ring->idx + 1) % ring->entries;
1303 }
1304 ring->idx = 0;
1305 }
1306 }
1307
1308 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1309
1310 return 0;
1311 }
1312
1313 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1314 struct sk_buff *skb)
1315 {
1316 struct rtl_priv *rtlpriv = rtl_priv(hw);
1317 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1318 struct ieee80211_sta *sta = info->control.sta;
1319 struct rtl_sta_info *sta_entry = NULL;
1320 u8 tid = rtl_get_tid(skb);
1321
1322 if (!sta)
1323 return false;
1324 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1325
1326 if (!rtlpriv->rtlhal.earlymode_enable)
1327 return false;
1328 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1329 return false;
1330 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1331 return false;
1332 if (tid > 7)
1333 return false;
1334
1335 /* maybe every tid should be checked */
1336 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1337 return false;
1338
1339 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1340 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1341 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1342
1343 return true;
1344 }
1345
1346 static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1347 struct rtl_tcb_desc *ptcb_desc)
1348 {
1349 struct rtl_priv *rtlpriv = rtl_priv(hw);
1350 struct rtl_sta_info *sta_entry = NULL;
1351 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1352 struct ieee80211_sta *sta = info->control.sta;
1353 struct rtl8192_tx_ring *ring;
1354 struct rtl_tx_desc *pdesc;
1355 u8 idx;
1356 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1357 unsigned long flags;
1358 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1359 __le16 fc = rtl_get_fc(skb);
1360 u8 *pda_addr = hdr->addr1;
1361 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1362 /*ssn */
1363 u8 tid = 0;
1364 u16 seq_number = 0;
1365 u8 own;
1366 u8 temp_one = 1;
1367
1368 if (ieee80211_is_auth(fc)) {
1369 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1370 rtl_ips_nic_on(hw);
1371 }
1372
1373 if (rtlpriv->psc.sw_ps_enabled) {
1374 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1375 !ieee80211_has_pm(fc))
1376 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1377 }
1378
1379 rtl_action_proc(hw, skb, true);
1380
1381 if (is_multicast_ether_addr(pda_addr))
1382 rtlpriv->stats.txbytesmulticast += skb->len;
1383 else if (is_broadcast_ether_addr(pda_addr))
1384 rtlpriv->stats.txbytesbroadcast += skb->len;
1385 else
1386 rtlpriv->stats.txbytesunicast += skb->len;
1387
1388 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1389 ring = &rtlpci->tx_ring[hw_queue];
1390 if (hw_queue != BEACON_QUEUE)
1391 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1392 ring->entries;
1393 else
1394 idx = 0;
1395
1396 pdesc = &ring->desc[idx];
1397 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1398 true, HW_DESC_OWN);
1399
1400 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1401 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1402 ("No more TX desc@%d, ring->idx = %d,"
1403 "idx = %d, skb_queue_len = 0x%d\n",
1404 hw_queue, ring->idx, idx,
1405 skb_queue_len(&ring->queue)));
1406
1407 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1408 return skb->len;
1409 }
1410
1411 if (ieee80211_is_data_qos(fc)) {
1412 tid = rtl_get_tid(skb);
1413 if (sta) {
1414 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1415 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1416 IEEE80211_SCTL_SEQ) >> 4;
1417 seq_number += 1;
1418
1419 if (!ieee80211_has_morefrags(hdr->frame_control))
1420 sta_entry->tids[tid].seq_number = seq_number;
1421 }
1422 }
1423
1424 if (ieee80211_is_data(fc))
1425 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1426
1427 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1428 info, skb, hw_queue, ptcb_desc);
1429
1430 __skb_queue_tail(&ring->queue, skb);
1431
1432 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1433 HW_DESC_OWN, (u8 *)&temp_one);
1434
1435
1436 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1437 hw_queue != BEACON_QUEUE) {
1438
1439 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1440 ("less desc left, stop skb_queue@%d, "
1441 "ring->idx = %d,"
1442 "idx = %d, skb_queue_len = 0x%d\n",
1443 hw_queue, ring->idx, idx,
1444 skb_queue_len(&ring->queue)));
1445
1446 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1447 }
1448
1449 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1450
1451 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1452
1453 return 0;
1454 }
1455
1456 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1457 {
1458 struct rtl_priv *rtlpriv = rtl_priv(hw);
1459 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1460 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1461 u16 i = 0;
1462 int queue_id;
1463 struct rtl8192_tx_ring *ring;
1464
1465 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1466 u32 queue_len;
1467 ring = &pcipriv->dev.tx_ring[queue_id];
1468 queue_len = skb_queue_len(&ring->queue);
1469 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1470 queue_id == TXCMD_QUEUE) {
1471 queue_id--;
1472 continue;
1473 } else {
1474 msleep(20);
1475 i++;
1476 }
1477
1478 /* we just wait 1s for all queues */
1479 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1480 is_hal_stop(rtlhal) || i >= 200)
1481 return;
1482 }
1483 }
1484
1485 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1486 {
1487 struct rtl_priv *rtlpriv = rtl_priv(hw);
1488 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1489
1490 _rtl_pci_deinit_trx_ring(hw);
1491
1492 synchronize_irq(rtlpci->pdev->irq);
1493 tasklet_kill(&rtlpriv->works.irq_tasklet);
1494 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1495
1496 flush_workqueue(rtlpriv->works.rtl_wq);
1497 destroy_workqueue(rtlpriv->works.rtl_wq);
1498
1499 }
1500
1501 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1502 {
1503 struct rtl_priv *rtlpriv = rtl_priv(hw);
1504 int err;
1505
1506 _rtl_pci_init_struct(hw, pdev);
1507
1508 err = _rtl_pci_init_trx_ring(hw);
1509 if (err) {
1510 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1511 ("tx ring initialization failed"));
1512 return err;
1513 }
1514
1515 return 0;
1516 }
1517
1518 static int rtl_pci_start(struct ieee80211_hw *hw)
1519 {
1520 struct rtl_priv *rtlpriv = rtl_priv(hw);
1521 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1522 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1523 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1524
1525 int err;
1526
1527 rtl_pci_reset_trx_ring(hw);
1528
1529 rtlpci->driver_is_goingto_unload = false;
1530 err = rtlpriv->cfg->ops->hw_init(hw);
1531 if (err) {
1532 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1533 ("Failed to config hardware!\n"));
1534 return err;
1535 }
1536
1537 rtlpriv->cfg->ops->enable_interrupt(hw);
1538 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1539
1540 rtl_init_rx_config(hw);
1541
1542 /*should be after adapter start and interrupt enable. */
1543 set_hal_start(rtlhal);
1544
1545 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1546
1547 rtlpci->up_first_time = false;
1548
1549 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1550 return 0;
1551 }
1552
1553 static void rtl_pci_stop(struct ieee80211_hw *hw)
1554 {
1555 struct rtl_priv *rtlpriv = rtl_priv(hw);
1556 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1557 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1558 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1559 unsigned long flags;
1560 u8 RFInProgressTimeOut = 0;
1561
1562 /*
1563 *should be before disable interrupt&adapter
1564 *and will do it immediately.
1565 */
1566 set_hal_stop(rtlhal);
1567
1568 rtlpriv->cfg->ops->disable_interrupt(hw);
1569 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1570
1571 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1572 while (ppsc->rfchange_inprogress) {
1573 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1574 if (RFInProgressTimeOut > 100) {
1575 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1576 break;
1577 }
1578 mdelay(1);
1579 RFInProgressTimeOut++;
1580 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1581 }
1582 ppsc->rfchange_inprogress = true;
1583 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1584
1585 rtlpci->driver_is_goingto_unload = true;
1586 rtlpriv->cfg->ops->hw_disable(hw);
1587 /* some things are not needed if firmware not available */
1588 if (!rtlpriv->max_fw_size)
1589 return;
1590 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1591
1592 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1593 ppsc->rfchange_inprogress = false;
1594 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1595
1596 rtl_pci_enable_aspm(hw);
1597 }
1598
1599 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1600 struct ieee80211_hw *hw)
1601 {
1602 struct rtl_priv *rtlpriv = rtl_priv(hw);
1603 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1604 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1605 struct pci_dev *bridge_pdev = pdev->bus->self;
1606 u16 venderid;
1607 u16 deviceid;
1608 u8 revisionid;
1609 u16 irqline;
1610 u8 tmp;
1611
1612 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1613 venderid = pdev->vendor;
1614 deviceid = pdev->device;
1615 pci_read_config_byte(pdev, 0x8, &revisionid);
1616 pci_read_config_word(pdev, 0x3C, &irqline);
1617
1618 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1619 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1620 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1621 * the correct driver is r8192e_pci, thus this routine should
1622 * return false.
1623 */
1624 if (deviceid == RTL_PCI_8192SE_DID &&
1625 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1626 return false;
1627
1628 if (deviceid == RTL_PCI_8192_DID ||
1629 deviceid == RTL_PCI_0044_DID ||
1630 deviceid == RTL_PCI_0047_DID ||
1631 deviceid == RTL_PCI_8192SE_DID ||
1632 deviceid == RTL_PCI_8174_DID ||
1633 deviceid == RTL_PCI_8173_DID ||
1634 deviceid == RTL_PCI_8172_DID ||
1635 deviceid == RTL_PCI_8171_DID) {
1636 switch (revisionid) {
1637 case RTL_PCI_REVISION_ID_8192PCIE:
1638 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1639 ("8192 PCI-E is found - "
1640 "vid/did=%x/%x\n", venderid, deviceid));
1641 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1642 break;
1643 case RTL_PCI_REVISION_ID_8192SE:
1644 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1645 ("8192SE is found - "
1646 "vid/did=%x/%x\n", venderid, deviceid));
1647 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1648 break;
1649 default:
1650 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1651 ("Err: Unknown device - "
1652 "vid/did=%x/%x\n", venderid, deviceid));
1653 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1654 break;
1655
1656 }
1657 } else if (deviceid == RTL_PCI_8192CET_DID ||
1658 deviceid == RTL_PCI_8192CE_DID ||
1659 deviceid == RTL_PCI_8191CE_DID ||
1660 deviceid == RTL_PCI_8188CE_DID) {
1661 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1662 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1663 ("8192C PCI-E is found - "
1664 "vid/did=%x/%x\n", venderid, deviceid));
1665 } else if (deviceid == RTL_PCI_8192DE_DID ||
1666 deviceid == RTL_PCI_8192DE_DID2) {
1667 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1668 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1669 ("8192D PCI-E is found - "
1670 "vid/did=%x/%x\n", venderid, deviceid));
1671 } else {
1672 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1673 ("Err: Unknown device -"
1674 " vid/did=%x/%x\n", venderid, deviceid));
1675
1676 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1677 }
1678
1679 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1680 if (revisionid == 0 || revisionid == 1) {
1681 if (revisionid == 0) {
1682 RT_TRACE(rtlpriv, COMP_INIT,
1683 DBG_LOUD, ("Find 92DE MAC0.\n"));
1684 rtlhal->interfaceindex = 0;
1685 } else if (revisionid == 1) {
1686 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1687 ("Find 92DE MAC1.\n"));
1688 rtlhal->interfaceindex = 1;
1689 }
1690 } else {
1691 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1692 ("Unknown device - "
1693 "VendorID/DeviceID=%x/%x, Revision=%x\n",
1694 venderid, deviceid, revisionid));
1695 rtlhal->interfaceindex = 0;
1696 }
1697 }
1698 /*find bus info */
1699 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1700 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1701 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1702
1703 if (bridge_pdev) {
1704 /*find bridge info if available */
1705 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1706 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1707 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1708 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1709 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1710 ("Pci Bridge Vendor is found index:"
1711 " %d\n", tmp));
1712 break;
1713 }
1714 }
1715 }
1716
1717 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1718 PCI_BRIDGE_VENDOR_UNKNOWN) {
1719 pcipriv->ndis_adapter.pcibridge_busnum =
1720 bridge_pdev->bus->number;
1721 pcipriv->ndis_adapter.pcibridge_devnum =
1722 PCI_SLOT(bridge_pdev->devfn);
1723 pcipriv->ndis_adapter.pcibridge_funcnum =
1724 PCI_FUNC(bridge_pdev->devfn);
1725 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1726 pci_pcie_cap(bridge_pdev);
1727 pcipriv->ndis_adapter.num4bytes =
1728 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1729
1730 rtl_pci_get_linkcontrol_field(hw);
1731
1732 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1733 PCI_BRIDGE_VENDOR_AMD) {
1734 pcipriv->ndis_adapter.amd_l1_patch =
1735 rtl_pci_get_amd_l1_patch(hw);
1736 }
1737 }
1738
1739 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1740 ("pcidev busnumber:devnumber:funcnumber:"
1741 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1742 pcipriv->ndis_adapter.busnumber,
1743 pcipriv->ndis_adapter.devnumber,
1744 pcipriv->ndis_adapter.funcnumber,
1745 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1746
1747 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1748 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1749 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1750 pcipriv->ndis_adapter.pcibridge_busnum,
1751 pcipriv->ndis_adapter.pcibridge_devnum,
1752 pcipriv->ndis_adapter.pcibridge_funcnum,
1753 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1754 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1755 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1756 pcipriv->ndis_adapter.amd_l1_patch));
1757
1758 rtl_pci_parse_configuration(pdev, hw);
1759
1760 return true;
1761 }
1762
1763 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1764 const struct pci_device_id *id)
1765 {
1766 struct ieee80211_hw *hw = NULL;
1767
1768 struct rtl_priv *rtlpriv = NULL;
1769 struct rtl_pci_priv *pcipriv = NULL;
1770 struct rtl_pci *rtlpci;
1771 unsigned long pmem_start, pmem_len, pmem_flags;
1772 int err;
1773
1774 err = pci_enable_device(pdev);
1775 if (err) {
1776 RT_ASSERT(false,
1777 ("%s : Cannot enable new PCI device\n",
1778 pci_name(pdev)));
1779 return err;
1780 }
1781
1782 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1783 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1784 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1785 "for consistent allocations\n"));
1786 pci_disable_device(pdev);
1787 return -ENOMEM;
1788 }
1789 }
1790
1791 pci_set_master(pdev);
1792
1793 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1794 sizeof(struct rtl_priv), &rtl_ops);
1795 if (!hw) {
1796 RT_ASSERT(false,
1797 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1798 err = -ENOMEM;
1799 goto fail1;
1800 }
1801
1802 SET_IEEE80211_DEV(hw, &pdev->dev);
1803 pci_set_drvdata(pdev, hw);
1804
1805 rtlpriv = hw->priv;
1806 pcipriv = (void *)rtlpriv->priv;
1807 pcipriv->dev.pdev = pdev;
1808 init_completion(&rtlpriv->firmware_loading_complete);
1809
1810 /* init cfg & intf_ops */
1811 rtlpriv->rtlhal.interface = INTF_PCI;
1812 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1813 rtlpriv->intf_ops = &rtl_pci_ops;
1814
1815 /*
1816 *init dbgp flags before all
1817 *other functions, because we will
1818 *use it in other funtions like
1819 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1820 *you can not use these macro
1821 *before this
1822 */
1823 rtl_dbgp_flag_init(hw);
1824
1825 /* MEM map */
1826 err = pci_request_regions(pdev, KBUILD_MODNAME);
1827 if (err) {
1828 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1829 goto fail2;
1830 }
1831
1832 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1833 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1834 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1835
1836 /*shared mem start */
1837 rtlpriv->io.pci_mem_start =
1838 (unsigned long)pci_iomap(pdev,
1839 rtlpriv->cfg->bar_id, pmem_len);
1840 if (rtlpriv->io.pci_mem_start == 0) {
1841 RT_ASSERT(false, ("Can't map PCI mem\n"));
1842 goto fail2;
1843 }
1844
1845 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1846 ("mem mapped space: start: 0x%08lx len:%08lx "
1847 "flags:%08lx, after map:0x%08lx\n",
1848 pmem_start, pmem_len, pmem_flags,
1849 rtlpriv->io.pci_mem_start));
1850
1851 /* Disable Clk Request */
1852 pci_write_config_byte(pdev, 0x81, 0);
1853 /* leave D3 mode */
1854 pci_write_config_byte(pdev, 0x44, 0);
1855 pci_write_config_byte(pdev, 0x04, 0x06);
1856 pci_write_config_byte(pdev, 0x04, 0x07);
1857
1858 /* find adapter */
1859 if (!_rtl_pci_find_adapter(pdev, hw))
1860 goto fail3;
1861
1862 /* Init IO handler */
1863 _rtl_pci_io_handler_init(&pdev->dev, hw);
1864
1865 /*like read eeprom and so on */
1866 rtlpriv->cfg->ops->read_eeprom_info(hw);
1867
1868 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1869 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1870 ("Can't init_sw_vars.\n"));
1871 goto fail3;
1872 }
1873
1874 rtlpriv->cfg->ops->init_sw_leds(hw);
1875
1876 /*aspm */
1877 rtl_pci_init_aspm(hw);
1878
1879 /* Init mac80211 sw */
1880 err = rtl_init_core(hw);
1881 if (err) {
1882 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1883 ("Can't allocate sw for mac80211.\n"));
1884 goto fail3;
1885 }
1886
1887 /* Init PCI sw */
1888 err = rtl_pci_init(hw, pdev);
1889 if (err) {
1890 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1891 ("Failed to init PCI.\n"));
1892 goto fail3;
1893 }
1894
1895 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1896 if (err) {
1897 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1898 ("failed to create sysfs device attributes\n"));
1899 goto fail3;
1900 }
1901
1902 rtlpci = rtl_pcidev(pcipriv);
1903 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1904 IRQF_SHARED, KBUILD_MODNAME, hw);
1905 if (err) {
1906 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1907 ("%s: failed to register IRQ handler\n",
1908 wiphy_name(hw->wiphy)));
1909 goto fail3;
1910 }
1911 rtlpci->irq_alloc = 1;
1912
1913 return 0;
1914
1915 fail3:
1916 pci_set_drvdata(pdev, NULL);
1917 rtl_deinit_core(hw);
1918 _rtl_pci_io_handler_release(hw);
1919
1920 if (rtlpriv->io.pci_mem_start != 0)
1921 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1922
1923 fail2:
1924 pci_release_regions(pdev);
1925 complete(&rtlpriv->firmware_loading_complete);
1926
1927 fail1:
1928
1929 pci_disable_device(pdev);
1930
1931 return -ENODEV;
1932
1933 }
1934 EXPORT_SYMBOL(rtl_pci_probe);
1935
1936 void rtl_pci_disconnect(struct pci_dev *pdev)
1937 {
1938 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1939 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1940 struct rtl_priv *rtlpriv = rtl_priv(hw);
1941 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1942 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1943
1944 /* just in case driver is removed before firmware callback */
1945 wait_for_completion(&rtlpriv->firmware_loading_complete);
1946 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1947
1948 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1949
1950 /*ieee80211_unregister_hw will call ops_stop */
1951 if (rtlmac->mac80211_registered == 1) {
1952 ieee80211_unregister_hw(hw);
1953 rtlmac->mac80211_registered = 0;
1954 } else {
1955 rtl_deinit_deferred_work(hw);
1956 rtlpriv->intf_ops->adapter_stop(hw);
1957 }
1958 rtlpriv->cfg->ops->disable_interrupt(hw);
1959
1960 /*deinit rfkill */
1961 rtl_deinit_rfkill(hw);
1962
1963 rtl_pci_deinit(hw);
1964 rtl_deinit_core(hw);
1965 _rtl_pci_io_handler_release(hw);
1966 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1967
1968 if (rtlpci->irq_alloc) {
1969 free_irq(rtlpci->pdev->irq, hw);
1970 rtlpci->irq_alloc = 0;
1971 }
1972
1973 if (rtlpriv->io.pci_mem_start != 0) {
1974 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1975 pci_release_regions(pdev);
1976 }
1977
1978 pci_disable_device(pdev);
1979
1980 rtl_pci_disable_aspm(hw);
1981
1982 pci_set_drvdata(pdev, NULL);
1983
1984 ieee80211_free_hw(hw);
1985 }
1986 EXPORT_SYMBOL(rtl_pci_disconnect);
1987
1988 /***************************************
1989 kernel pci power state define:
1990 PCI_D0 ((pci_power_t __force) 0)
1991 PCI_D1 ((pci_power_t __force) 1)
1992 PCI_D2 ((pci_power_t __force) 2)
1993 PCI_D3hot ((pci_power_t __force) 3)
1994 PCI_D3cold ((pci_power_t __force) 4)
1995 PCI_UNKNOWN ((pci_power_t __force) 5)
1996
1997 This function is called when system
1998 goes into suspend state mac80211 will
1999 call rtl_mac_stop() from the mac80211
2000 suspend function first, So there is
2001 no need to call hw_disable here.
2002 ****************************************/
2003 int rtl_pci_suspend(struct device *dev)
2004 {
2005 struct pci_dev *pdev = to_pci_dev(dev);
2006 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2007 struct rtl_priv *rtlpriv = rtl_priv(hw);
2008
2009 rtlpriv->cfg->ops->hw_suspend(hw);
2010 rtl_deinit_rfkill(hw);
2011
2012 return 0;
2013 }
2014 EXPORT_SYMBOL(rtl_pci_suspend);
2015
2016 int rtl_pci_resume(struct device *dev)
2017 {
2018 struct pci_dev *pdev = to_pci_dev(dev);
2019 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2020 struct rtl_priv *rtlpriv = rtl_priv(hw);
2021
2022 rtlpriv->cfg->ops->hw_resume(hw);
2023 rtl_init_rfkill(hw);
2024 return 0;
2025 }
2026 EXPORT_SYMBOL(rtl_pci_resume);
2027
2028 struct rtl_intf_ops rtl_pci_ops = {
2029 .read_efuse_byte = read_efuse_byte,
2030 .adapter_start = rtl_pci_start,
2031 .adapter_stop = rtl_pci_stop,
2032 .adapter_tx = rtl_pci_tx,
2033 .flush = rtl_pci_flush,
2034 .reset_trx_ring = rtl_pci_reset_trx_ring,
2035 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2036
2037 .disable_aspm = rtl_pci_disable_aspm,
2038 .enable_aspm = rtl_pci_enable_aspm,
2039 };