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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / wireless / wl1251 / reg.h
bloba5809019c5c19a5ced3d1f4d0b674b1e3bee6779
1 /*
2 * This file is part of wl12xx
3 *
4 * Copyright (c) 1998-2007 Texas Instruments Incorporated
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23 #ifndef __REG_H__
24 #define __REG_H__
25
26 #include <linux/bitops.h>
27
28 #define REGISTERS_BASE 0x00300000
29 #define DRPW_BASE 0x00310000
30
31 #define REGISTERS_DOWN_SIZE 0x00008800
32 #define REGISTERS_WORK_SIZE 0x0000b000
33
34 #define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
35
36 /* ELP register commands */
37 #define ELPCTRL_WAKE_UP 0x1
38 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
39 #define ELPCTRL_SLEEP 0x0
40 /* ELP WLAN_READY bit */
41 #define ELPCTRL_WLAN_READY 0x2
42
43 /* Device Configuration registers*/
44 #define SOR_CFG (REGISTERS_BASE + 0x0800)
45 #define ECPU_CTRL (REGISTERS_BASE + 0x0804)
46 #define HI_CFG (REGISTERS_BASE + 0x0808)
47
48 /* EEPROM registers */
49 #define EE_START (REGISTERS_BASE + 0x080C)
50 #define EE_CTL (REGISTERS_BASE + 0x2000)
51 #define EE_DATA (REGISTERS_BASE + 0x2004)
52 #define EE_ADDR (REGISTERS_BASE + 0x2008)
53
54 #define EE_CTL_READ 2
55
56 #define CHIP_ID_B (REGISTERS_BASE + 0x5674)
57
58 #define CHIP_ID_1251_PG10 (0x7010101)
59 #define CHIP_ID_1251_PG11 (0x7020101)
60 #define CHIP_ID_1251_PG12 (0x7030101)
61
62 #define ENABLE (REGISTERS_BASE + 0x5450)
63
64 /* Power Management registers */
65 #define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
66 #define ELP_CMD (REGISTERS_BASE + 0x5808)
67 #define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
68 #define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
69 #define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
70
71 #define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
72
73 /* Scratch Pad registers*/
74 #define SCR_PAD0 (REGISTERS_BASE + 0x5608)
75 #define SCR_PAD1 (REGISTERS_BASE + 0x560C)
76 #define SCR_PAD2 (REGISTERS_BASE + 0x5610)
77 #define SCR_PAD3 (REGISTERS_BASE + 0x5614)
78 #define SCR_PAD4 (REGISTERS_BASE + 0x5618)
79 #define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
80 #define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
81 #define SCR_PAD5 (REGISTERS_BASE + 0x5624)
82 #define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
83 #define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
84 #define SCR_PAD6 (REGISTERS_BASE + 0x5630)
85 #define SCR_PAD7 (REGISTERS_BASE + 0x5634)
86 #define SCR_PAD8 (REGISTERS_BASE + 0x5638)
87 #define SCR_PAD9 (REGISTERS_BASE + 0x563C)
88
89 /* Spare registers*/
90 #define SPARE_A1 (REGISTERS_BASE + 0x0994)
91 #define SPARE_A2 (REGISTERS_BASE + 0x0998)
92 #define SPARE_A3 (REGISTERS_BASE + 0x099C)
93 #define SPARE_A4 (REGISTERS_BASE + 0x09A0)
94 #define SPARE_A5 (REGISTERS_BASE + 0x09A4)
95 #define SPARE_A6 (REGISTERS_BASE + 0x09A8)
96 #define SPARE_A7 (REGISTERS_BASE + 0x09AC)
97 #define SPARE_A8 (REGISTERS_BASE + 0x09B0)
98 #define SPARE_B1 (REGISTERS_BASE + 0x5420)
99 #define SPARE_B2 (REGISTERS_BASE + 0x5424)
100 #define SPARE_B3 (REGISTERS_BASE + 0x5428)
101 #define SPARE_B4 (REGISTERS_BASE + 0x542C)
102 #define SPARE_B5 (REGISTERS_BASE + 0x5430)
103 #define SPARE_B6 (REGISTERS_BASE + 0x5434)
104 #define SPARE_B7 (REGISTERS_BASE + 0x5438)
105 #define SPARE_B8 (REGISTERS_BASE + 0x543C)
106
107 enum wl12xx_acx_int_reg {
108 ACX_REG_INTERRUPT_TRIG,
109 ACX_REG_INTERRUPT_TRIG_H,
110
111 /*=============================================
112 Host Interrupt Mask Register - 32bit (RW)
113 ------------------------------------------
114 Setting a bit in this register masks the
115 corresponding interrupt to the host.
116 0 - RX0 - Rx first dubble buffer Data Interrupt
117 1 - TXD - Tx Data Interrupt
118 2 - TXXFR - Tx Transfer Interrupt
119 3 - RX1 - Rx second dubble buffer Data Interrupt
120 4 - RXXFR - Rx Transfer Interrupt
121 5 - EVENT_A - Event Mailbox interrupt
122 6 - EVENT_B - Event Mailbox interrupt
123 7 - WNONHST - Wake On Host Interrupt
124 8 - TRACE_A - Debug Trace interrupt
125 9 - TRACE_B - Debug Trace interrupt
126 10 - CDCMP - Command Complete Interrupt
127 11 -
128 12 -
129 13 -
130 14 - ICOMP - Initialization Complete Interrupt
131 16 - SG SE - Soft Gemini - Sense enable interrupt
132 17 - SG SD - Soft Gemini - Sense disable interrupt
133 18 - -
134 19 - -
135 20 - -
136 21- -
137 Default: 0x0001
138 *==============================================*/
139 ACX_REG_INTERRUPT_MASK,
140
141 /*=============================================
142 Host Interrupt Mask Set 16bit, (Write only)
143 ------------------------------------------
144 Setting a bit in this register sets
145 the corresponding bin in ACX_HINT_MASK register
146 without effecting the mask
147 state of other bits (0 = no effect).
148 ==============================================*/
149 ACX_REG_HINT_MASK_SET,
150
151 /*=============================================
152 Host Interrupt Mask Clear 16bit,(Write only)
153 ------------------------------------------
154 Setting a bit in this register clears
155 the corresponding bin in ACX_HINT_MASK register
156 without effecting the mask
157 state of other bits (0 = no effect).
158 =============================================*/
159 ACX_REG_HINT_MASK_CLR,
160
161 /*=============================================
162 Host Interrupt Status Nondestructive Read
163 16bit,(Read only)
164 ------------------------------------------
165 The host can read this register to determine
166 which interrupts are active.
167 Reading this register doesn't
168 effect its content.
169 =============================================*/
170 ACX_REG_INTERRUPT_NO_CLEAR,
171
172 /*=============================================
173 Host Interrupt Status Clear on Read Register
174 16bit,(Read only)
175 ------------------------------------------
176 The host can read this register to determine
177 which interrupts are active.
178 Reading this register clears it,
179 thus making all interrupts inactive.
180 ==============================================*/
181 ACX_REG_INTERRUPT_CLEAR,
182
183 /*=============================================
184 Host Interrupt Acknowledge Register
185 16bit,(Write only)
186 ------------------------------------------
187 The host can set individual bits in this
188 register to clear (acknowledge) the corresp.
189 interrupt status bits in the HINT_STS_CLR and
190 HINT_STS_ND registers, thus making the
191 assotiated interrupt inactive. (0-no effect)
192 ==============================================*/
193 ACX_REG_INTERRUPT_ACK,
194
195 /*===============================================
196 Host Software Reset - 32bit RW
197 ------------------------------------------
198 [31:1] Reserved
199 0 SOFT_RESET Soft Reset - When this bit is set,
200 it holds the Wlan hardware in a soft reset state.
201 This reset disables all MAC and baseband processor
202 clocks except the CardBus/PCI interface clock.
203 It also initializes all MAC state machines except
204 the host interface. It does not reload the
205 contents of the EEPROM. When this bit is cleared
206 (not self-clearing), the Wlan hardware
207 exits the software reset state.
208 ===============================================*/
209 ACX_REG_SLV_SOFT_RESET,
210
211 /*===============================================
212 EEPROM Burst Read Start - 32bit RW
213 ------------------------------------------
214 [31:1] Reserved
215 0 ACX_EE_START - EEPROM Burst Read Start 0
216 Setting this bit starts a burst read from
217 the external EEPROM.
218 If this bit is set (after reset) before an EEPROM read/write,
219 the burst read starts at EEPROM address 0.
220 Otherwise, it starts at the address
221 following the address of the previous access.
222 TheWlan hardware hardware clears this bit automatically.
223
224 Default: 0x00000000
225 *================================================*/
226 ACX_REG_EE_START,
227
228 /* Embedded ARM CPU Control */
229
230 /*===============================================
231 Halt eCPU - 32bit RW
232 ------------------------------------------
233 0 HALT_ECPU Halt Embedded CPU - This bit is the
234 compliment of bit 1 (MDATA2) in the SOR_CFG register.
235 During a hardware reset, this bit holds
236 the inverse of MDATA2.
237 When downloading firmware from the host,
238 set this bit (pull down MDATA2).
239 The host clears this bit after downloading the firmware into
240 zero-wait-state SSRAM.
241 When loading firmware from Flash, clear this bit (pull up MDATA2)
242 so that the eCPU can run the bootloader code in Flash
243 HALT_ECPU eCPU State
244 --------------------
245 1 halt eCPU
246 0 enable eCPU
247 ===============================================*/
248 ACX_REG_ECPU_CONTROL,
249
250 ACX_REG_TABLE_LEN
251 };
252
253 #define ACX_SLV_SOFT_RESET_BIT BIT(0)
254 #define ACX_REG_EEPROM_START_BIT BIT(0)
255
256 /* Command/Information Mailbox Pointers */
257
258 /*===============================================
259 Command Mailbox Pointer - 32bit RW
260 ------------------------------------------
261 This register holds the start address of
262 the command mailbox located in the Wlan hardware memory.
263 The host must read this pointer after a reset to
264 find the location of the command mailbox.
265 The Wlan hardware initializes the command mailbox
266 pointer with the default address of the command mailbox.
267 The command mailbox pointer is not valid until after
268 the host receives the Init Complete interrupt from
269 the Wlan hardware.
270 ===============================================*/
271 #define REG_COMMAND_MAILBOX_PTR (SCR_PAD0)
272
273 /*===============================================
274 Information Mailbox Pointer - 32bit RW
275 ------------------------------------------
276 This register holds the start address of
277 the information mailbox located in the Wlan hardware memory.
278 The host must read this pointer after a reset to find
279 the location of the information mailbox.
280 The Wlan hardware initializes the information mailbox pointer
281 with the default address of the information mailbox.
282 The information mailbox pointer is not valid
283 until after the host receives the Init Complete interrupt from
284 the Wlan hardware.
285 ===============================================*/
286 #define REG_EVENT_MAILBOX_PTR (SCR_PAD1)
287
288
289 /* Misc */
290
291 #define REG_ENABLE_TX_RX (ENABLE)
292 /*
293 * Rx configuration (filter) information element
294 * ---------------------------------------------
295 */
296 #define REG_RX_CONFIG (RX_CFG)
297 #define REG_RX_FILTER (RX_FILTER_CFG)
298
299
300 #define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002
301
302 /* promiscuous - receives all valid frames */
303 #define RX_CFG_PROMISCUOUS 0x0008
304
305 /* receives frames from any BSSID */
306 #define RX_CFG_BSSID 0x0020
307
308 /* receives frames destined to any MAC address */
309 #define RX_CFG_MAC 0x0010
310
311 #define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010
312 #define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000
313 #define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020
314 #define RX_CFG_ENABLE_ANY_BSSID 0x0000
315
316 /* discards all broadcast frames */
317 #define RX_CFG_DISABLE_BCAST 0x0200
318
319 #define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400
320 #define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800
321 #define RX_CFG_COPY_RX_STATUS 0x2000
322 #define RX_CFG_TSF 0x10000
323
324 #define RX_CONFIG_OPTION_ANY_DST_MY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
325 RX_CFG_ENABLE_ONLY_MY_BSSID)
326
327 #define RX_CONFIG_OPTION_MY_DST_ANY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
328 | RX_CFG_ENABLE_ANY_BSSID)
329
330 #define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
331 RX_CFG_ENABLE_ANY_BSSID)
332
333 #define RX_CONFIG_OPTION_MY_DST_MY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
334 | RX_CFG_ENABLE_ONLY_MY_BSSID)
335
336 #define RX_CONFIG_OPTION_FOR_SCAN (RX_CFG_ENABLE_PHY_HEADER_PLCP \
337 | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \
338 | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF)
339
340 #define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC)
341
342 #define RX_CONFIG_OPTION_FOR_JOIN (RX_CFG_ENABLE_ONLY_MY_BSSID | \
343 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
344
345 #define RX_CONFIG_OPTION_FOR_IBSS_JOIN (RX_CFG_ENABLE_ONLY_MY_SSID | \
346 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
347
348 #define RX_FILTER_OPTION_DEF (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
349 | CFG_RX_CTL_EN | CFG_RX_BCN_EN\
350 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
351
352 #define RX_FILTER_OPTION_FILTER_ALL 0
353
354 #define RX_FILTER_OPTION_DEF_PRSP_BCN (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\
355 | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN)
356
357 #define RX_FILTER_OPTION_JOIN (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
358 | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\
359 | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\
360 | CFG_RX_PRSP_EN)
361
362
363 /*===============================================
364 EEPROM Read/Write Request 32bit RW
365 ------------------------------------------
366 1 EE_READ - EEPROM Read Request 1 - Setting this bit
367 loads a single byte of data into the EE_DATA
368 register from the EEPROM location specified in
369 the EE_ADDR register.
370 The Wlan hardware hardware clears this bit automatically.
371 EE_DATA is valid when this bit is cleared.
372
373 0 EE_WRITE - EEPROM Write Request - Setting this bit
374 writes a single byte of data from the EE_DATA register into the
375 EEPROM location specified in the EE_ADDR register.
376 The Wlan hardware hardware clears this bit automatically.
377 *===============================================*/
378 #define EE_CTL (REGISTERS_BASE + 0x2000)
379 #define ACX_EE_CTL_REG EE_CTL
380 #define EE_WRITE 0x00000001ul
381 #define EE_READ 0x00000002ul
382
383 /*===============================================
384 EEPROM Address - 32bit RW
385 ------------------------------------------
386 This register specifies the address
387 within the EEPROM from/to which to read/write data.
388 ===============================================*/
389 #define EE_ADDR (REGISTERS_BASE + 0x2008)
390 #define ACX_EE_ADDR_REG EE_ADDR
391
392 /*===============================================
393 EEPROM Data - 32bit RW
394 ------------------------------------------
395 This register either holds the read 8 bits of
396 data from the EEPROM or the write data
397 to be written to the EEPROM.
398 ===============================================*/
399 #define EE_DATA (REGISTERS_BASE + 0x2004)
400 #define ACX_EE_DATA_REG EE_DATA
401
402 #define EEPROM_ACCESS_TO 10000 /* timeout counter */
403 #define START_EEPROM_MGR 0x00000001
404
405 /*===============================================
406 EEPROM Base Address - 32bit RW
407 ------------------------------------------
408 This register holds the upper nine bits
409 [23:15] of the 24-bit Wlan hardware memory
410 address for burst reads from EEPROM accesses.
411 The EEPROM provides the lower 15 bits of this address.
412 The MSB of the address from the EEPROM is ignored.
413 ===============================================*/
414 #define ACX_EE_CFG EE_CFG
415
416 /*===============================================
417 GPIO Output Values -32bit, RW
418 ------------------------------------------
419 [31:16] Reserved
420 [15: 0] Specify the output values (at the output driver inputs) for
421 GPIO[15:0], respectively.
422 ===============================================*/
423 #define ACX_GPIO_OUT_REG GPIO_OUT
424 #define ACX_MAX_GPIO_LINES 15
425
426 /*===============================================
427 Contention window -32bit, RW
428 ------------------------------------------
429 [31:26] Reserved
430 [25:16] Max (0x3ff)
431 [15:07] Reserved
432 [06:00] Current contention window value - default is 0x1F
433 ===============================================*/
434 #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
435 #define ACX_CONT_WIND_MIN_MASK 0x0000007f
436 #define ACX_CONT_WIND_MAX 0x03ff0000
437
438 /*===============================================
439 HI_CFG Interface Configuration Register Values
440 ------------------------------------------
441 ===============================================*/
442 #define HI_CFG_UART_ENABLE 0x00000004
443 #define HI_CFG_RST232_ENABLE 0x00000008
444 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010
445 #define HI_CFG_HOST_INT_ENABLE 0x00000020
446 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
447 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
448 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
449 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
450 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
451
452 /*
453 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile
454 * for platforms using active high interrupt level
455 */
456 #ifdef USE_ACTIVE_HIGH
457 #define HI_CFG_DEF_VAL \
458 (HI_CFG_UART_ENABLE | \
459 HI_CFG_RST232_ENABLE | \
460 HI_CFG_CLOCK_REQ_SELECT | \
461 HI_CFG_HOST_INT_ENABLE)
462 #else
463 #define HI_CFG_DEF_VAL \
464 (HI_CFG_UART_ENABLE | \
465 HI_CFG_RST232_ENABLE | \
466 HI_CFG_CLOCK_REQ_SELECT | \
467 HI_CFG_HOST_INT_ENABLE)
468
469 #endif
470
471 #define REF_FREQ_19_2 0
472 #define REF_FREQ_26_0 1
473 #define REF_FREQ_38_4 2
474 #define REF_FREQ_40_0 3
475 #define REF_FREQ_33_6 4
476 #define REF_FREQ_NUM 5
477
478 #define LUT_PARAM_INTEGER_DIVIDER 0
479 #define LUT_PARAM_FRACTIONAL_DIVIDER 1
480 #define LUT_PARAM_ATTN_BB 2
481 #define LUT_PARAM_ALPHA_BB 3
482 #define LUT_PARAM_STOP_TIME_BB 4
483 #define LUT_PARAM_BB_PLL_LOOP_FILTER 5
484 #define LUT_PARAM_NUM 6
485
486 #define ACX_EEPROMLESS_IND_REG (SCR_PAD4)
487 #define USE_EEPROM 0
488 #define SOFT_RESET_MAX_TIME 1000000
489 #define SOFT_RESET_STALL_TIME 1000
490 #define NVS_DATA_BUNDARY_ALIGNMENT 4
491
492
493 /* Firmware image load chunk size */
494 #define CHUNK_SIZE 512
495
496 /* Firmware image header size */
497 #define FW_HDR_SIZE 8
498
499 #define ECPU_CONTROL_HALT 0x00000101
500
501
502 /******************************************************************************
503
504 CHANNELS, BAND & REG DOMAINS definitions
505
506 ******************************************************************************/
507
508
509 enum {
510 RADIO_BAND_2_4GHZ = 0, /* 2.4 Ghz band */
511 RADIO_BAND_5GHZ = 1, /* 5 Ghz band */
512 RADIO_BAND_JAPAN_4_9_GHZ = 2,
513 DEFAULT_BAND = RADIO_BAND_2_4GHZ,
514 INVALID_BAND = 0xFE,
515 MAX_RADIO_BANDS = 0xFF
516 };
517
518 enum {
519 NO_RATE = 0,
520 RATE_1MBPS = 0x0A,
521 RATE_2MBPS = 0x14,
522 RATE_5_5MBPS = 0x37,
523 RATE_6MBPS = 0x0B,
524 RATE_9MBPS = 0x0F,
525 RATE_11MBPS = 0x6E,
526 RATE_12MBPS = 0x0A,
527 RATE_18MBPS = 0x0E,
528 RATE_22MBPS = 0xDC,
529 RATE_24MBPS = 0x09,
530 RATE_36MBPS = 0x0D,
531 RATE_48MBPS = 0x08,
532 RATE_54MBPS = 0x0C
533 };
534
535 enum {
536 RATE_INDEX_1MBPS = 0,
537 RATE_INDEX_2MBPS = 1,
538 RATE_INDEX_5_5MBPS = 2,
539 RATE_INDEX_6MBPS = 3,
540 RATE_INDEX_9MBPS = 4,
541 RATE_INDEX_11MBPS = 5,
542 RATE_INDEX_12MBPS = 6,
543 RATE_INDEX_18MBPS = 7,
544 RATE_INDEX_22MBPS = 8,
545 RATE_INDEX_24MBPS = 9,
546 RATE_INDEX_36MBPS = 10,
547 RATE_INDEX_48MBPS = 11,
548 RATE_INDEX_54MBPS = 12,
549 RATE_INDEX_MAX = RATE_INDEX_54MBPS,
550 MAX_RATE_INDEX,
551 INVALID_RATE_INDEX = MAX_RATE_INDEX,
552 RATE_INDEX_ENUM_MAX_SIZE = 0x7FFFFFFF
553 };
554
555 enum {
556 RATE_MASK_1MBPS = 0x1,
557 RATE_MASK_2MBPS = 0x2,
558 RATE_MASK_5_5MBPS = 0x4,
559 RATE_MASK_11MBPS = 0x20,
560 };
561
562 #define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */
563 #define OFDM_RATE_BIT BIT(6)
564 #define PBCC_RATE_BIT BIT(7)
565
566 enum {
567 CCK_LONG = 0,
568 CCK_SHORT = SHORT_PREAMBLE_BIT,
569 PBCC_LONG = PBCC_RATE_BIT,
570 PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,
571 OFDM = OFDM_RATE_BIT
572 };
573
574 /******************************************************************************
575
576 Transmit-Descriptor RATE-SET field definitions...
577
578 Define a new "Rate-Set" for TX path that incorporates the
579 Rate & Modulation info into a single 16-bit field.
580
581 TxdRateSet_t:
582 b15 - Indicates Preamble type (1=SHORT, 0=LONG).
583 Notes:
584 Must be LONG (0) for 1Mbps rate.
585 Does not apply (set to 0) for RevG-OFDM rates.
586 b14 - Indicates PBCC encoding (1=PBCC, 0=not).
587 Notes:
588 Does not apply (set to 0) for rates 1 and 2 Mbps.
589 Does not apply (set to 0) for RevG-OFDM rates.
590 b13 - Unused (set to 0).
591 b12-b0 - Supported Rate indicator bits as defined below.
592
593 ******************************************************************************/
594
595
596 /*************************************************************************
597
598 Interrupt Trigger Register (Host -> WiLink)
599
600 **************************************************************************/
601
602 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
603
604 /*
605 * Host Command Interrupt. Setting this bit masks
606 * the interrupt that the host issues to inform
607 * the FW that it has sent a command
608 * to the Wlan hardware Command Mailbox.
609 */
610 #define INTR_TRIG_CMD BIT(0)
611
612 /*
613 * Host Event Acknowlegde Interrupt. The host
614 * sets this bit to acknowledge that it received
615 * the unsolicited information from the event
616 * mailbox.
617 */
618 #define INTR_TRIG_EVENT_ACK BIT(1)
619
620 /*
621 * The host sets this bit to inform the Wlan
622 * FW that a TX packet is in the XFER
623 * Buffer #0.
624 */
625 #define INTR_TRIG_TX_PROC0 BIT(2)
626
627 /*
628 * The host sets this bit to inform the FW
629 * that it read a packet from RX XFER
630 * Buffer #0.
631 */
632 #define INTR_TRIG_RX_PROC0 BIT(3)
633
634 #define INTR_TRIG_DEBUG_ACK BIT(4)
635
636 #define INTR_TRIG_STATE_CHANGED BIT(5)
637
638
639 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
640
641 /*
642 * The host sets this bit to inform the FW
643 * that it read a packet from RX XFER
644 * Buffer #1.
645 */
646 #define INTR_TRIG_RX_PROC1 BIT(17)
647
648 /*
649 * The host sets this bit to inform the Wlan
650 * hardware that a TX packet is in the XFER
651 * Buffer #1.
652 */
653 #define INTR_TRIG_TX_PROC1 BIT(18)
654
655 #endif