spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / net / wireless / wl12xx / rx.h
blob86ba6b1d0cdc42a59889cb364d95f29d6c911d2b
1 /*
2 * This file is part of wl1271
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2009 Nokia Corporation
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
25 #ifndef __RX_H__
26 #define __RX_H__
28 #include <linux/bitops.h>
30 #define WL1271_RX_MAX_RSSI -30
31 #define WL1271_RX_MIN_RSSI -95
33 #define SHORT_PREAMBLE_BIT BIT(0)
34 #define OFDM_RATE_BIT BIT(6)
35 #define PBCC_RATE_BIT BIT(7)
37 #define PLCP_HEADER_LENGTH 8
38 #define RX_DESC_PACKETID_SHIFT 11
39 #define RX_MAX_PACKET_ID 3
41 #define NUM_RX_PKT_DESC_MOD_MASK 7
43 #define RX_DESC_VALID_FCS 0x0001
44 #define RX_DESC_MATCH_RXADDR1 0x0002
45 #define RX_DESC_MCAST 0x0004
46 #define RX_DESC_STAINTIM 0x0008
47 #define RX_DESC_VIRTUAL_BM 0x0010
48 #define RX_DESC_BCAST 0x0020
49 #define RX_DESC_MATCH_SSID 0x0040
50 #define RX_DESC_MATCH_BSSID 0x0080
51 #define RX_DESC_ENCRYPTION_MASK 0x0300
52 #define RX_DESC_MEASURMENT 0x0400
53 #define RX_DESC_SEQNUM_MASK 0x1800
54 #define RX_DESC_MIC_FAIL 0x2000
55 #define RX_DESC_DECRYPT_FAIL 0x4000
58 * RX Descriptor flags:
60 * Bits 0-1 - band
61 * Bit 2 - STBC
62 * Bit 3 - A-MPDU
63 * Bit 4 - HT
64 * Bits 5-7 - encryption
66 #define WL1271_RX_DESC_BAND_MASK 0x03
67 #define WL1271_RX_DESC_ENCRYPT_MASK 0xE0
69 #define WL1271_RX_DESC_BAND_BG 0x00
70 #define WL1271_RX_DESC_BAND_J 0x01
71 #define WL1271_RX_DESC_BAND_A 0x02
73 #define WL1271_RX_DESC_STBC BIT(2)
74 #define WL1271_RX_DESC_A_MPDU BIT(3)
75 #define WL1271_RX_DESC_HT BIT(4)
77 #define WL1271_RX_DESC_ENCRYPT_WEP 0x20
78 #define WL1271_RX_DESC_ENCRYPT_TKIP 0x40
79 #define WL1271_RX_DESC_ENCRYPT_AES 0x60
80 #define WL1271_RX_DESC_ENCRYPT_GEM 0x80
83 * RX Descriptor status
85 * Bits 0-2 - error code
86 * Bits 3-5 - process_id tag (AP mode FW)
87 * Bits 6-7 - reserved
89 #define WL1271_RX_DESC_STATUS_MASK 0x03
91 #define WL1271_RX_DESC_SUCCESS 0x00
92 #define WL1271_RX_DESC_DECRYPT_FAIL 0x01
93 #define WL1271_RX_DESC_MIC_FAIL 0x02
94 #define WL1271_RX_DESC_DRIVER_RX_Q_FAIL 0x03
96 #define RX_MEM_BLOCK_MASK 0xFF
97 #define RX_BUF_SIZE_MASK 0xFFF00
98 #define RX_BUF_SIZE_SHIFT_DIV 6
99 /* If set, the start of IP payload is not 4 bytes aligned */
100 #define RX_BUF_UNALIGNED_PAYLOAD BIT(20)
102 enum {
103 WL12XX_RX_CLASS_UNKNOWN,
104 WL12XX_RX_CLASS_MANAGEMENT,
105 WL12XX_RX_CLASS_DATA,
106 WL12XX_RX_CLASS_QOS_DATA,
107 WL12XX_RX_CLASS_BCN_PRBRSP,
108 WL12XX_RX_CLASS_EAPOL,
109 WL12XX_RX_CLASS_BA_EVENT,
110 WL12XX_RX_CLASS_AMSDU,
111 WL12XX_RX_CLASS_LOGGER,
114 struct wl1271_rx_descriptor {
115 __le16 length;
116 u8 status;
117 u8 flags;
118 u8 rate;
119 u8 channel;
120 s8 rssi;
121 u8 snr;
122 __le32 timestamp;
123 u8 packet_class;
124 u8 hlid;
125 u8 pad_len;
126 u8 reserved;
127 } __packed;
129 void wl12xx_rx(struct wl1271 *wl, struct wl12xx_fw_status *status);
130 u8 wl1271_rate_to_idx(int rate, enum ieee80211_band band);
132 #endif