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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / usb / dwc3 / gadget.c
blobacea57a9a05b2530356c5952a69e61483c806622
1 /**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
46 #include <linux/io.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
49
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
52
53 #include "core.h"
54 #include "gadget.h"
55 #include "io.h"
56
57 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59 void dwc3_map_buffer_to_dma(struct dwc3_request *req)
60 {
61 struct dwc3 *dwc = req->dep->dwc;
62
63 if (req->request.length == 0) {
64 /* req->request.dma = dwc->setup_buf_addr; */
65 return;
66 }
67
68 if (req->request.num_sgs) {
69 int mapped;
70
71 mapped = dma_map_sg(dwc->dev, req->request.sg,
72 req->request.num_sgs,
73 req->direction ? DMA_TO_DEVICE
74 : DMA_FROM_DEVICE);
75 if (mapped < 0) {
76 dev_err(dwc->dev, "failed to map SGs\n");
77 return;
78 }
79
80 req->request.num_mapped_sgs = mapped;
81 return;
82 }
83
84 if (req->request.dma == DMA_ADDR_INVALID) {
85 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
86 req->request.length, req->direction
87 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
88 req->mapped = true;
89 }
90 }
91
92 void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
93 {
94 struct dwc3 *dwc = req->dep->dwc;
95
96 if (req->request.length == 0) {
97 req->request.dma = DMA_ADDR_INVALID;
98 return;
99 }
100
101 if (req->request.num_mapped_sgs) {
102 req->request.dma = DMA_ADDR_INVALID;
103 dma_unmap_sg(dwc->dev, req->request.sg,
104 req->request.num_mapped_sgs,
105 req->direction ? DMA_TO_DEVICE
106 : DMA_FROM_DEVICE);
107
108 req->request.num_mapped_sgs = 0;
109 return;
110 }
111
112 if (req->mapped) {
113 dma_unmap_single(dwc->dev, req->request.dma,
114 req->request.length, req->direction
115 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
116 req->mapped = 0;
117 req->request.dma = DMA_ADDR_INVALID;
118 }
119 }
120
121 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
122 int status)
123 {
124 struct dwc3 *dwc = dep->dwc;
125
126 if (req->queued) {
127 if (req->request.num_mapped_sgs)
128 dep->busy_slot += req->request.num_mapped_sgs;
129 else
130 dep->busy_slot++;
131
132 /*
133 * Skip LINK TRB. We can't use req->trb and check for
134 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
135 * completed (not the LINK TRB).
136 */
137 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
138 usb_endpoint_xfer_isoc(dep->desc))
139 dep->busy_slot++;
140 }
141 list_del(&req->list);
142 req->trb = NULL;
143
144 if (req->request.status == -EINPROGRESS)
145 req->request.status = status;
146
147 dwc3_unmap_buffer_from_dma(req);
148
149 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
150 req, dep->name, req->request.actual,
151 req->request.length, status);
152
153 spin_unlock(&dwc->lock);
154 req->request.complete(&req->dep->endpoint, &req->request);
155 spin_lock(&dwc->lock);
156 }
157
158 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
159 {
160 switch (cmd) {
161 case DWC3_DEPCMD_DEPSTARTCFG:
162 return "Start New Configuration";
163 case DWC3_DEPCMD_ENDTRANSFER:
164 return "End Transfer";
165 case DWC3_DEPCMD_UPDATETRANSFER:
166 return "Update Transfer";
167 case DWC3_DEPCMD_STARTTRANSFER:
168 return "Start Transfer";
169 case DWC3_DEPCMD_CLEARSTALL:
170 return "Clear Stall";
171 case DWC3_DEPCMD_SETSTALL:
172 return "Set Stall";
173 case DWC3_DEPCMD_GETSEQNUMBER:
174 return "Get Data Sequence Number";
175 case DWC3_DEPCMD_SETTRANSFRESOURCE:
176 return "Set Endpoint Transfer Resource";
177 case DWC3_DEPCMD_SETEPCONFIG:
178 return "Set Endpoint Configuration";
179 default:
180 return "UNKNOWN command";
181 }
182 }
183
184 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
185 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
186 {
187 struct dwc3_ep *dep = dwc->eps[ep];
188 u32 timeout = 500;
189 u32 reg;
190
191 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
192 dep->name,
193 dwc3_gadget_ep_cmd_string(cmd), params->param0,
194 params->param1, params->param2);
195
196 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
197 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
198 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
199
200 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
201 do {
202 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
203 if (!(reg & DWC3_DEPCMD_CMDACT)) {
204 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
205 DWC3_DEPCMD_STATUS(reg));
206 return 0;
207 }
208
209 /*
210 * We can't sleep here, because it is also called from
211 * interrupt context.
212 */
213 timeout--;
214 if (!timeout)
215 return -ETIMEDOUT;
216
217 udelay(1);
218 } while (1);
219 }
220
221 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
222 struct dwc3_trb_hw *trb)
223 {
224 u32 offset = (char *) trb - (char *) dep->trb_pool;
225
226 return dep->trb_pool_dma + offset;
227 }
228
229 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
230 {
231 struct dwc3 *dwc = dep->dwc;
232
233 if (dep->trb_pool)
234 return 0;
235
236 if (dep->number == 0 || dep->number == 1)
237 return 0;
238
239 dep->trb_pool = dma_alloc_coherent(dwc->dev,
240 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
241 &dep->trb_pool_dma, GFP_KERNEL);
242 if (!dep->trb_pool) {
243 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
244 dep->name);
245 return -ENOMEM;
246 }
247
248 return 0;
249 }
250
251 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
252 {
253 struct dwc3 *dwc = dep->dwc;
254
255 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
256 dep->trb_pool, dep->trb_pool_dma);
257
258 dep->trb_pool = NULL;
259 dep->trb_pool_dma = 0;
260 }
261
262 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
263 {
264 struct dwc3_gadget_ep_cmd_params params;
265 u32 cmd;
266
267 memset(&params, 0x00, sizeof(params));
268
269 if (dep->number != 1) {
270 cmd = DWC3_DEPCMD_DEPSTARTCFG;
271 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
272 if (dep->number > 1) {
273 if (dwc->start_config_issued)
274 return 0;
275 dwc->start_config_issued = true;
276 cmd |= DWC3_DEPCMD_PARAM(2);
277 }
278
279 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
280 }
281
282 return 0;
283 }
284
285 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
286 const struct usb_endpoint_descriptor *desc,
287 const struct usb_ss_ep_comp_descriptor *comp_desc)
288 {
289 struct dwc3_gadget_ep_cmd_params params;
290
291 memset(&params, 0x00, sizeof(params));
292
293 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
294 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
295 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
296
297 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
298 | DWC3_DEPCFG_XFER_NOT_READY_EN;
299
300 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
301 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
302 | DWC3_DEPCFG_STREAM_EVENT_EN;
303 dep->stream_capable = true;
304 }
305
306 if (usb_endpoint_xfer_isoc(desc))
307 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
308
309 /*
310 * We are doing 1:1 mapping for endpoints, meaning
311 * Physical Endpoints 2 maps to Logical Endpoint 2 and
312 * so on. We consider the direction bit as part of the physical
313 * endpoint number. So USB endpoint 0x81 is 0x03.
314 */
315 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
316
317 /*
318 * We must use the lower 16 TX FIFOs even though
319 * HW might have more
320 */
321 if (dep->direction)
322 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
323
324 if (desc->bInterval) {
325 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
326 dep->interval = 1 << (desc->bInterval - 1);
327 }
328
329 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
330 DWC3_DEPCMD_SETEPCONFIG, &params);
331 }
332
333 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
334 {
335 struct dwc3_gadget_ep_cmd_params params;
336
337 memset(&params, 0x00, sizeof(params));
338
339 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
340
341 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
342 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
343 }
344
345 /**
346 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
347 * @dep: endpoint to be initialized
348 * @desc: USB Endpoint Descriptor
349 *
350 * Caller should take care of locking
351 */
352 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
353 const struct usb_endpoint_descriptor *desc,
354 const struct usb_ss_ep_comp_descriptor *comp_desc)
355 {
356 struct dwc3 *dwc = dep->dwc;
357 u32 reg;
358 int ret = -ENOMEM;
359
360 if (!(dep->flags & DWC3_EP_ENABLED)) {
361 ret = dwc3_gadget_start_config(dwc, dep);
362 if (ret)
363 return ret;
364 }
365
366 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
367 if (ret)
368 return ret;
369
370 if (!(dep->flags & DWC3_EP_ENABLED)) {
371 struct dwc3_trb_hw *trb_st_hw;
372 struct dwc3_trb_hw *trb_link_hw;
373 struct dwc3_trb trb_link;
374
375 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
376 if (ret)
377 return ret;
378
379 dep->desc = desc;
380 dep->comp_desc = comp_desc;
381 dep->type = usb_endpoint_type(desc);
382 dep->flags |= DWC3_EP_ENABLED;
383
384 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
385 reg |= DWC3_DALEPENA_EP(dep->number);
386 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
387
388 if (!usb_endpoint_xfer_isoc(desc))
389 return 0;
390
391 memset(&trb_link, 0, sizeof(trb_link));
392
393 /* Link TRB for ISOC. The HWO but is never reset */
394 trb_st_hw = &dep->trb_pool[0];
395
396 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
397 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
398 trb_link.hwo = true;
399
400 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
401 dwc3_trb_to_hw(&trb_link, trb_link_hw);
402 }
403
404 return 0;
405 }
406
407 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
408 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
409 {
410 struct dwc3_request *req;
411
412 if (!list_empty(&dep->req_queued))
413 dwc3_stop_active_transfer(dwc, dep->number);
414
415 while (!list_empty(&dep->request_list)) {
416 req = next_request(&dep->request_list);
417
418 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
419 }
420 }
421
422 /**
423 * __dwc3_gadget_ep_disable - Disables a HW endpoint
424 * @dep: the endpoint to disable
425 *
426 * This function also removes requests which are currently processed ny the
427 * hardware and those which are not yet scheduled.
428 * Caller should take care of locking.
429 */
430 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
431 {
432 struct dwc3 *dwc = dep->dwc;
433 u32 reg;
434
435 dwc3_remove_requests(dwc, dep);
436
437 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
438 reg &= ~DWC3_DALEPENA_EP(dep->number);
439 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
440
441 dep->stream_capable = false;
442 dep->desc = NULL;
443 dep->endpoint.desc = NULL;
444 dep->comp_desc = NULL;
445 dep->type = 0;
446 dep->flags = 0;
447
448 return 0;
449 }
450
451 /* -------------------------------------------------------------------------- */
452
453 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
454 const struct usb_endpoint_descriptor *desc)
455 {
456 return -EINVAL;
457 }
458
459 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
460 {
461 return -EINVAL;
462 }
463
464 /* -------------------------------------------------------------------------- */
465
466 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
467 const struct usb_endpoint_descriptor *desc)
468 {
469 struct dwc3_ep *dep;
470 struct dwc3 *dwc;
471 unsigned long flags;
472 int ret;
473
474 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
475 pr_debug("dwc3: invalid parameters\n");
476 return -EINVAL;
477 }
478
479 if (!desc->wMaxPacketSize) {
480 pr_debug("dwc3: missing wMaxPacketSize\n");
481 return -EINVAL;
482 }
483
484 dep = to_dwc3_ep(ep);
485 dwc = dep->dwc;
486
487 switch (usb_endpoint_type(desc)) {
488 case USB_ENDPOINT_XFER_CONTROL:
489 strlcat(dep->name, "-control", sizeof(dep->name));
490 break;
491 case USB_ENDPOINT_XFER_ISOC:
492 strlcat(dep->name, "-isoc", sizeof(dep->name));
493 break;
494 case USB_ENDPOINT_XFER_BULK:
495 strlcat(dep->name, "-bulk", sizeof(dep->name));
496 break;
497 case USB_ENDPOINT_XFER_INT:
498 strlcat(dep->name, "-int", sizeof(dep->name));
499 break;
500 default:
501 dev_err(dwc->dev, "invalid endpoint transfer type\n");
502 }
503
504 if (dep->flags & DWC3_EP_ENABLED) {
505 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
506 dep->name);
507 return 0;
508 }
509
510 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
511
512 spin_lock_irqsave(&dwc->lock, flags);
513 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
514 spin_unlock_irqrestore(&dwc->lock, flags);
515
516 return ret;
517 }
518
519 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
520 {
521 struct dwc3_ep *dep;
522 struct dwc3 *dwc;
523 unsigned long flags;
524 int ret;
525
526 if (!ep) {
527 pr_debug("dwc3: invalid parameters\n");
528 return -EINVAL;
529 }
530
531 dep = to_dwc3_ep(ep);
532 dwc = dep->dwc;
533
534 if (!(dep->flags & DWC3_EP_ENABLED)) {
535 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
536 dep->name);
537 return 0;
538 }
539
540 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
541 dep->number >> 1,
542 (dep->number & 1) ? "in" : "out");
543
544 spin_lock_irqsave(&dwc->lock, flags);
545 ret = __dwc3_gadget_ep_disable(dep);
546 spin_unlock_irqrestore(&dwc->lock, flags);
547
548 return ret;
549 }
550
551 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
552 gfp_t gfp_flags)
553 {
554 struct dwc3_request *req;
555 struct dwc3_ep *dep = to_dwc3_ep(ep);
556 struct dwc3 *dwc = dep->dwc;
557
558 req = kzalloc(sizeof(*req), gfp_flags);
559 if (!req) {
560 dev_err(dwc->dev, "not enough memory\n");
561 return NULL;
562 }
563
564 req->epnum = dep->number;
565 req->dep = dep;
566 req->request.dma = DMA_ADDR_INVALID;
567
568 return &req->request;
569 }
570
571 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
572 struct usb_request *request)
573 {
574 struct dwc3_request *req = to_dwc3_request(request);
575
576 kfree(req);
577 }
578
579 /**
580 * dwc3_prepare_one_trb - setup one TRB from one request
581 * @dep: endpoint for which this request is prepared
582 * @req: dwc3_request pointer
583 */
584 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
585 struct dwc3_request *req, dma_addr_t dma,
586 unsigned length, unsigned last, unsigned chain)
587 {
588 struct dwc3 *dwc = dep->dwc;
589 struct dwc3_trb_hw *trb_hw;
590 struct dwc3_trb trb;
591
592 unsigned int cur_slot;
593
594 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
595 dep->name, req, (unsigned long long) dma,
596 length, last ? " last" : "",
597 chain ? " chain" : "");
598
599 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
600 cur_slot = dep->free_slot;
601 dep->free_slot++;
602
603 /* Skip the LINK-TRB on ISOC */
604 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
605 usb_endpoint_xfer_isoc(dep->desc))
606 return;
607
608 memset(&trb, 0, sizeof(trb));
609 if (!req->trb) {
610 dwc3_gadget_move_request_queued(req);
611 req->trb = trb_hw;
612 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
613 }
614
615 if (usb_endpoint_xfer_isoc(dep->desc)) {
616 trb.isp_imi = true;
617 trb.csp = true;
618 } else {
619 trb.chn = chain;
620 trb.lst = last;
621 }
622
623 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
624 trb.sid_sofn = req->request.stream_id;
625
626 switch (usb_endpoint_type(dep->desc)) {
627 case USB_ENDPOINT_XFER_CONTROL:
628 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
629 break;
630
631 case USB_ENDPOINT_XFER_ISOC:
632 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
633
634 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
635 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
636 trb.ioc = last;
637 break;
638
639 case USB_ENDPOINT_XFER_BULK:
640 case USB_ENDPOINT_XFER_INT:
641 trb.trbctl = DWC3_TRBCTL_NORMAL;
642 break;
643 default:
644 /*
645 * This is only possible with faulty memory because we
646 * checked it already :)
647 */
648 BUG();
649 }
650
651 trb.length = length;
652 trb.bplh = dma;
653 trb.hwo = true;
654
655 dwc3_trb_to_hw(&trb, trb_hw);
656 }
657
658 /*
659 * dwc3_prepare_trbs - setup TRBs from requests
660 * @dep: endpoint for which requests are being prepared
661 * @starting: true if the endpoint is idle and no requests are queued.
662 *
663 * The functions goes through the requests list and setups TRBs for the
664 * transfers. The functions returns once there are not more TRBs available or
665 * it run out of requests.
666 */
667 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
668 {
669 struct dwc3_request *req, *n;
670 u32 trbs_left;
671 u32 max;
672 unsigned int last_one = 0;
673
674 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
675
676 /* the first request must not be queued */
677 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
678
679 /* Can't wrap around on a non-isoc EP since there's no link TRB */
680 if (!usb_endpoint_xfer_isoc(dep->desc)) {
681 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
682 if (trbs_left > max)
683 trbs_left = max;
684 }
685
686 /*
687 * if busy & slot are equal than it is either full or empty. If we are
688 * starting to proceed requests then we are empty. Otherwise we ar
689 * full and don't do anything
690 */
691 if (!trbs_left) {
692 if (!starting)
693 return;
694 trbs_left = DWC3_TRB_NUM;
695 /*
696 * In case we start from scratch, we queue the ISOC requests
697 * starting from slot 1. This is done because we use ring
698 * buffer and have no LST bit to stop us. Instead, we place
699 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
700 * after the first request so we start at slot 1 and have
701 * 7 requests proceed before we hit the first IOC.
702 * Other transfer types don't use the ring buffer and are
703 * processed from the first TRB until the last one. Since we
704 * don't wrap around we have to start at the beginning.
705 */
706 if (usb_endpoint_xfer_isoc(dep->desc)) {
707 dep->busy_slot = 1;
708 dep->free_slot = 1;
709 } else {
710 dep->busy_slot = 0;
711 dep->free_slot = 0;
712 }
713 }
714
715 /* The last TRB is a link TRB, not used for xfer */
716 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
717 return;
718
719 list_for_each_entry_safe(req, n, &dep->request_list, list) {
720 unsigned length;
721 dma_addr_t dma;
722
723 if (req->request.num_mapped_sgs > 0) {
724 struct usb_request *request = &req->request;
725 struct scatterlist *sg = request->sg;
726 struct scatterlist *s;
727 int i;
728
729 for_each_sg(sg, s, request->num_mapped_sgs, i) {
730 unsigned chain = true;
731
732 length = sg_dma_len(s);
733 dma = sg_dma_address(s);
734
735 if (i == (request->num_mapped_sgs - 1)
736 || sg_is_last(s)) {
737 last_one = true;
738 chain = false;
739 }
740
741 trbs_left--;
742 if (!trbs_left)
743 last_one = true;
744
745 if (last_one)
746 chain = false;
747
748 dwc3_prepare_one_trb(dep, req, dma, length,
749 last_one, chain);
750
751 if (last_one)
752 break;
753 }
754 } else {
755 dma = req->request.dma;
756 length = req->request.length;
757 trbs_left--;
758
759 if (!trbs_left)
760 last_one = 1;
761
762 /* Is this the last request? */
763 if (list_is_last(&req->list, &dep->request_list))
764 last_one = 1;
765
766 dwc3_prepare_one_trb(dep, req, dma, length,
767 last_one, false);
768
769 if (last_one)
770 break;
771 }
772 }
773 }
774
775 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
776 int start_new)
777 {
778 struct dwc3_gadget_ep_cmd_params params;
779 struct dwc3_request *req;
780 struct dwc3 *dwc = dep->dwc;
781 int ret;
782 u32 cmd;
783
784 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
785 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
786 return -EBUSY;
787 }
788 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
789
790 /*
791 * If we are getting here after a short-out-packet we don't enqueue any
792 * new requests as we try to set the IOC bit only on the last request.
793 */
794 if (start_new) {
795 if (list_empty(&dep->req_queued))
796 dwc3_prepare_trbs(dep, start_new);
797
798 /* req points to the first request which will be sent */
799 req = next_request(&dep->req_queued);
800 } else {
801 dwc3_prepare_trbs(dep, start_new);
802
803 /*
804 * req points to the first request where HWO changed
805 * from 0 to 1
806 */
807 req = next_request(&dep->req_queued);
808 }
809 if (!req) {
810 dep->flags |= DWC3_EP_PENDING_REQUEST;
811 return 0;
812 }
813
814 memset(&params, 0, sizeof(params));
815 params.param0 = upper_32_bits(req->trb_dma);
816 params.param1 = lower_32_bits(req->trb_dma);
817
818 if (start_new)
819 cmd = DWC3_DEPCMD_STARTTRANSFER;
820 else
821 cmd = DWC3_DEPCMD_UPDATETRANSFER;
822
823 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
824 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
825 if (ret < 0) {
826 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
827
828 /*
829 * FIXME we need to iterate over the list of requests
830 * here and stop, unmap, free and del each of the linked
831 * requests instead of we do now.
832 */
833 dwc3_unmap_buffer_from_dma(req);
834 list_del(&req->list);
835 return ret;
836 }
837
838 dep->flags |= DWC3_EP_BUSY;
839 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
840 dep->number);
841
842 WARN_ON_ONCE(!dep->res_trans_idx);
843
844 return 0;
845 }
846
847 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
848 {
849 req->request.actual = 0;
850 req->request.status = -EINPROGRESS;
851 req->direction = dep->direction;
852 req->epnum = dep->number;
853
854 /*
855 * We only add to our list of requests now and
856 * start consuming the list once we get XferNotReady
857 * IRQ.
858 *
859 * That way, we avoid doing anything that we don't need
860 * to do now and defer it until the point we receive a
861 * particular token from the Host side.
862 *
863 * This will also avoid Host cancelling URBs due to too
864 * many NACKs.
865 */
866 dwc3_map_buffer_to_dma(req);
867 list_add_tail(&req->list, &dep->request_list);
868
869 /*
870 * There is one special case: XferNotReady with
871 * empty list of requests. We need to kick the
872 * transfer here in that situation, otherwise
873 * we will be NAKing forever.
874 *
875 * If we get XferNotReady before gadget driver
876 * has a chance to queue a request, we will ACK
877 * the IRQ but won't be able to receive the data
878 * until the next request is queued. The following
879 * code is handling exactly that.
880 */
881 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
882 int ret;
883 int start_trans;
884
885 start_trans = 1;
886 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
887 dep->flags & DWC3_EP_BUSY)
888 start_trans = 0;
889
890 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
891 if (ret && ret != -EBUSY) {
892 struct dwc3 *dwc = dep->dwc;
893
894 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
895 dep->name);
896 }
897 };
898
899 return 0;
900 }
901
902 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
903 gfp_t gfp_flags)
904 {
905 struct dwc3_request *req = to_dwc3_request(request);
906 struct dwc3_ep *dep = to_dwc3_ep(ep);
907 struct dwc3 *dwc = dep->dwc;
908
909 unsigned long flags;
910
911 int ret;
912
913 if (!dep->desc) {
914 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
915 request, ep->name);
916 return -ESHUTDOWN;
917 }
918
919 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
920 request, ep->name, request->length);
921
922 spin_lock_irqsave(&dwc->lock, flags);
923 ret = __dwc3_gadget_ep_queue(dep, req);
924 spin_unlock_irqrestore(&dwc->lock, flags);
925
926 return ret;
927 }
928
929 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
930 struct usb_request *request)
931 {
932 struct dwc3_request *req = to_dwc3_request(request);
933 struct dwc3_request *r = NULL;
934
935 struct dwc3_ep *dep = to_dwc3_ep(ep);
936 struct dwc3 *dwc = dep->dwc;
937
938 unsigned long flags;
939 int ret = 0;
940
941 spin_lock_irqsave(&dwc->lock, flags);
942
943 list_for_each_entry(r, &dep->request_list, list) {
944 if (r == req)
945 break;
946 }
947
948 if (r != req) {
949 list_for_each_entry(r, &dep->req_queued, list) {
950 if (r == req)
951 break;
952 }
953 if (r == req) {
954 /* wait until it is processed */
955 dwc3_stop_active_transfer(dwc, dep->number);
956 goto out0;
957 }
958 dev_err(dwc->dev, "request %p was not queued to %s\n",
959 request, ep->name);
960 ret = -EINVAL;
961 goto out0;
962 }
963
964 /* giveback the request */
965 dwc3_gadget_giveback(dep, req, -ECONNRESET);
966
967 out0:
968 spin_unlock_irqrestore(&dwc->lock, flags);
969
970 return ret;
971 }
972
973 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
974 {
975 struct dwc3_gadget_ep_cmd_params params;
976 struct dwc3 *dwc = dep->dwc;
977 int ret;
978
979 memset(&params, 0x00, sizeof(params));
980
981 if (value) {
982 if (dep->number == 0 || dep->number == 1) {
983 /*
984 * Whenever EP0 is stalled, we will restart
985 * the state machine, thus moving back to
986 * Setup Phase
987 */
988 dwc->ep0state = EP0_SETUP_PHASE;
989 }
990
991 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
992 DWC3_DEPCMD_SETSTALL, &params);
993 if (ret)
994 dev_err(dwc->dev, "failed to %s STALL on %s\n",
995 value ? "set" : "clear",
996 dep->name);
997 else
998 dep->flags |= DWC3_EP_STALL;
999 } else {
1000 if (dep->flags & DWC3_EP_WEDGE)
1001 return 0;
1002
1003 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1004 DWC3_DEPCMD_CLEARSTALL, &params);
1005 if (ret)
1006 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1007 value ? "set" : "clear",
1008 dep->name);
1009 else
1010 dep->flags &= ~DWC3_EP_STALL;
1011 }
1012
1013 return ret;
1014 }
1015
1016 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1017 {
1018 struct dwc3_ep *dep = to_dwc3_ep(ep);
1019 struct dwc3 *dwc = dep->dwc;
1020
1021 unsigned long flags;
1022
1023 int ret;
1024
1025 spin_lock_irqsave(&dwc->lock, flags);
1026
1027 if (usb_endpoint_xfer_isoc(dep->desc)) {
1028 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1029 ret = -EINVAL;
1030 goto out;
1031 }
1032
1033 ret = __dwc3_gadget_ep_set_halt(dep, value);
1034 out:
1035 spin_unlock_irqrestore(&dwc->lock, flags);
1036
1037 return ret;
1038 }
1039
1040 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1041 {
1042 struct dwc3_ep *dep = to_dwc3_ep(ep);
1043
1044 dep->flags |= DWC3_EP_WEDGE;
1045
1046 return dwc3_gadget_ep_set_halt(ep, 1);
1047 }
1048
1049 /* -------------------------------------------------------------------------- */
1050
1051 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1052 .bLength = USB_DT_ENDPOINT_SIZE,
1053 .bDescriptorType = USB_DT_ENDPOINT,
1054 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1055 };
1056
1057 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1058 .enable = dwc3_gadget_ep0_enable,
1059 .disable = dwc3_gadget_ep0_disable,
1060 .alloc_request = dwc3_gadget_ep_alloc_request,
1061 .free_request = dwc3_gadget_ep_free_request,
1062 .queue = dwc3_gadget_ep0_queue,
1063 .dequeue = dwc3_gadget_ep_dequeue,
1064 .set_halt = dwc3_gadget_ep_set_halt,
1065 .set_wedge = dwc3_gadget_ep_set_wedge,
1066 };
1067
1068 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1069 .enable = dwc3_gadget_ep_enable,
1070 .disable = dwc3_gadget_ep_disable,
1071 .alloc_request = dwc3_gadget_ep_alloc_request,
1072 .free_request = dwc3_gadget_ep_free_request,
1073 .queue = dwc3_gadget_ep_queue,
1074 .dequeue = dwc3_gadget_ep_dequeue,
1075 .set_halt = dwc3_gadget_ep_set_halt,
1076 .set_wedge = dwc3_gadget_ep_set_wedge,
1077 };
1078
1079 /* -------------------------------------------------------------------------- */
1080
1081 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1082 {
1083 struct dwc3 *dwc = gadget_to_dwc(g);
1084 u32 reg;
1085
1086 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1087 return DWC3_DSTS_SOFFN(reg);
1088 }
1089
1090 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1091 {
1092 struct dwc3 *dwc = gadget_to_dwc(g);
1093
1094 unsigned long timeout;
1095 unsigned long flags;
1096
1097 u32 reg;
1098
1099 int ret = 0;
1100
1101 u8 link_state;
1102 u8 speed;
1103
1104 spin_lock_irqsave(&dwc->lock, flags);
1105
1106 /*
1107 * According to the Databook Remote wakeup request should
1108 * be issued only when the device is in early suspend state.
1109 *
1110 * We can check that via USB Link State bits in DSTS register.
1111 */
1112 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1113
1114 speed = reg & DWC3_DSTS_CONNECTSPD;
1115 if (speed == DWC3_DSTS_SUPERSPEED) {
1116 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1117 ret = -EINVAL;
1118 goto out;
1119 }
1120
1121 link_state = DWC3_DSTS_USBLNKST(reg);
1122
1123 switch (link_state) {
1124 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1125 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1126 break;
1127 default:
1128 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1129 link_state);
1130 ret = -EINVAL;
1131 goto out;
1132 }
1133
1134 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1135
1136 /*
1137 * Switch link state to Recovery. In HS/FS/LS this means
1138 * RemoteWakeup Request
1139 */
1140 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1141 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1142
1143 /* wait for at least 2000us */
1144 usleep_range(2000, 2500);
1145
1146 /* write zeroes to Link Change Request */
1147 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1148 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1149
1150 /* pool until Link State change to ON */
1151 timeout = jiffies + msecs_to_jiffies(100);
1152
1153 while (!(time_after(jiffies, timeout))) {
1154 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1155
1156 /* in HS, means ON */
1157 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1158 break;
1159 }
1160
1161 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1162 dev_err(dwc->dev, "failed to send remote wakeup\n");
1163 ret = -EINVAL;
1164 }
1165
1166 out:
1167 spin_unlock_irqrestore(&dwc->lock, flags);
1168
1169 return ret;
1170 }
1171
1172 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1173 int is_selfpowered)
1174 {
1175 struct dwc3 *dwc = gadget_to_dwc(g);
1176
1177 dwc->is_selfpowered = !!is_selfpowered;
1178
1179 return 0;
1180 }
1181
1182 static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1183 {
1184 u32 reg;
1185 u32 timeout = 500;
1186
1187 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1188 if (is_on)
1189 reg |= DWC3_DCTL_RUN_STOP;
1190 else
1191 reg &= ~DWC3_DCTL_RUN_STOP;
1192
1193 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1194
1195 do {
1196 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1197 if (is_on) {
1198 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1199 break;
1200 } else {
1201 if (reg & DWC3_DSTS_DEVCTRLHLT)
1202 break;
1203 }
1204 timeout--;
1205 if (!timeout)
1206 break;
1207 udelay(1);
1208 } while (1);
1209
1210 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1211 dwc->gadget_driver
1212 ? dwc->gadget_driver->function : "no-function",
1213 is_on ? "connect" : "disconnect");
1214 }
1215
1216 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1217 {
1218 struct dwc3 *dwc = gadget_to_dwc(g);
1219 unsigned long flags;
1220
1221 is_on = !!is_on;
1222
1223 spin_lock_irqsave(&dwc->lock, flags);
1224 dwc3_gadget_run_stop(dwc, is_on);
1225 spin_unlock_irqrestore(&dwc->lock, flags);
1226
1227 return 0;
1228 }
1229
1230 static int dwc3_gadget_start(struct usb_gadget *g,
1231 struct usb_gadget_driver *driver)
1232 {
1233 struct dwc3 *dwc = gadget_to_dwc(g);
1234 struct dwc3_ep *dep;
1235 unsigned long flags;
1236 int ret = 0;
1237 u32 reg;
1238
1239 spin_lock_irqsave(&dwc->lock, flags);
1240
1241 if (dwc->gadget_driver) {
1242 dev_err(dwc->dev, "%s is already bound to %s\n",
1243 dwc->gadget.name,
1244 dwc->gadget_driver->driver.name);
1245 ret = -EBUSY;
1246 goto err0;
1247 }
1248
1249 dwc->gadget_driver = driver;
1250 dwc->gadget.dev.driver = &driver->driver;
1251
1252 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1253 reg &= ~(DWC3_DCFG_SPEED_MASK);
1254 reg |= dwc->maximum_speed;
1255 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1256
1257 dwc->start_config_issued = false;
1258
1259 /* Start with SuperSpeed Default */
1260 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1261
1262 dep = dwc->eps[0];
1263 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1264 if (ret) {
1265 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1266 goto err0;
1267 }
1268
1269 dep = dwc->eps[1];
1270 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1271 if (ret) {
1272 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1273 goto err1;
1274 }
1275
1276 /* begin to receive SETUP packets */
1277 dwc->ep0state = EP0_SETUP_PHASE;
1278 dwc3_ep0_out_start(dwc);
1279
1280 spin_unlock_irqrestore(&dwc->lock, flags);
1281
1282 return 0;
1283
1284 err1:
1285 __dwc3_gadget_ep_disable(dwc->eps[0]);
1286
1287 err0:
1288 spin_unlock_irqrestore(&dwc->lock, flags);
1289
1290 return ret;
1291 }
1292
1293 static int dwc3_gadget_stop(struct usb_gadget *g,
1294 struct usb_gadget_driver *driver)
1295 {
1296 struct dwc3 *dwc = gadget_to_dwc(g);
1297 unsigned long flags;
1298
1299 spin_lock_irqsave(&dwc->lock, flags);
1300
1301 __dwc3_gadget_ep_disable(dwc->eps[0]);
1302 __dwc3_gadget_ep_disable(dwc->eps[1]);
1303
1304 dwc->gadget_driver = NULL;
1305 dwc->gadget.dev.driver = NULL;
1306
1307 spin_unlock_irqrestore(&dwc->lock, flags);
1308
1309 return 0;
1310 }
1311 static const struct usb_gadget_ops dwc3_gadget_ops = {
1312 .get_frame = dwc3_gadget_get_frame,
1313 .wakeup = dwc3_gadget_wakeup,
1314 .set_selfpowered = dwc3_gadget_set_selfpowered,
1315 .pullup = dwc3_gadget_pullup,
1316 .udc_start = dwc3_gadget_start,
1317 .udc_stop = dwc3_gadget_stop,
1318 };
1319
1320 /* -------------------------------------------------------------------------- */
1321
1322 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1323 {
1324 struct dwc3_ep *dep;
1325 u8 epnum;
1326
1327 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1328
1329 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1330 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1331 if (!dep) {
1332 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1333 epnum);
1334 return -ENOMEM;
1335 }
1336
1337 dep->dwc = dwc;
1338 dep->number = epnum;
1339 dwc->eps[epnum] = dep;
1340
1341 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1342 (epnum & 1) ? "in" : "out");
1343 dep->endpoint.name = dep->name;
1344 dep->direction = (epnum & 1);
1345
1346 if (epnum == 0 || epnum == 1) {
1347 dep->endpoint.maxpacket = 512;
1348 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1349 if (!epnum)
1350 dwc->gadget.ep0 = &dep->endpoint;
1351 } else {
1352 int ret;
1353
1354 dep->endpoint.maxpacket = 1024;
1355 dep->endpoint.max_streams = 15;
1356 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1357 list_add_tail(&dep->endpoint.ep_list,
1358 &dwc->gadget.ep_list);
1359
1360 ret = dwc3_alloc_trb_pool(dep);
1361 if (ret)
1362 return ret;
1363 }
1364
1365 INIT_LIST_HEAD(&dep->request_list);
1366 INIT_LIST_HEAD(&dep->req_queued);
1367 }
1368
1369 return 0;
1370 }
1371
1372 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1373 {
1374 struct dwc3_ep *dep;
1375 u8 epnum;
1376
1377 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1378 dep = dwc->eps[epnum];
1379 dwc3_free_trb_pool(dep);
1380
1381 if (epnum != 0 && epnum != 1)
1382 list_del(&dep->endpoint.ep_list);
1383
1384 kfree(dep);
1385 }
1386 }
1387
1388 static void dwc3_gadget_release(struct device *dev)
1389 {
1390 dev_dbg(dev, "%s\n", __func__);
1391 }
1392
1393 /* -------------------------------------------------------------------------- */
1394 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1395 const struct dwc3_event_depevt *event, int status)
1396 {
1397 struct dwc3_request *req;
1398 struct dwc3_trb trb;
1399 unsigned int count;
1400 unsigned int s_pkt = 0;
1401
1402 do {
1403 req = next_request(&dep->req_queued);
1404 if (!req) {
1405 WARN_ON_ONCE(1);
1406 return 1;
1407 }
1408
1409 dwc3_trb_to_nat(req->trb, &trb);
1410
1411 if (trb.hwo && status != -ESHUTDOWN)
1412 /*
1413 * We continue despite the error. There is not much we
1414 * can do. If we don't clean in up we loop for ever. If
1415 * we skip the TRB than it gets overwritten reused after
1416 * a while since we use them in a ring buffer. a BUG()
1417 * would help. Lets hope that if this occures, someone
1418 * fixes the root cause instead of looking away :)
1419 */
1420 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1421 dep->name, req->trb);
1422 count = trb.length;
1423
1424 if (dep->direction) {
1425 if (count) {
1426 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1427 dep->name);
1428 status = -ECONNRESET;
1429 }
1430 } else {
1431 if (count && (event->status & DEPEVT_STATUS_SHORT))
1432 s_pkt = 1;
1433 }
1434
1435 /*
1436 * We assume here we will always receive the entire data block
1437 * which we should receive. Meaning, if we program RX to
1438 * receive 4K but we receive only 2K, we assume that's all we
1439 * should receive and we simply bounce the request back to the
1440 * gadget driver for further processing.
1441 */
1442 req->request.actual += req->request.length - count;
1443 dwc3_gadget_giveback(dep, req, status);
1444 if (s_pkt)
1445 break;
1446 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1447 break;
1448 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1449 break;
1450 } while (1);
1451
1452 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1453 return 0;
1454 return 1;
1455 }
1456
1457 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1458 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1459 int start_new)
1460 {
1461 unsigned status = 0;
1462 int clean_busy;
1463
1464 if (event->status & DEPEVT_STATUS_BUSERR)
1465 status = -ECONNRESET;
1466
1467 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1468 if (clean_busy) {
1469 dep->flags &= ~DWC3_EP_BUSY;
1470 dep->res_trans_idx = 0;
1471 }
1472
1473 /*
1474 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1475 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1476 */
1477 if (dwc->revision < DWC3_REVISION_183A) {
1478 u32 reg;
1479 int i;
1480
1481 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1482 struct dwc3_ep *dep = dwc->eps[i];
1483
1484 if (!(dep->flags & DWC3_EP_ENABLED))
1485 continue;
1486
1487 if (!list_empty(&dep->req_queued))
1488 return;
1489 }
1490
1491 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1492 reg |= dwc->u1u2;
1493 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1494
1495 dwc->u1u2 = 0;
1496 }
1497 }
1498
1499 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1500 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1501 {
1502 u32 uf, mask;
1503
1504 if (list_empty(&dep->request_list)) {
1505 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1506 dep->name);
1507 return;
1508 }
1509
1510 mask = ~(dep->interval - 1);
1511 uf = event->parameters & mask;
1512 /* 4 micro frames in the future */
1513 uf += dep->interval * 4;
1514
1515 __dwc3_gadget_kick_transfer(dep, uf, 1);
1516 }
1517
1518 static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1519 const struct dwc3_event_depevt *event)
1520 {
1521 struct dwc3 *dwc = dep->dwc;
1522 struct dwc3_event_depevt mod_ev = *event;
1523
1524 /*
1525 * We were asked to remove one requests. It is possible that this
1526 * request and a few other were started together and have the same
1527 * transfer index. Since we stopped the complete endpoint we don't
1528 * know how many requests were already completed (and not yet)
1529 * reported and how could be done (later). We purge them all until
1530 * the end of the list.
1531 */
1532 mod_ev.status = DEPEVT_STATUS_LST;
1533 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1534 dep->flags &= ~DWC3_EP_BUSY;
1535 /* pending requets are ignored and are queued on XferNotReady */
1536 }
1537
1538 static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1539 const struct dwc3_event_depevt *event)
1540 {
1541 u32 param = event->parameters;
1542 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1543
1544 switch (cmd_type) {
1545 case DWC3_DEPCMD_ENDTRANSFER:
1546 dwc3_process_ep_cmd_complete(dep, event);
1547 break;
1548 case DWC3_DEPCMD_STARTTRANSFER:
1549 dep->res_trans_idx = param & 0x7f;
1550 break;
1551 default:
1552 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1553 __func__, cmd_type);
1554 break;
1555 };
1556 }
1557
1558 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1559 const struct dwc3_event_depevt *event)
1560 {
1561 struct dwc3_ep *dep;
1562 u8 epnum = event->endpoint_number;
1563
1564 dep = dwc->eps[epnum];
1565
1566 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1567 dwc3_ep_event_string(event->endpoint_event));
1568
1569 if (epnum == 0 || epnum == 1) {
1570 dwc3_ep0_interrupt(dwc, event);
1571 return;
1572 }
1573
1574 switch (event->endpoint_event) {
1575 case DWC3_DEPEVT_XFERCOMPLETE:
1576 if (usb_endpoint_xfer_isoc(dep->desc)) {
1577 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1578 dep->name);
1579 return;
1580 }
1581
1582 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1583 break;
1584 case DWC3_DEPEVT_XFERINPROGRESS:
1585 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1586 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1587 dep->name);
1588 return;
1589 }
1590
1591 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1592 break;
1593 case DWC3_DEPEVT_XFERNOTREADY:
1594 if (usb_endpoint_xfer_isoc(dep->desc)) {
1595 dwc3_gadget_start_isoc(dwc, dep, event);
1596 } else {
1597 int ret;
1598
1599 dev_vdbg(dwc->dev, "%s: reason %s\n",
1600 dep->name, event->status
1601 ? "Transfer Active"
1602 : "Transfer Not Active");
1603
1604 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1605 if (!ret || ret == -EBUSY)
1606 return;
1607
1608 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1609 dep->name);
1610 }
1611
1612 break;
1613 case DWC3_DEPEVT_STREAMEVT:
1614 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1615 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1616 dep->name);
1617 return;
1618 }
1619
1620 switch (event->status) {
1621 case DEPEVT_STREAMEVT_FOUND:
1622 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1623 event->parameters);
1624
1625 break;
1626 case DEPEVT_STREAMEVT_NOTFOUND:
1627 /* FALLTHROUGH */
1628 default:
1629 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1630 }
1631 break;
1632 case DWC3_DEPEVT_RXTXFIFOEVT:
1633 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1634 break;
1635 case DWC3_DEPEVT_EPCMDCMPLT:
1636 dwc3_ep_cmd_compl(dep, event);
1637 break;
1638 }
1639 }
1640
1641 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1642 {
1643 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1644 spin_unlock(&dwc->lock);
1645 dwc->gadget_driver->disconnect(&dwc->gadget);
1646 spin_lock(&dwc->lock);
1647 }
1648 }
1649
1650 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1651 {
1652 struct dwc3_ep *dep;
1653 struct dwc3_gadget_ep_cmd_params params;
1654 u32 cmd;
1655 int ret;
1656
1657 dep = dwc->eps[epnum];
1658
1659 WARN_ON(!dep->res_trans_idx);
1660 if (dep->res_trans_idx) {
1661 cmd = DWC3_DEPCMD_ENDTRANSFER;
1662 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1663 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1664 memset(&params, 0, sizeof(params));
1665 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1666 WARN_ON_ONCE(ret);
1667 dep->res_trans_idx = 0;
1668 }
1669 }
1670
1671 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1672 {
1673 u32 epnum;
1674
1675 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1676 struct dwc3_ep *dep;
1677
1678 dep = dwc->eps[epnum];
1679 if (!(dep->flags & DWC3_EP_ENABLED))
1680 continue;
1681
1682 dwc3_remove_requests(dwc, dep);
1683 }
1684 }
1685
1686 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1687 {
1688 u32 epnum;
1689
1690 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1691 struct dwc3_ep *dep;
1692 struct dwc3_gadget_ep_cmd_params params;
1693 int ret;
1694
1695 dep = dwc->eps[epnum];
1696
1697 if (!(dep->flags & DWC3_EP_STALL))
1698 continue;
1699
1700 dep->flags &= ~DWC3_EP_STALL;
1701
1702 memset(&params, 0, sizeof(params));
1703 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1704 DWC3_DEPCMD_CLEARSTALL, &params);
1705 WARN_ON_ONCE(ret);
1706 }
1707 }
1708
1709 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1710 {
1711 dev_vdbg(dwc->dev, "%s\n", __func__);
1712 #if 0
1713 XXX
1714 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1715 enable it before we can disable it.
1716
1717 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1718 reg &= ~DWC3_DCTL_INITU1ENA;
1719 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1720
1721 reg &= ~DWC3_DCTL_INITU2ENA;
1722 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1723 #endif
1724
1725 dwc3_stop_active_transfers(dwc);
1726 dwc3_disconnect_gadget(dwc);
1727 dwc->start_config_issued = false;
1728
1729 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1730 dwc->setup_packet_pending = false;
1731 }
1732
1733 static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1734 {
1735 u32 reg;
1736
1737 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1738
1739 if (on)
1740 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1741 else
1742 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1743
1744 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1745 }
1746
1747 static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1748 {
1749 u32 reg;
1750
1751 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1752
1753 if (on)
1754 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1755 else
1756 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1757
1758 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1759 }
1760
1761 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1762 {
1763 u32 reg;
1764
1765 dev_vdbg(dwc->dev, "%s\n", __func__);
1766
1767 /*
1768 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1769 * would cause a missing Disconnect Event if there's a
1770 * pending Setup Packet in the FIFO.
1771 *
1772 * There's no suggested workaround on the official Bug
1773 * report, which states that "unless the driver/application
1774 * is doing any special handling of a disconnect event,
1775 * there is no functional issue".
1776 *
1777 * Unfortunately, it turns out that we _do_ some special
1778 * handling of a disconnect event, namely complete all
1779 * pending transfers, notify gadget driver of the
1780 * disconnection, and so on.
1781 *
1782 * Our suggested workaround is to follow the Disconnect
1783 * Event steps here, instead, based on a setup_packet_pending
1784 * flag. Such flag gets set whenever we have a XferNotReady
1785 * event on EP0 and gets cleared on XferComplete for the
1786 * same endpoint.
1787 *
1788 * Refers to:
1789 *
1790 * STAR#9000466709: RTL: Device : Disconnect event not
1791 * generated if setup packet pending in FIFO
1792 */
1793 if (dwc->revision < DWC3_REVISION_188A) {
1794 if (dwc->setup_packet_pending)
1795 dwc3_gadget_disconnect_interrupt(dwc);
1796 }
1797
1798 /* after reset -> Default State */
1799 dwc->dev_state = DWC3_DEFAULT_STATE;
1800
1801 /* Enable PHYs */
1802 dwc3_gadget_usb2_phy_power(dwc, true);
1803 dwc3_gadget_usb3_phy_power(dwc, true);
1804
1805 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1806 dwc3_disconnect_gadget(dwc);
1807
1808 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1809 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1810 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1811
1812 dwc3_stop_active_transfers(dwc);
1813 dwc3_clear_stall_all_ep(dwc);
1814 dwc->start_config_issued = false;
1815
1816 /* Reset device address to zero */
1817 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1818 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1819 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1820 }
1821
1822 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1823 {
1824 u32 reg;
1825 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1826
1827 /*
1828 * We change the clock only at SS but I dunno why I would want to do
1829 * this. Maybe it becomes part of the power saving plan.
1830 */
1831
1832 if (speed != DWC3_DSTS_SUPERSPEED)
1833 return;
1834
1835 /*
1836 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1837 * each time on Connect Done.
1838 */
1839 if (!usb30_clock)
1840 return;
1841
1842 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1843 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1844 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1845 }
1846
1847 static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1848 {
1849 switch (speed) {
1850 case USB_SPEED_SUPER:
1851 dwc3_gadget_usb2_phy_power(dwc, false);
1852 break;
1853 case USB_SPEED_HIGH:
1854 case USB_SPEED_FULL:
1855 case USB_SPEED_LOW:
1856 dwc3_gadget_usb3_phy_power(dwc, false);
1857 break;
1858 }
1859 }
1860
1861 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1862 {
1863 struct dwc3_gadget_ep_cmd_params params;
1864 struct dwc3_ep *dep;
1865 int ret;
1866 u32 reg;
1867 u8 speed;
1868
1869 dev_vdbg(dwc->dev, "%s\n", __func__);
1870
1871 memset(&params, 0x00, sizeof(params));
1872
1873 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1874 speed = reg & DWC3_DSTS_CONNECTSPD;
1875 dwc->speed = speed;
1876
1877 dwc3_update_ram_clk_sel(dwc, speed);
1878
1879 switch (speed) {
1880 case DWC3_DCFG_SUPERSPEED:
1881 /*
1882 * WORKAROUND: DWC3 revisions <1.90a have an issue which
1883 * would cause a missing USB3 Reset event.
1884 *
1885 * In such situations, we should force a USB3 Reset
1886 * event by calling our dwc3_gadget_reset_interrupt()
1887 * routine.
1888 *
1889 * Refers to:
1890 *
1891 * STAR#9000483510: RTL: SS : USB3 reset event may
1892 * not be generated always when the link enters poll
1893 */
1894 if (dwc->revision < DWC3_REVISION_190A)
1895 dwc3_gadget_reset_interrupt(dwc);
1896
1897 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1898 dwc->gadget.ep0->maxpacket = 512;
1899 dwc->gadget.speed = USB_SPEED_SUPER;
1900 break;
1901 case DWC3_DCFG_HIGHSPEED:
1902 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1903 dwc->gadget.ep0->maxpacket = 64;
1904 dwc->gadget.speed = USB_SPEED_HIGH;
1905 break;
1906 case DWC3_DCFG_FULLSPEED2:
1907 case DWC3_DCFG_FULLSPEED1:
1908 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1909 dwc->gadget.ep0->maxpacket = 64;
1910 dwc->gadget.speed = USB_SPEED_FULL;
1911 break;
1912 case DWC3_DCFG_LOWSPEED:
1913 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1914 dwc->gadget.ep0->maxpacket = 8;
1915 dwc->gadget.speed = USB_SPEED_LOW;
1916 break;
1917 }
1918
1919 /* Disable unneded PHY */
1920 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1921
1922 dep = dwc->eps[0];
1923 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1924 if (ret) {
1925 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1926 return;
1927 }
1928
1929 dep = dwc->eps[1];
1930 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1931 if (ret) {
1932 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1933 return;
1934 }
1935
1936 /*
1937 * Configure PHY via GUSB3PIPECTLn if required.
1938 *
1939 * Update GTXFIFOSIZn
1940 *
1941 * In both cases reset values should be sufficient.
1942 */
1943 }
1944
1945 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1946 {
1947 dev_vdbg(dwc->dev, "%s\n", __func__);
1948
1949 /*
1950 * TODO take core out of low power mode when that's
1951 * implemented.
1952 */
1953
1954 dwc->gadget_driver->resume(&dwc->gadget);
1955 }
1956
1957 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1958 unsigned int evtinfo)
1959 {
1960 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
1961
1962 /*
1963 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
1964 * on the link partner, the USB session might do multiple entry/exit
1965 * of low power states before a transfer takes place.
1966 *
1967 * Due to this problem, we might experience lower throughput. The
1968 * suggested workaround is to disable DCTL[12:9] bits if we're
1969 * transitioning from U1/U2 to U0 and enable those bits again
1970 * after a transfer completes and there are no pending transfers
1971 * on any of the enabled endpoints.
1972 *
1973 * This is the first half of that workaround.
1974 *
1975 * Refers to:
1976 *
1977 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
1978 * core send LGO_Ux entering U0
1979 */
1980 if (dwc->revision < DWC3_REVISION_183A) {
1981 if (next == DWC3_LINK_STATE_U0) {
1982 u32 u1u2;
1983 u32 reg;
1984
1985 switch (dwc->link_state) {
1986 case DWC3_LINK_STATE_U1:
1987 case DWC3_LINK_STATE_U2:
1988 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1989 u1u2 = reg & (DWC3_DCTL_INITU2ENA
1990 | DWC3_DCTL_ACCEPTU2ENA
1991 | DWC3_DCTL_INITU1ENA
1992 | DWC3_DCTL_ACCEPTU1ENA);
1993
1994 if (!dwc->u1u2)
1995 dwc->u1u2 = reg & u1u2;
1996
1997 reg &= ~u1u2;
1998
1999 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2000 break;
2001 default:
2002 /* do nothing */
2003 break;
2004 }
2005 }
2006 }
2007
2008 dwc->link_state = next;
2009
2010 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2011 }
2012
2013 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2014 const struct dwc3_event_devt *event)
2015 {
2016 switch (event->type) {
2017 case DWC3_DEVICE_EVENT_DISCONNECT:
2018 dwc3_gadget_disconnect_interrupt(dwc);
2019 break;
2020 case DWC3_DEVICE_EVENT_RESET:
2021 dwc3_gadget_reset_interrupt(dwc);
2022 break;
2023 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2024 dwc3_gadget_conndone_interrupt(dwc);
2025 break;
2026 case DWC3_DEVICE_EVENT_WAKEUP:
2027 dwc3_gadget_wakeup_interrupt(dwc);
2028 break;
2029 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2030 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2031 break;
2032 case DWC3_DEVICE_EVENT_EOPF:
2033 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2034 break;
2035 case DWC3_DEVICE_EVENT_SOF:
2036 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2037 break;
2038 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2039 dev_vdbg(dwc->dev, "Erratic Error\n");
2040 break;
2041 case DWC3_DEVICE_EVENT_CMD_CMPL:
2042 dev_vdbg(dwc->dev, "Command Complete\n");
2043 break;
2044 case DWC3_DEVICE_EVENT_OVERFLOW:
2045 dev_vdbg(dwc->dev, "Overflow\n");
2046 break;
2047 default:
2048 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2049 }
2050 }
2051
2052 static void dwc3_process_event_entry(struct dwc3 *dwc,
2053 const union dwc3_event *event)
2054 {
2055 /* Endpoint IRQ, handle it and return early */
2056 if (event->type.is_devspec == 0) {
2057 /* depevt */
2058 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2059 }
2060
2061 switch (event->type.type) {
2062 case DWC3_EVENT_TYPE_DEV:
2063 dwc3_gadget_interrupt(dwc, &event->devt);
2064 break;
2065 /* REVISIT what to do with Carkit and I2C events ? */
2066 default:
2067 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2068 }
2069 }
2070
2071 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2072 {
2073 struct dwc3_event_buffer *evt;
2074 int left;
2075 u32 count;
2076
2077 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2078 count &= DWC3_GEVNTCOUNT_MASK;
2079 if (!count)
2080 return IRQ_NONE;
2081
2082 evt = dwc->ev_buffs[buf];
2083 left = count;
2084
2085 while (left > 0) {
2086 union dwc3_event event;
2087
2088 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
2089 dwc3_process_event_entry(dwc, &event);
2090 /*
2091 * XXX we wrap around correctly to the next entry as almost all
2092 * entries are 4 bytes in size. There is one entry which has 12
2093 * bytes which is a regular entry followed by 8 bytes data. ATM
2094 * I don't know how things are organized if were get next to the
2095 * a boundary so I worry about that once we try to handle that.
2096 */
2097 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2098 left -= 4;
2099
2100 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2101 }
2102
2103 return IRQ_HANDLED;
2104 }
2105
2106 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2107 {
2108 struct dwc3 *dwc = _dwc;
2109 int i;
2110 irqreturn_t ret = IRQ_NONE;
2111
2112 spin_lock(&dwc->lock);
2113
2114 for (i = 0; i < dwc->num_event_buffers; i++) {
2115 irqreturn_t status;
2116
2117 status = dwc3_process_event_buf(dwc, i);
2118 if (status == IRQ_HANDLED)
2119 ret = status;
2120 }
2121
2122 spin_unlock(&dwc->lock);
2123
2124 return ret;
2125 }
2126
2127 /**
2128 * dwc3_gadget_init - Initializes gadget related registers
2129 * @dwc: Pointer to out controller context structure
2130 *
2131 * Returns 0 on success otherwise negative errno.
2132 */
2133 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2134 {
2135 u32 reg;
2136 int ret;
2137 int irq;
2138
2139 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2140 &dwc->ctrl_req_addr, GFP_KERNEL);
2141 if (!dwc->ctrl_req) {
2142 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2143 ret = -ENOMEM;
2144 goto err0;
2145 }
2146
2147 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2148 &dwc->ep0_trb_addr, GFP_KERNEL);
2149 if (!dwc->ep0_trb) {
2150 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2151 ret = -ENOMEM;
2152 goto err1;
2153 }
2154
2155 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
2156 sizeof(*dwc->setup_buf) * 2,
2157 &dwc->setup_buf_addr, GFP_KERNEL);
2158 if (!dwc->setup_buf) {
2159 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2160 ret = -ENOMEM;
2161 goto err2;
2162 }
2163
2164 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2165 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
2166 if (!dwc->ep0_bounce) {
2167 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2168 ret = -ENOMEM;
2169 goto err3;
2170 }
2171
2172 dev_set_name(&dwc->gadget.dev, "gadget");
2173
2174 dwc->gadget.ops = &dwc3_gadget_ops;
2175 dwc->gadget.max_speed = USB_SPEED_SUPER;
2176 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2177 dwc->gadget.dev.parent = dwc->dev;
2178 dwc->gadget.sg_supported = true;
2179
2180 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2181
2182 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2183 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2184 dwc->gadget.dev.release = dwc3_gadget_release;
2185 dwc->gadget.name = "dwc3-gadget";
2186
2187 /*
2188 * REVISIT: Here we should clear all pending IRQs to be
2189 * sure we're starting from a well known location.
2190 */
2191
2192 ret = dwc3_gadget_init_endpoints(dwc);
2193 if (ret)
2194 goto err4;
2195
2196 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2197
2198 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2199 "dwc3", dwc);
2200 if (ret) {
2201 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2202 irq, ret);
2203 goto err5;
2204 }
2205
2206 /* Enable all but Start and End of Frame IRQs */
2207 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2208 DWC3_DEVTEN_EVNTOVERFLOWEN |
2209 DWC3_DEVTEN_CMDCMPLTEN |
2210 DWC3_DEVTEN_ERRTICERREN |
2211 DWC3_DEVTEN_WKUPEVTEN |
2212 DWC3_DEVTEN_ULSTCNGEN |
2213 DWC3_DEVTEN_CONNECTDONEEN |
2214 DWC3_DEVTEN_USBRSTEN |
2215 DWC3_DEVTEN_DISCONNEVTEN);
2216 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2217
2218 ret = device_register(&dwc->gadget.dev);
2219 if (ret) {
2220 dev_err(dwc->dev, "failed to register gadget device\n");
2221 put_device(&dwc->gadget.dev);
2222 goto err6;
2223 }
2224
2225 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2226 if (ret) {
2227 dev_err(dwc->dev, "failed to register udc\n");
2228 goto err7;
2229 }
2230
2231 return 0;
2232
2233 err7:
2234 device_unregister(&dwc->gadget.dev);
2235
2236 err6:
2237 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2238 free_irq(irq, dwc);
2239
2240 err5:
2241 dwc3_gadget_free_endpoints(dwc);
2242
2243 err4:
2244 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2245 dwc->ep0_bounce_addr);
2246
2247 err3:
2248 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2249 dwc->setup_buf, dwc->setup_buf_addr);
2250
2251 err2:
2252 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2253 dwc->ep0_trb, dwc->ep0_trb_addr);
2254
2255 err1:
2256 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2257 dwc->ctrl_req, dwc->ctrl_req_addr);
2258
2259 err0:
2260 return ret;
2261 }
2262
2263 void dwc3_gadget_exit(struct dwc3 *dwc)
2264 {
2265 int irq;
2266
2267 usb_del_gadget_udc(&dwc->gadget);
2268 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2269
2270 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2271 free_irq(irq, dwc);
2272
2273 dwc3_gadget_free_endpoints(dwc);
2274
2275 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2276 dwc->ep0_bounce_addr);
2277
2278 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2279 dwc->setup_buf, dwc->setup_buf_addr);
2280
2281 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2282 dwc->ep0_trb, dwc->ep0_trb_addr);
2283
2284 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2285 dwc->ctrl_req, dwc->ctrl_req_addr);
2286
2287 device_unregister(&dwc->gadget.dev);
2288 }