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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / video / aty / radeon_base.c
blobce1506b75adfb4c04a028498b111b497139a8dec
1 /*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53 #define RADEON_VERSION "0.2.0"
54
55 #include "radeonfb.h"
56
57 #include <linux/module.h>
58 #include <linux/moduleparam.h>
59 #include <linux/kernel.h>
60 #include <linux/errno.h>
61 #include <linux/string.h>
62 #include <linux/ctype.h>
63 #include <linux/mm.h>
64 #include <linux/slab.h>
65 #include <linux/delay.h>
66 #include <linux/time.h>
67 #include <linux/fb.h>
68 #include <linux/ioport.h>
69 #include <linux/init.h>
70 #include <linux/pci.h>
71 #include <linux/vmalloc.h>
72 #include <linux/device.h>
73
74 #include <asm/io.h>
75 #include <linux/uaccess.h>
76
77 #ifdef CONFIG_PPC_OF
78
79 #include <asm/pci-bridge.h>
80 #include "../macmodes.h"
81
82 #ifdef CONFIG_BOOTX_TEXT
83 #include <asm/btext.h>
84 #endif
85
86 #endif /* CONFIG_PPC_OF */
87
88 #ifdef CONFIG_MTRR
89 #include <asm/mtrr.h>
90 #endif
91
92 #include <video/radeon.h>
93 #include <linux/radeonfb.h>
94
95 #include "../edid.h" // MOVE THAT TO include/video
96 #include "ati_ids.h"
97
98 #define MAX_MAPPED_VRAM (2048*2048*4)
99 #define MIN_MAPPED_VRAM (1024*768*1)
100
101 #define CHIP_DEF(id, family, flags) \
102 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
103
104 static struct pci_device_id radeonfb_pci_table[] = {
105 /* Radeon Xpress 200m */
106 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
107 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
108 /* Mobility M6 */
109 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
110 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
111 /* Radeon VE/7000 */
112 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
113 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
114 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
115 /* Radeon IGP320M (U1) */
116 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* Radeon IGP320 (A3) */
118 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* IGP330M/340M/350M (U2) */
120 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121 /* IGP330/340/350 (A4) */
122 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123 /* Mobility 7000 IGP */
124 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
125 /* 7000 IGP (A4+) */
126 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
127 /* 8500 AIW */
128 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
130 /* 8700/8800 */
131 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
132 /* 8500 */
133 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
134 /* 9100 */
135 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
136 /* Mobility M7 */
137 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
138 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 /* 7500 */
140 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
141 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
142 /* Mobility M9 */
143 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 /* 9000/Pro */
148 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
149 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
150
151 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
152 /* Mobility 9100 IGP (U3) */
153 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
155 /* 9100 IGP (A5) */
156 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
158 /* Mobility 9200 (M9+) */
159 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
161 /* 9200 */
162 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
165 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
166 /* 9500 */
167 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
169 /* 9600TX / FireGL Z1 */
170 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
172 /* 9700/9500/Pro/FireGL X1 */
173 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
176 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
177 /* Mobility M10/M11 */
178 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
184 /* 9600/FireGL T2 */
185 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
191 /* 9800/Pro/FileGL X2 */
192 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
200 /* Newer stuff */
201 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
205 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
212 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
219 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
226 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
227 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
228 /* Original Radeon/7200 */
229 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
231 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
232 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
233 { 0, }
234 };
235 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
236
237
238 typedef struct {
239 u16 reg;
240 u32 val;
241 } reg_val;
242
243
244 /* these common regs are cleared before mode setting so they do not
245 * interfere with anything
246 */
247 static reg_val common_regs[] = {
248 { OVR_CLR, 0 },
249 { OVR_WID_LEFT_RIGHT, 0 },
250 { OVR_WID_TOP_BOTTOM, 0 },
251 { OV0_SCALE_CNTL, 0 },
252 { SUBPIC_CNTL, 0 },
253 { VIPH_CONTROL, 0 },
254 { I2C_CNTL_1, 0 },
255 { GEN_INT_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 },
257 { CAP1_TRIG_CNTL, 0 },
258 };
259
260 /*
261 * globals
262 */
263
264 static char *mode_option;
265 static char *monitor_layout;
266 static bool noaccel = 0;
267 static int default_dynclk = -2;
268 static bool nomodeset = 0;
269 static bool ignore_edid = 0;
270 static bool mirror = 0;
271 static int panel_yres = 0;
272 static bool force_dfp = 0;
273 static bool force_measure_pll = 0;
274 #ifdef CONFIG_MTRR
275 static bool nomtrr = 0;
276 #endif
277 static bool force_sleep;
278 static bool ignore_devlist;
279 #ifdef CONFIG_PMAC_BACKLIGHT
280 static int backlight = 1;
281 #else
282 static int backlight = 0;
283 #endif
284
285 /*
286 * prototypes
287 */
288
289 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
290 {
291 if (!rinfo->bios_seg)
292 return;
293 pci_unmap_rom(dev, rinfo->bios_seg);
294 }
295
296 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
297 {
298 void __iomem *rom;
299 u16 dptr;
300 u8 rom_type;
301 size_t rom_size;
302
303 /* If this is a primary card, there is a shadow copy of the
304 * ROM somewhere in the first meg. We will just ignore the copy
305 * and use the ROM directly.
306 */
307
308 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
309 unsigned int temp;
310 temp = INREG(MPP_TB_CONFIG);
311 temp &= 0x00ffffffu;
312 temp |= 0x04 << 24;
313 OUTREG(MPP_TB_CONFIG, temp);
314 temp = INREG(MPP_TB_CONFIG);
315
316 rom = pci_map_rom(dev, &rom_size);
317 if (!rom) {
318 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
319 pci_name(rinfo->pdev));
320 return -ENOMEM;
321 }
322
323 rinfo->bios_seg = rom;
324
325 /* Very simple test to make sure it appeared */
326 if (BIOS_IN16(0) != 0xaa55) {
327 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
328 "should be 0xaa55\n",
329 pci_name(rinfo->pdev), BIOS_IN16(0));
330 goto failed;
331 }
332 /* Look for the PCI data to check the ROM type */
333 dptr = BIOS_IN16(0x18);
334
335 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
336 * for now, until I've verified this works everywhere. The goal here is more
337 * to phase out Open Firmware images.
338 *
339 * Currently, we only look at the first PCI data, we could iteratre and deal with
340 * them all, and we should use fb_bios_start relative to start of image and not
341 * relative start of ROM, but so far, I never found a dual-image ATI card
342 *
343 * typedef struct {
344 * u32 signature; + 0x00
345 * u16 vendor; + 0x04
346 * u16 device; + 0x06
347 * u16 reserved_1; + 0x08
348 * u16 dlen; + 0x0a
349 * u8 drevision; + 0x0c
350 * u8 class_hi; + 0x0d
351 * u16 class_lo; + 0x0e
352 * u16 ilen; + 0x10
353 * u16 irevision; + 0x12
354 * u8 type; + 0x14
355 * u8 indicator; + 0x15
356 * u16 reserved_2; + 0x16
357 * } pci_data_t;
358 */
359 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
360 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
361 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
362 goto anyway;
363 }
364 rom_type = BIOS_IN8(dptr + 0x14);
365 switch(rom_type) {
366 case 0:
367 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
368 break;
369 case 1:
370 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
371 goto failed;
372 case 2:
373 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
374 goto failed;
375 default:
376 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
377 goto failed;
378 }
379 anyway:
380 /* Locate the flat panel infos, do some sanity checking !!! */
381 rinfo->fp_bios_start = BIOS_IN16(0x48);
382 return 0;
383
384 failed:
385 rinfo->bios_seg = NULL;
386 radeon_unmap_ROM(rinfo, dev);
387 return -ENXIO;
388 }
389
390 #ifdef CONFIG_X86
391 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
392 {
393 /* I simplified this code as we used to miss the signatures in
394 * a lot of case. It's now closer to XFree, we just don't check
395 * for signatures at all... Something better will have to be done
396 * if we end up having conflicts
397 */
398 u32 segstart;
399 void __iomem *rom_base = NULL;
400
401 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
402 rom_base = ioremap(segstart, 0x10000);
403 if (rom_base == NULL)
404 return -ENOMEM;
405 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
406 break;
407 iounmap(rom_base);
408 rom_base = NULL;
409 }
410 if (rom_base == NULL)
411 return -ENXIO;
412
413 /* Locate the flat panel infos, do some sanity checking !!! */
414 rinfo->bios_seg = rom_base;
415 rinfo->fp_bios_start = BIOS_IN16(0x48);
416
417 return 0;
418 }
419 #endif
420
421 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
422 /*
423 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
424 * tree. Hopefully, ATI OF driver is kind enough to fill these
425 */
426 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
427 {
428 struct device_node *dp = rinfo->of_node;
429 const u32 *val;
430
431 if (dp == NULL)
432 return -ENODEV;
433 val = of_get_property(dp, "ATY,RefCLK", NULL);
434 if (!val || !*val) {
435 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
436 return -EINVAL;
437 }
438
439 rinfo->pll.ref_clk = (*val) / 10;
440
441 val = of_get_property(dp, "ATY,SCLK", NULL);
442 if (val && *val)
443 rinfo->pll.sclk = (*val) / 10;
444
445 val = of_get_property(dp, "ATY,MCLK", NULL);
446 if (val && *val)
447 rinfo->pll.mclk = (*val) / 10;
448
449 return 0;
450 }
451 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
452
453 /*
454 * Read PLL infos from chip registers
455 */
456 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
457 {
458 unsigned char ppll_div_sel;
459 unsigned Ns, Nm, M;
460 unsigned sclk, mclk, tmp, ref_div;
461 int hTotal, vTotal, num, denom, m, n;
462 unsigned long long hz, vclk;
463 long xtal;
464 struct timeval start_tv, stop_tv;
465 long total_secs, total_usecs;
466 int i;
467
468 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
469 * here, so... --BenH
470 */
471
472 /* Flush PCI buffers ? */
473 tmp = INREG16(DEVICE_ID);
474
475 local_irq_disable();
476
477 for(i=0; i<1000000; i++)
478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
479 break;
480
481 do_gettimeofday(&start_tv);
482
483 for(i=0; i<1000000; i++)
484 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
485 break;
486
487 for(i=0; i<1000000; i++)
488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
489 break;
490
491 do_gettimeofday(&stop_tv);
492
493 local_irq_enable();
494
495 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
496 if (total_secs > 10)
497 return -1;
498 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
499 total_usecs += total_secs * 1000000;
500 if (total_usecs < 0)
501 total_usecs = -total_usecs;
502 hz = 1000000/total_usecs;
503
504 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
505 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
506 vclk = (long long)hTotal * (long long)vTotal * hz;
507
508 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
509 case 0:
510 default:
511 num = 1;
512 denom = 1;
513 break;
514 case 1:
515 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
516 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
517 num = 2*n;
518 denom = 2*m;
519 break;
520 case 2:
521 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
522 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
523 num = 2*n;
524 denom = 2*m;
525 break;
526 }
527
528 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
529 radeon_pll_errata_after_index(rinfo);
530
531 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
532 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
533
534 num *= n;
535 denom *= m;
536
537 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
538 case 1:
539 denom *= 2;
540 break;
541 case 2:
542 denom *= 4;
543 break;
544 case 3:
545 denom *= 8;
546 break;
547 case 4:
548 denom *= 3;
549 break;
550 case 6:
551 denom *= 6;
552 break;
553 case 7:
554 denom *= 12;
555 break;
556 }
557
558 vclk *= denom;
559 do_div(vclk, 1000 * num);
560 xtal = vclk;
561
562 if ((xtal > 26900) && (xtal < 27100))
563 xtal = 2700;
564 else if ((xtal > 14200) && (xtal < 14400))
565 xtal = 1432;
566 else if ((xtal > 29400) && (xtal < 29600))
567 xtal = 2950;
568 else {
569 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
570 return -1;
571 }
572
573 tmp = INPLL(M_SPLL_REF_FB_DIV);
574 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
575
576 Ns = (tmp & 0xff0000) >> 16;
577 Nm = (tmp & 0xff00) >> 8;
578 M = (tmp & 0xff);
579 sclk = round_div((2 * Ns * xtal), (2 * M));
580 mclk = round_div((2 * Nm * xtal), (2 * M));
581
582 /* we're done, hopefully these are sane values */
583 rinfo->pll.ref_clk = xtal;
584 rinfo->pll.ref_div = ref_div;
585 rinfo->pll.sclk = sclk;
586 rinfo->pll.mclk = mclk;
587
588 return 0;
589 }
590
591 /*
592 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
593 */
594 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
595 {
596 /*
597 * In the case nothing works, these are defaults; they are mostly
598 * incomplete, however. It does provide ppll_max and _min values
599 * even for most other methods, however.
600 */
601 switch (rinfo->chipset) {
602 case PCI_DEVICE_ID_ATI_RADEON_QW:
603 case PCI_DEVICE_ID_ATI_RADEON_QX:
604 rinfo->pll.ppll_max = 35000;
605 rinfo->pll.ppll_min = 12000;
606 rinfo->pll.mclk = 23000;
607 rinfo->pll.sclk = 23000;
608 rinfo->pll.ref_clk = 2700;
609 break;
610 case PCI_DEVICE_ID_ATI_RADEON_QL:
611 case PCI_DEVICE_ID_ATI_RADEON_QN:
612 case PCI_DEVICE_ID_ATI_RADEON_QO:
613 case PCI_DEVICE_ID_ATI_RADEON_Ql:
614 case PCI_DEVICE_ID_ATI_RADEON_BB:
615 rinfo->pll.ppll_max = 35000;
616 rinfo->pll.ppll_min = 12000;
617 rinfo->pll.mclk = 27500;
618 rinfo->pll.sclk = 27500;
619 rinfo->pll.ref_clk = 2700;
620 break;
621 case PCI_DEVICE_ID_ATI_RADEON_Id:
622 case PCI_DEVICE_ID_ATI_RADEON_Ie:
623 case PCI_DEVICE_ID_ATI_RADEON_If:
624 case PCI_DEVICE_ID_ATI_RADEON_Ig:
625 rinfo->pll.ppll_max = 35000;
626 rinfo->pll.ppll_min = 12000;
627 rinfo->pll.mclk = 25000;
628 rinfo->pll.sclk = 25000;
629 rinfo->pll.ref_clk = 2700;
630 break;
631 case PCI_DEVICE_ID_ATI_RADEON_ND:
632 case PCI_DEVICE_ID_ATI_RADEON_NE:
633 case PCI_DEVICE_ID_ATI_RADEON_NF:
634 case PCI_DEVICE_ID_ATI_RADEON_NG:
635 rinfo->pll.ppll_max = 40000;
636 rinfo->pll.ppll_min = 20000;
637 rinfo->pll.mclk = 27000;
638 rinfo->pll.sclk = 27000;
639 rinfo->pll.ref_clk = 2700;
640 break;
641 case PCI_DEVICE_ID_ATI_RADEON_QD:
642 case PCI_DEVICE_ID_ATI_RADEON_QE:
643 case PCI_DEVICE_ID_ATI_RADEON_QF:
644 case PCI_DEVICE_ID_ATI_RADEON_QG:
645 default:
646 rinfo->pll.ppll_max = 35000;
647 rinfo->pll.ppll_min = 12000;
648 rinfo->pll.mclk = 16600;
649 rinfo->pll.sclk = 16600;
650 rinfo->pll.ref_clk = 2700;
651 break;
652 }
653 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
654
655
656 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
657 /*
658 * Retrieve PLL infos from Open Firmware first
659 */
660 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
661 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
662 goto found;
663 }
664 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
665
666 /*
667 * Check out if we have an X86 which gave us some PLL informations
668 * and if yes, retrieve them
669 */
670 if (!force_measure_pll && rinfo->bios_seg) {
671 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
672
673 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
674 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
675 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
676 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
677 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
678 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
679
680 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
681 goto found;
682 }
683
684 /*
685 * We didn't get PLL parameters from either OF or BIOS, we try to
686 * probe them
687 */
688 if (radeon_probe_pll_params(rinfo) == 0) {
689 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
690 goto found;
691 }
692
693 /*
694 * Fall back to already-set defaults...
695 */
696 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
697
698 found:
699 /*
700 * Some methods fail to retrieve SCLK and MCLK values, we apply default
701 * settings in this case (200Mhz). If that really happens often, we
702 * could fetch from registers instead...
703 */
704 if (rinfo->pll.mclk == 0)
705 rinfo->pll.mclk = 20000;
706 if (rinfo->pll.sclk == 0)
707 rinfo->pll.sclk = 20000;
708
709 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
710 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
711 rinfo->pll.ref_div,
712 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
713 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
714 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
715 }
716
717 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
718 {
719 struct radeonfb_info *rinfo = info->par;
720 struct fb_var_screeninfo v;
721 int nom, den;
722 unsigned int pitch;
723
724 if (radeon_match_mode(rinfo, &v, var))
725 return -EINVAL;
726
727 switch (v.bits_per_pixel) {
728 case 0 ... 8:
729 v.bits_per_pixel = 8;
730 break;
731 case 9 ... 16:
732 v.bits_per_pixel = 16;
733 break;
734 case 17 ... 24:
735 #if 0 /* Doesn't seem to work */
736 v.bits_per_pixel = 24;
737 break;
738 #endif
739 return -EINVAL;
740 case 25 ... 32:
741 v.bits_per_pixel = 32;
742 break;
743 default:
744 return -EINVAL;
745 }
746
747 switch (var_to_depth(&v)) {
748 case 8:
749 nom = den = 1;
750 v.red.offset = v.green.offset = v.blue.offset = 0;
751 v.red.length = v.green.length = v.blue.length = 8;
752 v.transp.offset = v.transp.length = 0;
753 break;
754 case 15:
755 nom = 2;
756 den = 1;
757 v.red.offset = 10;
758 v.green.offset = 5;
759 v.blue.offset = 0;
760 v.red.length = v.green.length = v.blue.length = 5;
761 v.transp.offset = v.transp.length = 0;
762 break;
763 case 16:
764 nom = 2;
765 den = 1;
766 v.red.offset = 11;
767 v.green.offset = 5;
768 v.blue.offset = 0;
769 v.red.length = 5;
770 v.green.length = 6;
771 v.blue.length = 5;
772 v.transp.offset = v.transp.length = 0;
773 break;
774 case 24:
775 nom = 4;
776 den = 1;
777 v.red.offset = 16;
778 v.green.offset = 8;
779 v.blue.offset = 0;
780 v.red.length = v.blue.length = v.green.length = 8;
781 v.transp.offset = v.transp.length = 0;
782 break;
783 case 32:
784 nom = 4;
785 den = 1;
786 v.red.offset = 16;
787 v.green.offset = 8;
788 v.blue.offset = 0;
789 v.red.length = v.blue.length = v.green.length = 8;
790 v.transp.offset = 24;
791 v.transp.length = 8;
792 break;
793 default:
794 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
795 var->xres, var->yres, var->bits_per_pixel);
796 return -EINVAL;
797 }
798
799 if (v.yres_virtual < v.yres)
800 v.yres_virtual = v.yres;
801 if (v.xres_virtual < v.xres)
802 v.xres_virtual = v.xres;
803
804
805 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
806 * with some panels, though I don't quite like this solution
807 */
808 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
809 v.xres_virtual = v.xres_virtual & ~7ul;
810 } else {
811 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
812 & ~(0x3f)) >> 6;
813 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
814 }
815
816 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
817 return -EINVAL;
818
819 if (v.xres_virtual < v.xres)
820 v.xres = v.xres_virtual;
821
822 if (v.xoffset < 0)
823 v.xoffset = 0;
824 if (v.yoffset < 0)
825 v.yoffset = 0;
826
827 if (v.xoffset > v.xres_virtual - v.xres)
828 v.xoffset = v.xres_virtual - v.xres - 1;
829
830 if (v.yoffset > v.yres_virtual - v.yres)
831 v.yoffset = v.yres_virtual - v.yres - 1;
832
833 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
834 v.transp.offset = v.transp.length =
835 v.transp.msb_right = 0;
836
837 memcpy(var, &v, sizeof(v));
838
839 return 0;
840 }
841
842
843 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
844 struct fb_info *info)
845 {
846 struct radeonfb_info *rinfo = info->par;
847
848 if ((var->xoffset + info->var.xres > info->var.xres_virtual)
849 || (var->yoffset + info->var.yres > info->var.yres_virtual))
850 return -EINVAL;
851
852 if (rinfo->asleep)
853 return 0;
854
855 radeon_fifo_wait(2);
856 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +
857 var->xoffset * info->var.bits_per_pixel / 8) & ~7);
858 return 0;
859 }
860
861
862 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
863 unsigned long arg)
864 {
865 struct radeonfb_info *rinfo = info->par;
866 unsigned int tmp;
867 u32 value = 0;
868 int rc;
869
870 switch (cmd) {
871 /*
872 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
873 * and do something better using 2nd CRTC instead of just hackish
874 * routing to second output
875 */
876 case FBIO_RADEON_SET_MIRROR:
877 if (!rinfo->is_mobility)
878 return -EINVAL;
879
880 rc = get_user(value, (__u32 __user *)arg);
881
882 if (rc)
883 return rc;
884
885 radeon_fifo_wait(2);
886 if (value & 0x01) {
887 tmp = INREG(LVDS_GEN_CNTL);
888
889 tmp |= (LVDS_ON | LVDS_BLON);
890 } else {
891 tmp = INREG(LVDS_GEN_CNTL);
892
893 tmp &= ~(LVDS_ON | LVDS_BLON);
894 }
895
896 OUTREG(LVDS_GEN_CNTL, tmp);
897
898 if (value & 0x02) {
899 tmp = INREG(CRTC_EXT_CNTL);
900 tmp |= CRTC_CRT_ON;
901
902 mirror = 1;
903 } else {
904 tmp = INREG(CRTC_EXT_CNTL);
905 tmp &= ~CRTC_CRT_ON;
906
907 mirror = 0;
908 }
909
910 OUTREG(CRTC_EXT_CNTL, tmp);
911
912 return 0;
913 case FBIO_RADEON_GET_MIRROR:
914 if (!rinfo->is_mobility)
915 return -EINVAL;
916
917 tmp = INREG(LVDS_GEN_CNTL);
918 if ((LVDS_ON | LVDS_BLON) & tmp)
919 value |= 0x01;
920
921 tmp = INREG(CRTC_EXT_CNTL);
922 if (CRTC_CRT_ON & tmp)
923 value |= 0x02;
924
925 return put_user(value, (__u32 __user *)arg);
926 default:
927 return -EINVAL;
928 }
929
930 return -EINVAL;
931 }
932
933
934 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
935 {
936 u32 val;
937 u32 tmp_pix_clks;
938 int unblank = 0;
939
940 if (rinfo->lock_blank)
941 return 0;
942
943 radeon_engine_idle();
944
945 val = INREG(CRTC_EXT_CNTL);
946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
947 CRTC_VSYNC_DIS);
948 switch (blank) {
949 case FB_BLANK_VSYNC_SUSPEND:
950 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
951 break;
952 case FB_BLANK_HSYNC_SUSPEND:
953 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
954 break;
955 case FB_BLANK_POWERDOWN:
956 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
957 CRTC_HSYNC_DIS);
958 break;
959 case FB_BLANK_NORMAL:
960 val |= CRTC_DISPLAY_DIS;
961 break;
962 case FB_BLANK_UNBLANK:
963 default:
964 unblank = 1;
965 }
966 OUTREG(CRTC_EXT_CNTL, val);
967
968
969 switch (rinfo->mon1_type) {
970 case MT_DFP:
971 if (unblank)
972 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
973 ~(FP_FPON | FP_TMDS_EN));
974 else {
975 if (mode_switch || blank == FB_BLANK_NORMAL)
976 break;
977 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
978 }
979 break;
980 case MT_LCD:
981 del_timer_sync(&rinfo->lvds_timer);
982 val = INREG(LVDS_GEN_CNTL);
983 if (unblank) {
984 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
985 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
986 & (LVDS_DIGON | LVDS_BL_MOD_EN));
987 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
988 OUTREG(LVDS_GEN_CNTL, target_val);
989 else if ((val ^ target_val) != 0) {
990 OUTREG(LVDS_GEN_CNTL, target_val
991 & ~(LVDS_ON | LVDS_BL_MOD_EN));
992 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
993 rinfo->init_state.lvds_gen_cntl |=
994 target_val & LVDS_STATE_MASK;
995 if (mode_switch) {
996 radeon_msleep(rinfo->panel_info.pwr_delay);
997 OUTREG(LVDS_GEN_CNTL, target_val);
998 }
999 else {
1000 rinfo->pending_lvds_gen_cntl = target_val;
1001 mod_timer(&rinfo->lvds_timer,
1002 jiffies +
1003 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1004 }
1005 }
1006 } else {
1007 val |= LVDS_DISPLAY_DIS;
1008 OUTREG(LVDS_GEN_CNTL, val);
1009
1010 /* We don't do a full switch-off on a simple mode switch */
1011 if (mode_switch || blank == FB_BLANK_NORMAL)
1012 break;
1013
1014 /* Asic bug, when turning off LVDS_ON, we have to make sure
1015 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1016 */
1017 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1018 if (rinfo->is_mobility || rinfo->is_IGP)
1019 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1020 val &= ~(LVDS_BL_MOD_EN);
1021 OUTREG(LVDS_GEN_CNTL, val);
1022 udelay(100);
1023 val &= ~(LVDS_ON | LVDS_EN);
1024 OUTREG(LVDS_GEN_CNTL, val);
1025 val &= ~LVDS_DIGON;
1026 rinfo->pending_lvds_gen_cntl = val;
1027 mod_timer(&rinfo->lvds_timer,
1028 jiffies +
1029 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1030 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1031 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1032 if (rinfo->is_mobility || rinfo->is_IGP)
1033 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1034 }
1035 break;
1036 case MT_CRT:
1037 // todo: powerdown DAC
1038 default:
1039 break;
1040 }
1041
1042 return 0;
1043 }
1044
1045 static int radeonfb_blank (int blank, struct fb_info *info)
1046 {
1047 struct radeonfb_info *rinfo = info->par;
1048
1049 if (rinfo->asleep)
1050 return 0;
1051
1052 return radeon_screen_blank(rinfo, blank, 0);
1053 }
1054
1055 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1056 unsigned blue, unsigned transp,
1057 struct radeonfb_info *rinfo)
1058 {
1059 u32 pindex;
1060 unsigned int i;
1061
1062
1063 if (regno > 255)
1064 return -EINVAL;
1065
1066 red >>= 8;
1067 green >>= 8;
1068 blue >>= 8;
1069 rinfo->palette[regno].red = red;
1070 rinfo->palette[regno].green = green;
1071 rinfo->palette[regno].blue = blue;
1072
1073 /* default */
1074 pindex = regno;
1075
1076 if (!rinfo->asleep) {
1077 radeon_fifo_wait(9);
1078
1079 if (rinfo->bpp == 16) {
1080 pindex = regno * 8;
1081
1082 if (rinfo->depth == 16 && regno > 63)
1083 return -EINVAL;
1084 if (rinfo->depth == 15 && regno > 31)
1085 return -EINVAL;
1086
1087 /* For 565, the green component is mixed one order
1088 * below
1089 */
1090 if (rinfo->depth == 16) {
1091 OUTREG(PALETTE_INDEX, pindex>>1);
1092 OUTREG(PALETTE_DATA,
1093 (rinfo->palette[regno>>1].red << 16) |
1094 (green << 8) |
1095 (rinfo->palette[regno>>1].blue));
1096 green = rinfo->palette[regno<<1].green;
1097 }
1098 }
1099
1100 if (rinfo->depth != 16 || regno < 32) {
1101 OUTREG(PALETTE_INDEX, pindex);
1102 OUTREG(PALETTE_DATA, (red << 16) |
1103 (green << 8) | blue);
1104 }
1105 }
1106 if (regno < 16) {
1107 u32 *pal = rinfo->info->pseudo_palette;
1108 switch (rinfo->depth) {
1109 case 15:
1110 pal[regno] = (regno << 10) | (regno << 5) | regno;
1111 break;
1112 case 16:
1113 pal[regno] = (regno << 11) | (regno << 5) | regno;
1114 break;
1115 case 24:
1116 pal[regno] = (regno << 16) | (regno << 8) | regno;
1117 break;
1118 case 32:
1119 i = (regno << 8) | regno;
1120 pal[regno] = (i << 16) | i;
1121 break;
1122 }
1123 }
1124 return 0;
1125 }
1126
1127 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1128 unsigned blue, unsigned transp,
1129 struct fb_info *info)
1130 {
1131 struct radeonfb_info *rinfo = info->par;
1132 u32 dac_cntl2, vclk_cntl = 0;
1133 int rc;
1134
1135 if (!rinfo->asleep) {
1136 if (rinfo->is_mobility) {
1137 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1138 OUTPLL(VCLK_ECP_CNTL,
1139 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1140 }
1141
1142 /* Make sure we are on first palette */
1143 if (rinfo->has_CRTC2) {
1144 dac_cntl2 = INREG(DAC_CNTL2);
1145 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1146 OUTREG(DAC_CNTL2, dac_cntl2);
1147 }
1148 }
1149
1150 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1151
1152 if (!rinfo->asleep && rinfo->is_mobility)
1153 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1154
1155 return rc;
1156 }
1157
1158 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1159 {
1160 struct radeonfb_info *rinfo = info->par;
1161 u16 *red, *green, *blue, *transp;
1162 u32 dac_cntl2, vclk_cntl = 0;
1163 int i, start, rc = 0;
1164
1165 if (!rinfo->asleep) {
1166 if (rinfo->is_mobility) {
1167 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1168 OUTPLL(VCLK_ECP_CNTL,
1169 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1170 }
1171
1172 /* Make sure we are on first palette */
1173 if (rinfo->has_CRTC2) {
1174 dac_cntl2 = INREG(DAC_CNTL2);
1175 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1176 OUTREG(DAC_CNTL2, dac_cntl2);
1177 }
1178 }
1179
1180 red = cmap->red;
1181 green = cmap->green;
1182 blue = cmap->blue;
1183 transp = cmap->transp;
1184 start = cmap->start;
1185
1186 for (i = 0; i < cmap->len; i++) {
1187 u_int hred, hgreen, hblue, htransp = 0xffff;
1188
1189 hred = *red++;
1190 hgreen = *green++;
1191 hblue = *blue++;
1192 if (transp)
1193 htransp = *transp++;
1194 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1195 rinfo);
1196 if (rc)
1197 break;
1198 }
1199
1200 if (!rinfo->asleep && rinfo->is_mobility)
1201 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1202
1203 return rc;
1204 }
1205
1206 static void radeon_save_state (struct radeonfb_info *rinfo,
1207 struct radeon_regs *save)
1208 {
1209 /* CRTC regs */
1210 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1211 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1212 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1213 save->dac_cntl = INREG(DAC_CNTL);
1214 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1215 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1216 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1217 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1218 save->crtc_pitch = INREG(CRTC_PITCH);
1219 save->surface_cntl = INREG(SURFACE_CNTL);
1220
1221 /* FP regs */
1222 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1223 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1224 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1225 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1226 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1227 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1228 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1229 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1230 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1231 save->tmds_crc = INREG(TMDS_CRC);
1232 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1233 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1234
1235 /* PLL regs */
1236 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1237 radeon_pll_errata_after_index(rinfo);
1238 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1239 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1240 }
1241
1242
1243 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1244 {
1245 int i;
1246
1247 radeon_fifo_wait(20);
1248
1249 /* Workaround from XFree */
1250 if (rinfo->is_mobility) {
1251 /* A temporal workaround for the occasional blanking on certain laptop
1252 * panels. This appears to related to the PLL divider registers
1253 * (fail to lock?). It occurs even when all dividers are the same
1254 * with their old settings. In this case we really don't need to
1255 * fiddle with PLL registers. By doing this we can avoid the blanking
1256 * problem with some panels.
1257 */
1258 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1259 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1260 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1261 /* We still have to force a switch to selected PPLL div thanks to
1262 * an XFree86 driver bug which will switch it away in some cases
1263 * even when using UseFDev */
1264 OUTREGP(CLOCK_CNTL_INDEX,
1265 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1266 ~PPLL_DIV_SEL_MASK);
1267 radeon_pll_errata_after_index(rinfo);
1268 radeon_pll_errata_after_data(rinfo);
1269 return;
1270 }
1271 }
1272
1273 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1274 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1275
1276 /* Reset PPLL & enable atomic update */
1277 OUTPLLP(PPLL_CNTL,
1278 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1279 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1280
1281 /* Switch to selected PPLL divider */
1282 OUTREGP(CLOCK_CNTL_INDEX,
1283 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1284 ~PPLL_DIV_SEL_MASK);
1285 radeon_pll_errata_after_index(rinfo);
1286 radeon_pll_errata_after_data(rinfo);
1287
1288 /* Set PPLL ref. div */
1289 if (IS_R300_VARIANT(rinfo) ||
1290 rinfo->family == CHIP_FAMILY_RS300 ||
1291 rinfo->family == CHIP_FAMILY_RS400 ||
1292 rinfo->family == CHIP_FAMILY_RS480) {
1293 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1294 /* When restoring console mode, use saved PPLL_REF_DIV
1295 * setting.
1296 */
1297 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1298 } else {
1299 /* R300 uses ref_div_acc field as real ref divider */
1300 OUTPLLP(PPLL_REF_DIV,
1301 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1302 ~R300_PPLL_REF_DIV_ACC_MASK);
1303 }
1304 } else
1305 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1306
1307 /* Set PPLL divider 3 & post divider*/
1308 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1309 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1310
1311 /* Write update */
1312 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1313 ;
1314 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1315
1316 /* Wait read update complete */
1317 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1318 the cause yet, but this workaround will mask the problem for now.
1319 Other chips usually will pass at the very first test, so the
1320 workaround shouldn't have any effect on them. */
1321 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1322 ;
1323
1324 OUTPLL(HTOTAL_CNTL, 0);
1325
1326 /* Clear reset & atomic update */
1327 OUTPLLP(PPLL_CNTL, 0,
1328 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1329
1330 /* We may want some locking ... oh well */
1331 radeon_msleep(5);
1332
1333 /* Switch back VCLK source to PPLL */
1334 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1335 }
1336
1337 /*
1338 * Timer function for delayed LVDS panel power up/down
1339 */
1340 static void radeon_lvds_timer_func(unsigned long data)
1341 {
1342 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1343
1344 radeon_engine_idle();
1345
1346 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1347 }
1348
1349 /*
1350 * Apply a video mode. This will apply the whole register set, including
1351 * the PLL registers, to the card
1352 */
1353 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1354 int regs_only)
1355 {
1356 int i;
1357 int primary_mon = PRIMARY_MONITOR(rinfo);
1358
1359 if (nomodeset)
1360 return;
1361
1362 if (!regs_only)
1363 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1364
1365 radeon_fifo_wait(31);
1366 for (i=0; i<10; i++)
1367 OUTREG(common_regs[i].reg, common_regs[i].val);
1368
1369 /* Apply surface registers */
1370 for (i=0; i<8; i++) {
1371 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1372 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1373 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1374 }
1375
1376 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1377 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1378 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1379 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1380 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1381 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1382 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1383 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1384 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1385 OUTREG(CRTC_OFFSET, 0);
1386 OUTREG(CRTC_OFFSET_CNTL, 0);
1387 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1388 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1389
1390 radeon_write_pll_regs(rinfo, mode);
1391
1392 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1393 radeon_fifo_wait(10);
1394 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1395 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1396 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1397 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1398 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1399 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1400 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1401 OUTREG(TMDS_CRC, mode->tmds_crc);
1402 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1403 }
1404
1405 if (!regs_only)
1406 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1407
1408 radeon_fifo_wait(2);
1409 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1410
1411 return;
1412 }
1413
1414 /*
1415 * Calculate the PLL values for a given mode
1416 */
1417 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1418 unsigned long freq)
1419 {
1420 const struct {
1421 int divider;
1422 int bitvalue;
1423 } *post_div,
1424 post_divs[] = {
1425 { 1, 0 },
1426 { 2, 1 },
1427 { 4, 2 },
1428 { 8, 3 },
1429 { 3, 4 },
1430 { 16, 5 },
1431 { 6, 6 },
1432 { 12, 7 },
1433 { 0, 0 },
1434 };
1435 int fb_div, pll_output_freq = 0;
1436 int uses_dvo = 0;
1437
1438 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1439 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1440 * recent than an r(v)100...
1441 */
1442 #if 1
1443 /* XXX I had reports of flicker happening with the cinema display
1444 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1445 * this case. This could just be a bandwidth calculation issue, I
1446 * haven't implemented the bandwidth code yet, but in the meantime,
1447 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1448 * I haven't seen a case were were absolutely needed an odd PLL
1449 * divider. I'll find a better fix once I have more infos on the
1450 * real cause of the problem.
1451 */
1452 while (rinfo->has_CRTC2) {
1453 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1454 u32 disp_output_cntl;
1455 int source;
1456
1457 /* FP2 path not enabled */
1458 if ((fp2_gen_cntl & FP2_ON) == 0)
1459 break;
1460 /* Not all chip revs have the same format for this register,
1461 * extract the source selection
1462 */
1463 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1464 source = (fp2_gen_cntl >> 10) & 0x3;
1465 /* sourced from transform unit, check for transform unit
1466 * own source
1467 */
1468 if (source == 3) {
1469 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1470 source = (disp_output_cntl >> 12) & 0x3;
1471 }
1472 } else
1473 source = (fp2_gen_cntl >> 13) & 0x1;
1474 /* sourced from CRTC2 -> exit */
1475 if (source == 1)
1476 break;
1477
1478 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1479 uses_dvo = 1;
1480 break;
1481 }
1482 #else
1483 uses_dvo = 1;
1484 #endif
1485 if (freq > rinfo->pll.ppll_max)
1486 freq = rinfo->pll.ppll_max;
1487 if (freq*12 < rinfo->pll.ppll_min)
1488 freq = rinfo->pll.ppll_min / 12;
1489 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1490 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1491
1492 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1493 pll_output_freq = post_div->divider * freq;
1494 /* If we output to the DVO port (external TMDS), we don't allow an
1495 * odd PLL divider as those aren't supported on this path
1496 */
1497 if (uses_dvo && (post_div->divider & 1))
1498 continue;
1499 if (pll_output_freq >= rinfo->pll.ppll_min &&
1500 pll_output_freq <= rinfo->pll.ppll_max)
1501 break;
1502 }
1503
1504 /* If we fall through the bottom, try the "default value"
1505 given by the terminal post_div->bitvalue */
1506 if ( !post_div->divider ) {
1507 post_div = &post_divs[post_div->bitvalue];
1508 pll_output_freq = post_div->divider * freq;
1509 }
1510 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1511 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1512 pll_output_freq);
1513
1514 /* If we fall through the bottom, try the "default value"
1515 given by the terminal post_div->bitvalue */
1516 if ( !post_div->divider ) {
1517 post_div = &post_divs[post_div->bitvalue];
1518 pll_output_freq = post_div->divider * freq;
1519 }
1520 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1521 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1522 pll_output_freq);
1523
1524 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1525 rinfo->pll.ref_clk);
1526 regs->ppll_ref_div = rinfo->pll.ref_div;
1527 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1528
1529 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1530 pr_debug("fb_div = 0x%x\n", fb_div);
1531 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1532 }
1533
1534 static int radeonfb_set_par(struct fb_info *info)
1535 {
1536 struct radeonfb_info *rinfo = info->par;
1537 struct fb_var_screeninfo *mode = &info->var;
1538 struct radeon_regs *newmode;
1539 int hTotal, vTotal, hSyncStart, hSyncEnd,
1540 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1541 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1542 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1543 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1544 int i, freq;
1545 int format = 0;
1546 int nopllcalc = 0;
1547 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1548 int primary_mon = PRIMARY_MONITOR(rinfo);
1549 int depth = var_to_depth(mode);
1550 int use_rmx = 0;
1551
1552 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1553 if (!newmode)
1554 return -ENOMEM;
1555
1556 /* We always want engine to be idle on a mode switch, even
1557 * if we won't actually change the mode
1558 */
1559 radeon_engine_idle();
1560
1561 hSyncStart = mode->xres + mode->right_margin;
1562 hSyncEnd = hSyncStart + mode->hsync_len;
1563 hTotal = hSyncEnd + mode->left_margin;
1564
1565 vSyncStart = mode->yres + mode->lower_margin;
1566 vSyncEnd = vSyncStart + mode->vsync_len;
1567 vTotal = vSyncEnd + mode->upper_margin;
1568 pixClock = mode->pixclock;
1569
1570 sync = mode->sync;
1571 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1572 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1573
1574 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1575 if (rinfo->panel_info.xres < mode->xres)
1576 mode->xres = rinfo->panel_info.xres;
1577 if (rinfo->panel_info.yres < mode->yres)
1578 mode->yres = rinfo->panel_info.yres;
1579
1580 hTotal = mode->xres + rinfo->panel_info.hblank;
1581 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1582 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1583
1584 vTotal = mode->yres + rinfo->panel_info.vblank;
1585 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1586 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1587
1588 h_sync_pol = !rinfo->panel_info.hAct_high;
1589 v_sync_pol = !rinfo->panel_info.vAct_high;
1590
1591 pixClock = 100000000 / rinfo->panel_info.clock;
1592
1593 if (rinfo->panel_info.use_bios_dividers) {
1594 nopllcalc = 1;
1595 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1596 (rinfo->panel_info.post_divider << 16);
1597 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1598 }
1599 }
1600 dotClock = 1000000000 / pixClock;
1601 freq = dotClock / 10; /* x100 */
1602
1603 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1604 hSyncStart, hSyncEnd, hTotal);
1605 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1606 vSyncStart, vSyncEnd, vTotal);
1607
1608 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1609 vsync_wid = vSyncEnd - vSyncStart;
1610 if (hsync_wid == 0)
1611 hsync_wid = 1;
1612 else if (hsync_wid > 0x3f) /* max */
1613 hsync_wid = 0x3f;
1614
1615 if (vsync_wid == 0)
1616 vsync_wid = 1;
1617 else if (vsync_wid > 0x1f) /* max */
1618 vsync_wid = 0x1f;
1619
1620 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1621 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1622
1623 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1624
1625 format = radeon_get_dstbpp(depth);
1626 bytpp = mode->bits_per_pixel >> 3;
1627
1628 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1629 hsync_fudge = hsync_fudge_fp[format-1];
1630 else
1631 hsync_fudge = hsync_adj_tab[format-1];
1632
1633 hsync_start = hSyncStart - 8 + hsync_fudge;
1634
1635 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1636 (format << 8);
1637
1638 /* Clear auto-center etc... */
1639 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1640 newmode->crtc_more_cntl &= 0xfffffff0;
1641
1642 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1643 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1644 if (mirror)
1645 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1646
1647 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1648 CRTC_INTERLACE_EN);
1649 } else {
1650 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1651 CRTC_CRT_ON;
1652 }
1653
1654 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1655 DAC_8BIT_EN;
1656
1657 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1658 (((mode->xres / 8) - 1) << 16));
1659
1660 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1661 (hsync_wid << 16) | (h_sync_pol << 23));
1662
1663 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1664 ((mode->yres - 1) << 16);
1665
1666 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1667 (vsync_wid << 16) | (v_sync_pol << 23));
1668
1669 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1670 /* We first calculate the engine pitch */
1671 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1672 & ~(0x3f)) >> 6;
1673
1674 /* Then, re-multiply it to get the CRTC pitch */
1675 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1676 } else
1677 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1678
1679 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1680
1681 /*
1682 * It looks like recent chips have a problem with SURFACE_CNTL,
1683 * setting SURF_TRANSLATION_DIS completely disables the
1684 * swapper as well, so we leave it unset now.
1685 */
1686 newmode->surface_cntl = 0;
1687
1688 #if defined(__BIG_ENDIAN)
1689
1690 /* Setup swapping on both apertures, though we currently
1691 * only use aperture 0, enabling swapper on aperture 1
1692 * won't harm
1693 */
1694 switch (mode->bits_per_pixel) {
1695 case 16:
1696 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1697 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1698 break;
1699 case 24:
1700 case 32:
1701 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1702 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1703 break;
1704 }
1705 #endif
1706
1707 /* Clear surface registers */
1708 for (i=0; i<8; i++) {
1709 newmode->surf_lower_bound[i] = 0;
1710 newmode->surf_upper_bound[i] = 0x1f;
1711 newmode->surf_info[i] = 0;
1712 }
1713
1714 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1715 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1716 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1717 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1718
1719 rinfo->bpp = mode->bits_per_pixel;
1720 rinfo->depth = depth;
1721
1722 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1723 pr_debug("freq = %lu\n", (unsigned long)freq);
1724
1725 /* We use PPLL_DIV_3 */
1726 newmode->clk_cntl_index = 0x300;
1727
1728 /* Calculate PPLL value if necessary */
1729 if (!nopllcalc)
1730 radeon_calc_pll_regs(rinfo, newmode, freq);
1731
1732 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1733
1734 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1735 unsigned int hRatio, vRatio;
1736
1737 if (mode->xres > rinfo->panel_info.xres)
1738 mode->xres = rinfo->panel_info.xres;
1739 if (mode->yres > rinfo->panel_info.yres)
1740 mode->yres = rinfo->panel_info.yres;
1741
1742 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1743 << HORZ_PANEL_SHIFT);
1744 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1745 << VERT_PANEL_SHIFT);
1746
1747 if (mode->xres != rinfo->panel_info.xres) {
1748 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1749 rinfo->panel_info.xres);
1750 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1751 (newmode->fp_horz_stretch &
1752 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1753 HORZ_AUTO_RATIO_INC)));
1754 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1755 HORZ_STRETCH_ENABLE);
1756 use_rmx = 1;
1757 }
1758 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1759
1760 if (mode->yres != rinfo->panel_info.yres) {
1761 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1762 rinfo->panel_info.yres);
1763 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1764 (newmode->fp_vert_stretch &
1765 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1766 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1767 VERT_STRETCH_ENABLE);
1768 use_rmx = 1;
1769 }
1770 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1771
1772 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1773 ~(FP_SEL_CRTC2 |
1774 FP_RMX_HVSYNC_CONTROL_EN |
1775 FP_DFP_SYNC_SEL |
1776 FP_CRT_SYNC_SEL |
1777 FP_CRTC_LOCK_8DOT |
1778 FP_USE_SHADOW_EN |
1779 FP_CRTC_USE_SHADOW_VEND |
1780 FP_CRT_SYNC_ALT));
1781
1782 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1783 FP_CRTC_DONT_SHADOW_HEND |
1784 FP_PANEL_FORMAT);
1785
1786 if (IS_R300_VARIANT(rinfo) ||
1787 (rinfo->family == CHIP_FAMILY_R200)) {
1788 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1789 if (use_rmx)
1790 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1791 else
1792 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1793 } else
1794 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1795
1796 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1797 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1798 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1799 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1800
1801 if (primary_mon == MT_LCD) {
1802 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1803 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1804 } else {
1805 /* DFP */
1806 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1807 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1808 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1809 if (IS_R300_VARIANT(rinfo) ||
1810 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1811 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1812 else
1813 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1814 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1815 }
1816
1817 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1818 (((mode->xres / 8) - 1) << 16));
1819 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1820 ((mode->yres - 1) << 16);
1821 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1822 (hsync_wid << 16) | (h_sync_pol << 23));
1823 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1824 (vsync_wid << 16) | (v_sync_pol << 23));
1825 }
1826
1827 /* do it! */
1828 if (!rinfo->asleep) {
1829 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1830 radeon_write_mode (rinfo, newmode, 0);
1831 /* (re)initialize the engine */
1832 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1833 radeonfb_engine_init (rinfo);
1834 }
1835 /* Update fix */
1836 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1837 info->fix.line_length = rinfo->pitch*64;
1838 else
1839 info->fix.line_length = mode->xres_virtual
1840 * ((mode->bits_per_pixel + 1) / 8);
1841 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1842 : FB_VISUAL_DIRECTCOLOR;
1843
1844 #ifdef CONFIG_BOOTX_TEXT
1845 /* Update debug text engine */
1846 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1847 rinfo->depth, info->fix.line_length);
1848 #endif
1849
1850 kfree(newmode);
1851 return 0;
1852 }
1853
1854
1855 static struct fb_ops radeonfb_ops = {
1856 .owner = THIS_MODULE,
1857 .fb_check_var = radeonfb_check_var,
1858 .fb_set_par = radeonfb_set_par,
1859 .fb_setcolreg = radeonfb_setcolreg,
1860 .fb_setcmap = radeonfb_setcmap,
1861 .fb_pan_display = radeonfb_pan_display,
1862 .fb_blank = radeonfb_blank,
1863 .fb_ioctl = radeonfb_ioctl,
1864 .fb_sync = radeonfb_sync,
1865 .fb_fillrect = radeonfb_fillrect,
1866 .fb_copyarea = radeonfb_copyarea,
1867 .fb_imageblit = radeonfb_imageblit,
1868 };
1869
1870
1871 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1872 {
1873 struct fb_info *info = rinfo->info;
1874
1875 info->par = rinfo;
1876 info->pseudo_palette = rinfo->pseudo_palette;
1877 info->flags = FBINFO_DEFAULT
1878 | FBINFO_HWACCEL_COPYAREA
1879 | FBINFO_HWACCEL_FILLRECT
1880 | FBINFO_HWACCEL_XPAN
1881 | FBINFO_HWACCEL_YPAN;
1882 info->fbops = &radeonfb_ops;
1883 info->screen_base = rinfo->fb_base;
1884 info->screen_size = rinfo->mapped_vram;
1885 /* Fill fix common fields */
1886 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1887 info->fix.smem_start = rinfo->fb_base_phys;
1888 info->fix.smem_len = rinfo->video_ram;
1889 info->fix.type = FB_TYPE_PACKED_PIXELS;
1890 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1891 info->fix.xpanstep = 8;
1892 info->fix.ypanstep = 1;
1893 info->fix.ywrapstep = 0;
1894 info->fix.type_aux = 0;
1895 info->fix.mmio_start = rinfo->mmio_base_phys;
1896 info->fix.mmio_len = RADEON_REGSIZE;
1897 info->fix.accel = FB_ACCEL_ATI_RADEON;
1898
1899 fb_alloc_cmap(&info->cmap, 256, 0);
1900
1901 if (noaccel)
1902 info->flags |= FBINFO_HWACCEL_DISABLED;
1903
1904 return 0;
1905 }
1906
1907 /*
1908 * This reconfigure the card's internal memory map. In theory, we'd like
1909 * to setup the card's memory at the same address as it's PCI bus address,
1910 * and the AGP aperture right after that so that system RAM on 32 bits
1911 * machines at least, is directly accessible. However, doing so would
1912 * conflict with the current XFree drivers...
1913 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1914 * on the proper way to set this up and duplicate this here. In the meantime,
1915 * I put the card's memory at 0 in card space and AGP at some random high
1916 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1917 */
1918 #ifdef CONFIG_PPC_OF
1919 #undef SET_MC_FB_FROM_APERTURE
1920 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1921 {
1922 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1923 u32 save_crtc_ext_cntl;
1924 u32 aper_base, aper_size;
1925 u32 agp_base;
1926
1927 /* First, we disable display to avoid interfering */
1928 if (rinfo->has_CRTC2) {
1929 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1930 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1931 }
1932 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1933 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1934
1935 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1936 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1937 mdelay(100);
1938
1939 aper_base = INREG(CNFG_APER_0_BASE);
1940 aper_size = INREG(CNFG_APER_SIZE);
1941
1942 #ifdef SET_MC_FB_FROM_APERTURE
1943 /* Set framebuffer to be at the same address as set in PCI BAR */
1944 OUTREG(MC_FB_LOCATION,
1945 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1946 rinfo->fb_local_base = aper_base;
1947 #else
1948 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1949 rinfo->fb_local_base = 0;
1950 #endif
1951 agp_base = aper_base + aper_size;
1952 if (agp_base & 0xf0000000)
1953 agp_base = (aper_base | 0x0fffffff) + 1;
1954
1955 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1956 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1957 * always the case on PPCs afaik.
1958 */
1959 #ifdef SET_MC_FB_FROM_APERTURE
1960 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1961 #else
1962 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1963 #endif
1964
1965 /* Fixup the display base addresses & engine offsets while we
1966 * are at it as well
1967 */
1968 #ifdef SET_MC_FB_FROM_APERTURE
1969 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1970 if (rinfo->has_CRTC2)
1971 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1972 OUTREG(OV0_BASE_ADDR, aper_base);
1973 #else
1974 OUTREG(DISPLAY_BASE_ADDR, 0);
1975 if (rinfo->has_CRTC2)
1976 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1977 OUTREG(OV0_BASE_ADDR, 0);
1978 #endif
1979 mdelay(100);
1980
1981 /* Restore display settings */
1982 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1983 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1984 if (rinfo->has_CRTC2)
1985 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1986
1987 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1988 aper_base,
1989 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1990 0xffff0000 | (agp_base >> 16));
1991 }
1992 #endif /* CONFIG_PPC_OF */
1993
1994
1995 static void radeon_identify_vram(struct radeonfb_info *rinfo)
1996 {
1997 u32 tmp;
1998
1999 /* framebuffer size */
2000 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2001 (rinfo->family == CHIP_FAMILY_RS200) ||
2002 (rinfo->family == CHIP_FAMILY_RS300) ||
2003 (rinfo->family == CHIP_FAMILY_RC410) ||
2004 (rinfo->family == CHIP_FAMILY_RS400) ||
2005 (rinfo->family == CHIP_FAMILY_RS480) ) {
2006 u32 tom = INREG(NB_TOM);
2007 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2008
2009 radeon_fifo_wait(6);
2010 OUTREG(MC_FB_LOCATION, tom);
2011 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2012 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2013 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2014
2015 /* This is supposed to fix the crtc2 noise problem. */
2016 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2017
2018 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2019 (rinfo->family == CHIP_FAMILY_RS200)) {
2020 /* This is to workaround the asic bug for RMX, some versions
2021 of BIOS dosen't have this register initialized correctly.
2022 */
2023 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2024 ~CRTC_H_CUTOFF_ACTIVE_EN);
2025 }
2026 } else {
2027 tmp = INREG(CNFG_MEMSIZE);
2028 }
2029
2030 /* mem size is bits [28:0], mask off the rest */
2031 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2032
2033 /*
2034 * Hack to get around some busted production M6's
2035 * reporting no ram
2036 */
2037 if (rinfo->video_ram == 0) {
2038 switch (rinfo->pdev->device) {
2039 case PCI_CHIP_RADEON_LY:
2040 case PCI_CHIP_RADEON_LZ:
2041 rinfo->video_ram = 8192 * 1024;
2042 break;
2043 default:
2044 break;
2045 }
2046 }
2047
2048
2049 /*
2050 * Now try to identify VRAM type
2051 */
2052 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2053 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2054 rinfo->vram_ddr = 1;
2055 else
2056 rinfo->vram_ddr = 0;
2057
2058 tmp = INREG(MEM_CNTL);
2059 if (IS_R300_VARIANT(rinfo)) {
2060 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2061 switch (tmp) {
2062 case 0: rinfo->vram_width = 64; break;
2063 case 1: rinfo->vram_width = 128; break;
2064 case 2: rinfo->vram_width = 256; break;
2065 default: rinfo->vram_width = 128; break;
2066 }
2067 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2068 (rinfo->family == CHIP_FAMILY_RS100) ||
2069 (rinfo->family == CHIP_FAMILY_RS200)){
2070 if (tmp & RV100_MEM_HALF_MODE)
2071 rinfo->vram_width = 32;
2072 else
2073 rinfo->vram_width = 64;
2074 } else {
2075 if (tmp & MEM_NUM_CHANNELS_MASK)
2076 rinfo->vram_width = 128;
2077 else
2078 rinfo->vram_width = 64;
2079 }
2080
2081 /* This may not be correct, as some cards can have half of channel disabled
2082 * ToDo: identify these cases
2083 */
2084
2085 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2086 pci_name(rinfo->pdev),
2087 rinfo->video_ram / 1024,
2088 rinfo->vram_ddr ? "DDR" : "SDRAM",
2089 rinfo->vram_width);
2090 }
2091
2092 /*
2093 * Sysfs
2094 */
2095
2096 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2097 {
2098 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
2099 }
2100
2101
2102 static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
2103 struct bin_attribute *bin_attr,
2104 char *buf, loff_t off, size_t count)
2105 {
2106 struct device *dev = container_of(kobj, struct device, kobj);
2107 struct pci_dev *pdev = to_pci_dev(dev);
2108 struct fb_info *info = pci_get_drvdata(pdev);
2109 struct radeonfb_info *rinfo = info->par;
2110
2111 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2112 }
2113
2114
2115 static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
2116 struct bin_attribute *bin_attr,
2117 char *buf, loff_t off, size_t count)
2118 {
2119 struct device *dev = container_of(kobj, struct device, kobj);
2120 struct pci_dev *pdev = to_pci_dev(dev);
2121 struct fb_info *info = pci_get_drvdata(pdev);
2122 struct radeonfb_info *rinfo = info->par;
2123
2124 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2125 }
2126
2127 static struct bin_attribute edid1_attr = {
2128 .attr = {
2129 .name = "edid1",
2130 .mode = 0444,
2131 },
2132 .size = EDID_LENGTH,
2133 .read = radeon_show_edid1,
2134 };
2135
2136 static struct bin_attribute edid2_attr = {
2137 .attr = {
2138 .name = "edid2",
2139 .mode = 0444,
2140 },
2141 .size = EDID_LENGTH,
2142 .read = radeon_show_edid2,
2143 };
2144
2145
2146 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2147 const struct pci_device_id *ent)
2148 {
2149 struct fb_info *info;
2150 struct radeonfb_info *rinfo;
2151 int ret;
2152 unsigned char c1, c2;
2153 int err = 0;
2154
2155 pr_debug("radeonfb_pci_register BEGIN\n");
2156
2157 /* Enable device in PCI config */
2158 ret = pci_enable_device(pdev);
2159 if (ret < 0) {
2160 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2161 pci_name(pdev));
2162 goto err_out;
2163 }
2164
2165 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2166 if (!info) {
2167 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2168 pci_name(pdev));
2169 ret = -ENOMEM;
2170 goto err_disable;
2171 }
2172 rinfo = info->par;
2173 rinfo->info = info;
2174 rinfo->pdev = pdev;
2175
2176 spin_lock_init(&rinfo->reg_lock);
2177 init_timer(&rinfo->lvds_timer);
2178 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2179 rinfo->lvds_timer.data = (unsigned long)rinfo;
2180
2181 c1 = ent->device >> 8;
2182 c2 = ent->device & 0xff;
2183 if (isprint(c1) && isprint(c2))
2184 snprintf(rinfo->name, sizeof(rinfo->name),
2185 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2186 else
2187 snprintf(rinfo->name, sizeof(rinfo->name),
2188 "ATI Radeon %x", ent->device & 0xffff);
2189
2190 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2191 rinfo->chipset = pdev->device;
2192 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2193 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2194 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2195
2196 /* Set base addrs */
2197 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2198 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2199
2200 /* request the mem regions */
2201 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2202 if (ret < 0) {
2203 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2204 pci_name(rinfo->pdev));
2205 goto err_release_fb;
2206 }
2207
2208 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2209 if (ret < 0) {
2210 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2211 pci_name(rinfo->pdev));
2212 goto err_release_pci0;
2213 }
2214
2215 /* map the regions */
2216 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2217 if (!rinfo->mmio_base) {
2218 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2219 pci_name(rinfo->pdev));
2220 ret = -EIO;
2221 goto err_release_pci2;
2222 }
2223
2224 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2225
2226 /*
2227 * Check for errata
2228 */
2229 rinfo->errata = 0;
2230 if (rinfo->family == CHIP_FAMILY_R300 &&
2231 (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
2232 == CFG_ATI_REV_A11)
2233 rinfo->errata |= CHIP_ERRATA_R300_CG;
2234
2235 if (rinfo->family == CHIP_FAMILY_RV200 ||
2236 rinfo->family == CHIP_FAMILY_RS200)
2237 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2238
2239 if (rinfo->family == CHIP_FAMILY_RV100 ||
2240 rinfo->family == CHIP_FAMILY_RS100 ||
2241 rinfo->family == CHIP_FAMILY_RS200)
2242 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2243
2244 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2245 /* On PPC, we obtain the OF device-node pointer to the firmware
2246 * data for this chip
2247 */
2248 rinfo->of_node = pci_device_to_OF_node(pdev);
2249 if (rinfo->of_node == NULL)
2250 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2251 pci_name(rinfo->pdev));
2252
2253 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2254 #ifdef CONFIG_PPC_OF
2255 /* On PPC, the firmware sets up a memory mapping that tends
2256 * to cause lockups when enabling the engine. We reconfigure
2257 * the card internal memory mappings properly
2258 */
2259 fixup_memory_mappings(rinfo);
2260 #endif /* CONFIG_PPC_OF */
2261
2262 /* Get VRAM size and type */
2263 radeon_identify_vram(rinfo);
2264
2265 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2266
2267 do {
2268 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2269 rinfo->mapped_vram);
2270 } while (rinfo->fb_base == NULL &&
2271 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2272
2273 if (rinfo->fb_base == NULL) {
2274 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2275 pci_name(rinfo->pdev));
2276 ret = -EIO;
2277 goto err_unmap_rom;
2278 }
2279
2280 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2281 rinfo->mapped_vram/1024);
2282
2283 /*
2284 * Map the BIOS ROM if any and retrieve PLL parameters from
2285 * the BIOS. We skip that on mobility chips as the real panel
2286 * values we need aren't in the ROM but in the BIOS image in
2287 * memory. This is definitely not the best meacnism though,
2288 * we really need the arch code to tell us which is the "primary"
2289 * video adapter to use the memory image (or better, the arch
2290 * should provide us a copy of the BIOS image to shield us from
2291 * archs who would store that elsewhere and/or could initialize
2292 * more than one adapter during boot).
2293 */
2294 if (!rinfo->is_mobility)
2295 radeon_map_ROM(rinfo, pdev);
2296
2297 /*
2298 * On x86, the primary display on laptop may have it's BIOS
2299 * ROM elsewhere, try to locate it at the legacy memory hole.
2300 * We probably need to make sure this is the primary display,
2301 * but that is difficult without some arch support.
2302 */
2303 #ifdef CONFIG_X86
2304 if (rinfo->bios_seg == NULL)
2305 radeon_find_mem_vbios(rinfo);
2306 #endif
2307
2308 /* If both above failed, try the BIOS ROM again for mobility
2309 * chips
2310 */
2311 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2312 radeon_map_ROM(rinfo, pdev);
2313
2314 /* Get informations about the board's PLL */
2315 radeon_get_pllinfo(rinfo);
2316
2317 #ifdef CONFIG_FB_RADEON_I2C
2318 /* Register I2C bus */
2319 radeon_create_i2c_busses(rinfo);
2320 #endif
2321
2322 /* set all the vital stuff */
2323 radeon_set_fbinfo (rinfo);
2324
2325 /* Probe screen types */
2326 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2327
2328 /* Build mode list, check out panel native model */
2329 radeon_check_modes(rinfo, mode_option);
2330
2331 /* Register some sysfs stuff (should be done better) */
2332 if (rinfo->mon1_EDID)
2333 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2334 &edid1_attr);
2335 if (rinfo->mon2_EDID)
2336 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2337 &edid2_attr);
2338 if (err)
2339 pr_warning("%s() Creating sysfs files failed, continuing\n",
2340 __func__);
2341
2342 /* save current mode regs before we switch into the new one
2343 * so we can restore this upon __exit
2344 */
2345 radeon_save_state (rinfo, &rinfo->init_state);
2346 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2347
2348 /* Setup Power Management capabilities */
2349 if (default_dynclk < -1) {
2350 /* -2 is special: means ON on mobility chips and do not
2351 * change on others
2352 */
2353 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2354 } else
2355 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2356
2357 pci_set_drvdata(pdev, info);
2358
2359 /* Register with fbdev layer */
2360 ret = register_framebuffer(info);
2361 if (ret < 0) {
2362 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2363 pci_name(rinfo->pdev));
2364 goto err_unmap_fb;
2365 }
2366
2367 #ifdef CONFIG_MTRR
2368 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2369 rinfo->video_ram,
2370 MTRR_TYPE_WRCOMB, 1);
2371 #endif
2372
2373 if (backlight)
2374 radeonfb_bl_init(rinfo);
2375
2376 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2377
2378 if (rinfo->bios_seg)
2379 radeon_unmap_ROM(rinfo, pdev);
2380 pr_debug("radeonfb_pci_register END\n");
2381
2382 return 0;
2383 err_unmap_fb:
2384 iounmap(rinfo->fb_base);
2385 err_unmap_rom:
2386 kfree(rinfo->mon1_EDID);
2387 kfree(rinfo->mon2_EDID);
2388 if (rinfo->mon1_modedb)
2389 fb_destroy_modedb(rinfo->mon1_modedb);
2390 fb_dealloc_cmap(&info->cmap);
2391 #ifdef CONFIG_FB_RADEON_I2C
2392 radeon_delete_i2c_busses(rinfo);
2393 #endif
2394 if (rinfo->bios_seg)
2395 radeon_unmap_ROM(rinfo, pdev);
2396 iounmap(rinfo->mmio_base);
2397 err_release_pci2:
2398 pci_release_region(pdev, 2);
2399 err_release_pci0:
2400 pci_release_region(pdev, 0);
2401 err_release_fb:
2402 framebuffer_release(info);
2403 err_disable:
2404 err_out:
2405 return ret;
2406 }
2407
2408
2409
2410 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2411 {
2412 struct fb_info *info = pci_get_drvdata(pdev);
2413 struct radeonfb_info *rinfo = info->par;
2414
2415 if (!rinfo)
2416 return;
2417
2418 radeonfb_pm_exit(rinfo);
2419
2420 if (rinfo->mon1_EDID)
2421 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2422 if (rinfo->mon2_EDID)
2423 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2424
2425 #if 0
2426 /* restore original state
2427 *
2428 * Doesn't quite work yet, I suspect if we come from a legacy
2429 * VGA mode (or worse, text mode), we need to do some VGA black
2430 * magic here that I know nothing about. --BenH
2431 */
2432 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2433 #endif
2434
2435 del_timer_sync(&rinfo->lvds_timer);
2436
2437 #ifdef CONFIG_MTRR
2438 if (rinfo->mtrr_hdl >= 0)
2439 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2440 #endif
2441
2442 unregister_framebuffer(info);
2443
2444 radeonfb_bl_exit(rinfo);
2445
2446 iounmap(rinfo->mmio_base);
2447 iounmap(rinfo->fb_base);
2448
2449 pci_release_region(pdev, 2);
2450 pci_release_region(pdev, 0);
2451
2452 kfree(rinfo->mon1_EDID);
2453 kfree(rinfo->mon2_EDID);
2454 if (rinfo->mon1_modedb)
2455 fb_destroy_modedb(rinfo->mon1_modedb);
2456 #ifdef CONFIG_FB_RADEON_I2C
2457 radeon_delete_i2c_busses(rinfo);
2458 #endif
2459 fb_dealloc_cmap(&info->cmap);
2460 framebuffer_release(info);
2461 }
2462
2463
2464 static struct pci_driver radeonfb_driver = {
2465 .name = "radeonfb",
2466 .id_table = radeonfb_pci_table,
2467 .probe = radeonfb_pci_register,
2468 .remove = __devexit_p(radeonfb_pci_unregister),
2469 #ifdef CONFIG_PM
2470 .suspend = radeonfb_pci_suspend,
2471 .resume = radeonfb_pci_resume,
2472 #endif /* CONFIG_PM */
2473 };
2474
2475 #ifndef MODULE
2476 static int __init radeonfb_setup (char *options)
2477 {
2478 char *this_opt;
2479
2480 if (!options || !*options)
2481 return 0;
2482
2483 while ((this_opt = strsep (&options, ",")) != NULL) {
2484 if (!*this_opt)
2485 continue;
2486
2487 if (!strncmp(this_opt, "noaccel", 7)) {
2488 noaccel = 1;
2489 } else if (!strncmp(this_opt, "mirror", 6)) {
2490 mirror = 1;
2491 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2492 force_dfp = 1;
2493 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2494 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2495 } else if (!strncmp(this_opt, "backlight:", 10)) {
2496 backlight = simple_strtoul(this_opt+10, NULL, 0);
2497 #ifdef CONFIG_MTRR
2498 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2499 nomtrr = 1;
2500 #endif
2501 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2502 nomodeset = 1;
2503 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2504 force_measure_pll = 1;
2505 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2506 ignore_edid = 1;
2507 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2508 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2509 force_sleep = 1;
2510 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2511 ignore_devlist = 1;
2512 #endif
2513 } else
2514 mode_option = this_opt;
2515 }
2516 return 0;
2517 }
2518 #endif /* MODULE */
2519
2520 static int __init radeonfb_init (void)
2521 {
2522 #ifndef MODULE
2523 char *option = NULL;
2524
2525 if (fb_get_options("radeonfb", &option))
2526 return -ENODEV;
2527 radeonfb_setup(option);
2528 #endif
2529 return pci_register_driver (&radeonfb_driver);
2530 }
2531
2532
2533 static void __exit radeonfb_exit (void)
2534 {
2535 pci_unregister_driver (&radeonfb_driver);
2536 }
2537
2538 module_init(radeonfb_init);
2539 module_exit(radeonfb_exit);
2540
2541 MODULE_AUTHOR("Ani Joshi");
2542 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2543 MODULE_LICENSE("GPL");
2544 module_param(noaccel, bool, 0);
2545 module_param(default_dynclk, int, 0);
2546 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2547 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2548 module_param(nomodeset, bool, 0);
2549 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2550 module_param(mirror, bool, 0);
2551 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2552 module_param(force_dfp, bool, 0);
2553 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2554 module_param(ignore_edid, bool, 0);
2555 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2556 module_param(monitor_layout, charp, 0);
2557 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2558 module_param(force_measure_pll, bool, 0);
2559 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2560 #ifdef CONFIG_MTRR
2561 module_param(nomtrr, bool, 0);
2562 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2563 #endif
2564 module_param(panel_yres, int, 0);
2565 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2566 module_param(mode_option, charp, 0);
2567 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2568 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2569 module_param(force_sleep, bool, 0);
2570 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2571 module_param(ignore_devlist, bool, 0);
2572 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2573 #endif