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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux...
[zen-stable.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
blob7695e5d43316686429158ec56aafacbc7d25a6a7
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/io.h>
22
23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h>
25 #include <plat/i2c.h>
26 #include <plat/gpio.h>
27 #include <plat/dma.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mmc.h>
31 #include <plat/i2c.h>
32 #include <plat/dmtimer.h>
33
34 #include "omap_hwmod_common_data.h"
35
36 #include "cm1_44xx.h"
37 #include "cm2_44xx.h"
38 #include "prm44xx.h"
39 #include "prm-regbits-44xx.h"
40 #include "wd_timer.h"
41
42 /* Base offset for all OMAP4 interrupts external to MPUSS */
43 #define OMAP44XX_IRQ_GIC_START 32
44
45 /* Base offset for all OMAP4 dma requests */
46 #define OMAP44XX_DMA_REQ_START 1
47
48 /* Backward references (IPs with Bus Master capability) */
49 static struct omap_hwmod omap44xx_aess_hwmod;
50 static struct omap_hwmod omap44xx_dma_system_hwmod;
51 static struct omap_hwmod omap44xx_dmm_hwmod;
52 static struct omap_hwmod omap44xx_dsp_hwmod;
53 static struct omap_hwmod omap44xx_dss_hwmod;
54 static struct omap_hwmod omap44xx_emif_fw_hwmod;
55 static struct omap_hwmod omap44xx_hsi_hwmod;
56 static struct omap_hwmod omap44xx_ipu_hwmod;
57 static struct omap_hwmod omap44xx_iss_hwmod;
58 static struct omap_hwmod omap44xx_iva_hwmod;
59 static struct omap_hwmod omap44xx_l3_instr_hwmod;
60 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
61 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
62 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
63 static struct omap_hwmod omap44xx_l4_abe_hwmod;
64 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
65 static struct omap_hwmod omap44xx_l4_per_hwmod;
66 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
67 static struct omap_hwmod omap44xx_mmc1_hwmod;
68 static struct omap_hwmod omap44xx_mmc2_hwmod;
69 static struct omap_hwmod omap44xx_mpu_hwmod;
70 static struct omap_hwmod omap44xx_mpu_private_hwmod;
71 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
72
73 /*
74 * Interconnects omap_hwmod structures
75 * hwmods that compose the global OMAP interconnect
76 */
77
78 /*
79 * 'dmm' class
80 * instance(s): dmm
81 */
82 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
83 .name = "dmm",
84 };
85
86 /* dmm */
87 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
88 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
89 { .irq = -1 }
90 };
91
92 /* l3_main_1 -> dmm */
93 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
94 .master = &omap44xx_l3_main_1_hwmod,
95 .slave = &omap44xx_dmm_hwmod,
96 .clk = "l3_div_ck",
97 .user = OCP_USER_SDMA,
98 };
99
100 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
101 {
102 .pa_start = 0x4e000000,
103 .pa_end = 0x4e0007ff,
104 .flags = ADDR_TYPE_RT
105 },
106 { }
107 };
108
109 /* mpu -> dmm */
110 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
111 .master = &omap44xx_mpu_hwmod,
112 .slave = &omap44xx_dmm_hwmod,
113 .clk = "l3_div_ck",
114 .addr = omap44xx_dmm_addrs,
115 .user = OCP_USER_MPU,
116 };
117
118 /* dmm slave ports */
119 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
120 &omap44xx_l3_main_1__dmm,
121 &omap44xx_mpu__dmm,
122 };
123
124 static struct omap_hwmod omap44xx_dmm_hwmod = {
125 .name = "dmm",
126 .class = &omap44xx_dmm_hwmod_class,
127 .clkdm_name = "l3_emif_clkdm",
128 .prcm = {
129 .omap4 = {
130 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
131 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
132 },
133 },
134 .slaves = omap44xx_dmm_slaves,
135 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
136 .mpu_irqs = omap44xx_dmm_irqs,
137 };
138
139 /*
140 * 'emif_fw' class
141 * instance(s): emif_fw
142 */
143 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
144 .name = "emif_fw",
145 };
146
147 /* emif_fw */
148 /* dmm -> emif_fw */
149 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
150 .master = &omap44xx_dmm_hwmod,
151 .slave = &omap44xx_emif_fw_hwmod,
152 .clk = "l3_div_ck",
153 .user = OCP_USER_MPU | OCP_USER_SDMA,
154 };
155
156 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
157 {
158 .pa_start = 0x4a20c000,
159 .pa_end = 0x4a20c0ff,
160 .flags = ADDR_TYPE_RT
161 },
162 { }
163 };
164
165 /* l4_cfg -> emif_fw */
166 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
167 .master = &omap44xx_l4_cfg_hwmod,
168 .slave = &omap44xx_emif_fw_hwmod,
169 .clk = "l4_div_ck",
170 .addr = omap44xx_emif_fw_addrs,
171 .user = OCP_USER_MPU,
172 };
173
174 /* emif_fw slave ports */
175 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
176 &omap44xx_dmm__emif_fw,
177 &omap44xx_l4_cfg__emif_fw,
178 };
179
180 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
181 .name = "emif_fw",
182 .class = &omap44xx_emif_fw_hwmod_class,
183 .clkdm_name = "l3_emif_clkdm",
184 .prcm = {
185 .omap4 = {
186 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
187 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
188 },
189 },
190 .slaves = omap44xx_emif_fw_slaves,
191 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
192 };
193
194 /*
195 * 'l3' class
196 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
197 */
198 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
199 .name = "l3",
200 };
201
202 /* l3_instr */
203 /* iva -> l3_instr */
204 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
205 .master = &omap44xx_iva_hwmod,
206 .slave = &omap44xx_l3_instr_hwmod,
207 .clk = "l3_div_ck",
208 .user = OCP_USER_MPU | OCP_USER_SDMA,
209 };
210
211 /* l3_main_3 -> l3_instr */
212 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
213 .master = &omap44xx_l3_main_3_hwmod,
214 .slave = &omap44xx_l3_instr_hwmod,
215 .clk = "l3_div_ck",
216 .user = OCP_USER_MPU | OCP_USER_SDMA,
217 };
218
219 /* l3_instr slave ports */
220 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
221 &omap44xx_iva__l3_instr,
222 &omap44xx_l3_main_3__l3_instr,
223 };
224
225 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
226 .name = "l3_instr",
227 .class = &omap44xx_l3_hwmod_class,
228 .clkdm_name = "l3_instr_clkdm",
229 .prcm = {
230 .omap4 = {
231 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
232 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
233 .modulemode = MODULEMODE_HWCTRL,
234 },
235 },
236 .slaves = omap44xx_l3_instr_slaves,
237 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
238 };
239
240 /* l3_main_1 */
241 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
242 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
243 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
244 { .irq = -1 }
245 };
246
247 /* dsp -> l3_main_1 */
248 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
249 .master = &omap44xx_dsp_hwmod,
250 .slave = &omap44xx_l3_main_1_hwmod,
251 .clk = "l3_div_ck",
252 .user = OCP_USER_MPU | OCP_USER_SDMA,
253 };
254
255 /* dss -> l3_main_1 */
256 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
257 .master = &omap44xx_dss_hwmod,
258 .slave = &omap44xx_l3_main_1_hwmod,
259 .clk = "l3_div_ck",
260 .user = OCP_USER_MPU | OCP_USER_SDMA,
261 };
262
263 /* l3_main_2 -> l3_main_1 */
264 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
265 .master = &omap44xx_l3_main_2_hwmod,
266 .slave = &omap44xx_l3_main_1_hwmod,
267 .clk = "l3_div_ck",
268 .user = OCP_USER_MPU | OCP_USER_SDMA,
269 };
270
271 /* l4_cfg -> l3_main_1 */
272 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
273 .master = &omap44xx_l4_cfg_hwmod,
274 .slave = &omap44xx_l3_main_1_hwmod,
275 .clk = "l4_div_ck",
276 .user = OCP_USER_MPU | OCP_USER_SDMA,
277 };
278
279 /* mmc1 -> l3_main_1 */
280 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
281 .master = &omap44xx_mmc1_hwmod,
282 .slave = &omap44xx_l3_main_1_hwmod,
283 .clk = "l3_div_ck",
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
285 };
286
287 /* mmc2 -> l3_main_1 */
288 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
289 .master = &omap44xx_mmc2_hwmod,
290 .slave = &omap44xx_l3_main_1_hwmod,
291 .clk = "l3_div_ck",
292 .user = OCP_USER_MPU | OCP_USER_SDMA,
293 };
294
295 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
296 {
297 .pa_start = 0x44000000,
298 .pa_end = 0x44000fff,
299 .flags = ADDR_TYPE_RT
300 },
301 { }
302 };
303
304 /* mpu -> l3_main_1 */
305 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
306 .master = &omap44xx_mpu_hwmod,
307 .slave = &omap44xx_l3_main_1_hwmod,
308 .clk = "l3_div_ck",
309 .addr = omap44xx_l3_main_1_addrs,
310 .user = OCP_USER_MPU,
311 };
312
313 /* l3_main_1 slave ports */
314 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
315 &omap44xx_dsp__l3_main_1,
316 &omap44xx_dss__l3_main_1,
317 &omap44xx_l3_main_2__l3_main_1,
318 &omap44xx_l4_cfg__l3_main_1,
319 &omap44xx_mmc1__l3_main_1,
320 &omap44xx_mmc2__l3_main_1,
321 &omap44xx_mpu__l3_main_1,
322 };
323
324 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
325 .name = "l3_main_1",
326 .class = &omap44xx_l3_hwmod_class,
327 .clkdm_name = "l3_1_clkdm",
328 .mpu_irqs = omap44xx_l3_main_1_irqs,
329 .prcm = {
330 .omap4 = {
331 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
332 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
333 },
334 },
335 .slaves = omap44xx_l3_main_1_slaves,
336 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
337 };
338
339 /* l3_main_2 */
340 /* dma_system -> l3_main_2 */
341 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
342 .master = &omap44xx_dma_system_hwmod,
343 .slave = &omap44xx_l3_main_2_hwmod,
344 .clk = "l3_div_ck",
345 .user = OCP_USER_MPU | OCP_USER_SDMA,
346 };
347
348 /* hsi -> l3_main_2 */
349 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
350 .master = &omap44xx_hsi_hwmod,
351 .slave = &omap44xx_l3_main_2_hwmod,
352 .clk = "l3_div_ck",
353 .user = OCP_USER_MPU | OCP_USER_SDMA,
354 };
355
356 /* ipu -> l3_main_2 */
357 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
358 .master = &omap44xx_ipu_hwmod,
359 .slave = &omap44xx_l3_main_2_hwmod,
360 .clk = "l3_div_ck",
361 .user = OCP_USER_MPU | OCP_USER_SDMA,
362 };
363
364 /* iss -> l3_main_2 */
365 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
366 .master = &omap44xx_iss_hwmod,
367 .slave = &omap44xx_l3_main_2_hwmod,
368 .clk = "l3_div_ck",
369 .user = OCP_USER_MPU | OCP_USER_SDMA,
370 };
371
372 /* iva -> l3_main_2 */
373 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
374 .master = &omap44xx_iva_hwmod,
375 .slave = &omap44xx_l3_main_2_hwmod,
376 .clk = "l3_div_ck",
377 .user = OCP_USER_MPU | OCP_USER_SDMA,
378 };
379
380 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
381 {
382 .pa_start = 0x44800000,
383 .pa_end = 0x44801fff,
384 .flags = ADDR_TYPE_RT
385 },
386 { }
387 };
388
389 /* l3_main_1 -> l3_main_2 */
390 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
391 .master = &omap44xx_l3_main_1_hwmod,
392 .slave = &omap44xx_l3_main_2_hwmod,
393 .clk = "l3_div_ck",
394 .addr = omap44xx_l3_main_2_addrs,
395 .user = OCP_USER_MPU,
396 };
397
398 /* l4_cfg -> l3_main_2 */
399 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
400 .master = &omap44xx_l4_cfg_hwmod,
401 .slave = &omap44xx_l3_main_2_hwmod,
402 .clk = "l4_div_ck",
403 .user = OCP_USER_MPU | OCP_USER_SDMA,
404 };
405
406 /* usb_otg_hs -> l3_main_2 */
407 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
408 .master = &omap44xx_usb_otg_hs_hwmod,
409 .slave = &omap44xx_l3_main_2_hwmod,
410 .clk = "l3_div_ck",
411 .user = OCP_USER_MPU | OCP_USER_SDMA,
412 };
413
414 /* l3_main_2 slave ports */
415 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
416 &omap44xx_dma_system__l3_main_2,
417 &omap44xx_hsi__l3_main_2,
418 &omap44xx_ipu__l3_main_2,
419 &omap44xx_iss__l3_main_2,
420 &omap44xx_iva__l3_main_2,
421 &omap44xx_l3_main_1__l3_main_2,
422 &omap44xx_l4_cfg__l3_main_2,
423 &omap44xx_usb_otg_hs__l3_main_2,
424 };
425
426 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
427 .name = "l3_main_2",
428 .class = &omap44xx_l3_hwmod_class,
429 .clkdm_name = "l3_2_clkdm",
430 .prcm = {
431 .omap4 = {
432 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
433 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
434 },
435 },
436 .slaves = omap44xx_l3_main_2_slaves,
437 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
438 };
439
440 /* l3_main_3 */
441 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
442 {
443 .pa_start = 0x45000000,
444 .pa_end = 0x45000fff,
445 .flags = ADDR_TYPE_RT
446 },
447 { }
448 };
449
450 /* l3_main_1 -> l3_main_3 */
451 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
452 .master = &omap44xx_l3_main_1_hwmod,
453 .slave = &omap44xx_l3_main_3_hwmod,
454 .clk = "l3_div_ck",
455 .addr = omap44xx_l3_main_3_addrs,
456 .user = OCP_USER_MPU,
457 };
458
459 /* l3_main_2 -> l3_main_3 */
460 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
461 .master = &omap44xx_l3_main_2_hwmod,
462 .slave = &omap44xx_l3_main_3_hwmod,
463 .clk = "l3_div_ck",
464 .user = OCP_USER_MPU | OCP_USER_SDMA,
465 };
466
467 /* l4_cfg -> l3_main_3 */
468 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
469 .master = &omap44xx_l4_cfg_hwmod,
470 .slave = &omap44xx_l3_main_3_hwmod,
471 .clk = "l4_div_ck",
472 .user = OCP_USER_MPU | OCP_USER_SDMA,
473 };
474
475 /* l3_main_3 slave ports */
476 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
477 &omap44xx_l3_main_1__l3_main_3,
478 &omap44xx_l3_main_2__l3_main_3,
479 &omap44xx_l4_cfg__l3_main_3,
480 };
481
482 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
483 .name = "l3_main_3",
484 .class = &omap44xx_l3_hwmod_class,
485 .clkdm_name = "l3_instr_clkdm",
486 .prcm = {
487 .omap4 = {
488 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
489 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
490 .modulemode = MODULEMODE_HWCTRL,
491 },
492 },
493 .slaves = omap44xx_l3_main_3_slaves,
494 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
495 };
496
497 /*
498 * 'l4' class
499 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
500 */
501 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
502 .name = "l4",
503 };
504
505 /* l4_abe */
506 /* aess -> l4_abe */
507 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
508 .master = &omap44xx_aess_hwmod,
509 .slave = &omap44xx_l4_abe_hwmod,
510 .clk = "ocp_abe_iclk",
511 .user = OCP_USER_MPU | OCP_USER_SDMA,
512 };
513
514 /* dsp -> l4_abe */
515 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
516 .master = &omap44xx_dsp_hwmod,
517 .slave = &omap44xx_l4_abe_hwmod,
518 .clk = "ocp_abe_iclk",
519 .user = OCP_USER_MPU | OCP_USER_SDMA,
520 };
521
522 /* l3_main_1 -> l4_abe */
523 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
524 .master = &omap44xx_l3_main_1_hwmod,
525 .slave = &omap44xx_l4_abe_hwmod,
526 .clk = "l3_div_ck",
527 .user = OCP_USER_MPU | OCP_USER_SDMA,
528 };
529
530 /* mpu -> l4_abe */
531 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
532 .master = &omap44xx_mpu_hwmod,
533 .slave = &omap44xx_l4_abe_hwmod,
534 .clk = "ocp_abe_iclk",
535 .user = OCP_USER_MPU | OCP_USER_SDMA,
536 };
537
538 /* l4_abe slave ports */
539 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
540 &omap44xx_aess__l4_abe,
541 &omap44xx_dsp__l4_abe,
542 &omap44xx_l3_main_1__l4_abe,
543 &omap44xx_mpu__l4_abe,
544 };
545
546 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
547 .name = "l4_abe",
548 .class = &omap44xx_l4_hwmod_class,
549 .clkdm_name = "abe_clkdm",
550 .prcm = {
551 .omap4 = {
552 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
553 },
554 },
555 .slaves = omap44xx_l4_abe_slaves,
556 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
557 };
558
559 /* l4_cfg */
560 /* l3_main_1 -> l4_cfg */
561 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
562 .master = &omap44xx_l3_main_1_hwmod,
563 .slave = &omap44xx_l4_cfg_hwmod,
564 .clk = "l3_div_ck",
565 .user = OCP_USER_MPU | OCP_USER_SDMA,
566 };
567
568 /* l4_cfg slave ports */
569 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
570 &omap44xx_l3_main_1__l4_cfg,
571 };
572
573 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
574 .name = "l4_cfg",
575 .class = &omap44xx_l4_hwmod_class,
576 .clkdm_name = "l4_cfg_clkdm",
577 .prcm = {
578 .omap4 = {
579 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
580 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
581 },
582 },
583 .slaves = omap44xx_l4_cfg_slaves,
584 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
585 };
586
587 /* l4_per */
588 /* l3_main_2 -> l4_per */
589 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
590 .master = &omap44xx_l3_main_2_hwmod,
591 .slave = &omap44xx_l4_per_hwmod,
592 .clk = "l3_div_ck",
593 .user = OCP_USER_MPU | OCP_USER_SDMA,
594 };
595
596 /* l4_per slave ports */
597 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
598 &omap44xx_l3_main_2__l4_per,
599 };
600
601 static struct omap_hwmod omap44xx_l4_per_hwmod = {
602 .name = "l4_per",
603 .class = &omap44xx_l4_hwmod_class,
604 .clkdm_name = "l4_per_clkdm",
605 .prcm = {
606 .omap4 = {
607 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
608 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
609 },
610 },
611 .slaves = omap44xx_l4_per_slaves,
612 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
613 };
614
615 /* l4_wkup */
616 /* l4_cfg -> l4_wkup */
617 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
618 .master = &omap44xx_l4_cfg_hwmod,
619 .slave = &omap44xx_l4_wkup_hwmod,
620 .clk = "l4_div_ck",
621 .user = OCP_USER_MPU | OCP_USER_SDMA,
622 };
623
624 /* l4_wkup slave ports */
625 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
626 &omap44xx_l4_cfg__l4_wkup,
627 };
628
629 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
630 .name = "l4_wkup",
631 .class = &omap44xx_l4_hwmod_class,
632 .clkdm_name = "l4_wkup_clkdm",
633 .prcm = {
634 .omap4 = {
635 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
636 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
637 },
638 },
639 .slaves = omap44xx_l4_wkup_slaves,
640 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
641 };
642
643 /*
644 * 'mpu_bus' class
645 * instance(s): mpu_private
646 */
647 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
648 .name = "mpu_bus",
649 };
650
651 /* mpu_private */
652 /* mpu -> mpu_private */
653 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
654 .master = &omap44xx_mpu_hwmod,
655 .slave = &omap44xx_mpu_private_hwmod,
656 .clk = "l3_div_ck",
657 .user = OCP_USER_MPU | OCP_USER_SDMA,
658 };
659
660 /* mpu_private slave ports */
661 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
662 &omap44xx_mpu__mpu_private,
663 };
664
665 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
666 .name = "mpu_private",
667 .class = &omap44xx_mpu_bus_hwmod_class,
668 .clkdm_name = "mpuss_clkdm",
669 .slaves = omap44xx_mpu_private_slaves,
670 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
671 };
672
673 /*
674 * Modules omap_hwmod structures
675 *
676 * The following IPs are excluded for the moment because:
677 * - They do not need an explicit SW control using omap_hwmod API.
678 * - They still need to be validated with the driver
679 * properly adapted to omap_hwmod / omap_device
680 *
681 * c2c
682 * c2c_target_fw
683 * cm_core
684 * cm_core_aon
685 * ctrl_module_core
686 * ctrl_module_pad_core
687 * ctrl_module_pad_wkup
688 * ctrl_module_wkup
689 * debugss
690 * efuse_ctrl_cust
691 * efuse_ctrl_std
692 * elm
693 * emif1
694 * emif2
695 * fdif
696 * gpmc
697 * gpu
698 * hdq1w
699 * mcasp
700 * mpu_c0
701 * mpu_c1
702 * ocmc_ram
703 * ocp2scp_usb_phy
704 * ocp_wp_noc
705 * prcm_mpu
706 * prm
707 * scrm
708 * sl2if
709 * slimbus1
710 * slimbus2
711 * usb_host_fs
712 * usb_host_hs
713 * usb_phy_cm
714 * usb_tll_hs
715 * usim
716 */
717
718 /*
719 * 'aess' class
720 * audio engine sub system
721 */
722
723 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
724 .rev_offs = 0x0000,
725 .sysc_offs = 0x0010,
726 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
727 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
728 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
729 MSTANDBY_SMART_WKUP),
730 .sysc_fields = &omap_hwmod_sysc_type2,
731 };
732
733 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
734 .name = "aess",
735 .sysc = &omap44xx_aess_sysc,
736 };
737
738 /* aess */
739 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
740 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
741 { .irq = -1 }
742 };
743
744 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
745 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
746 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
747 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
748 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
749 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
750 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
751 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
752 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
753 { .dma_req = -1 }
754 };
755
756 /* aess master ports */
757 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
758 &omap44xx_aess__l4_abe,
759 };
760
761 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
762 {
763 .pa_start = 0x401f1000,
764 .pa_end = 0x401f13ff,
765 .flags = ADDR_TYPE_RT
766 },
767 { }
768 };
769
770 /* l4_abe -> aess */
771 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
772 .master = &omap44xx_l4_abe_hwmod,
773 .slave = &omap44xx_aess_hwmod,
774 .clk = "ocp_abe_iclk",
775 .addr = omap44xx_aess_addrs,
776 .user = OCP_USER_MPU,
777 };
778
779 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
780 {
781 .pa_start = 0x490f1000,
782 .pa_end = 0x490f13ff,
783 .flags = ADDR_TYPE_RT
784 },
785 { }
786 };
787
788 /* l4_abe -> aess (dma) */
789 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
790 .master = &omap44xx_l4_abe_hwmod,
791 .slave = &omap44xx_aess_hwmod,
792 .clk = "ocp_abe_iclk",
793 .addr = omap44xx_aess_dma_addrs,
794 .user = OCP_USER_SDMA,
795 };
796
797 /* aess slave ports */
798 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
799 &omap44xx_l4_abe__aess,
800 &omap44xx_l4_abe__aess_dma,
801 };
802
803 static struct omap_hwmod omap44xx_aess_hwmod = {
804 .name = "aess",
805 .class = &omap44xx_aess_hwmod_class,
806 .clkdm_name = "abe_clkdm",
807 .mpu_irqs = omap44xx_aess_irqs,
808 .sdma_reqs = omap44xx_aess_sdma_reqs,
809 .main_clk = "aess_fck",
810 .prcm = {
811 .omap4 = {
812 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
813 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
814 .modulemode = MODULEMODE_SWCTRL,
815 },
816 },
817 .slaves = omap44xx_aess_slaves,
818 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
819 .masters = omap44xx_aess_masters,
820 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
821 };
822
823 /*
824 * 'bandgap' class
825 * bangap reference for ldo regulators
826 */
827
828 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
829 .name = "bandgap",
830 };
831
832 /* bandgap */
833 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
834 { .role = "fclk", .clk = "bandgap_fclk" },
835 };
836
837 static struct omap_hwmod omap44xx_bandgap_hwmod = {
838 .name = "bandgap",
839 .class = &omap44xx_bandgap_hwmod_class,
840 .clkdm_name = "l4_wkup_clkdm",
841 .prcm = {
842 .omap4 = {
843 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
844 },
845 },
846 .opt_clks = bandgap_opt_clks,
847 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
848 };
849
850 /*
851 * 'counter' class
852 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
853 */
854
855 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
856 .rev_offs = 0x0000,
857 .sysc_offs = 0x0004,
858 .sysc_flags = SYSC_HAS_SIDLEMODE,
859 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
860 SIDLE_SMART_WKUP),
861 .sysc_fields = &omap_hwmod_sysc_type1,
862 };
863
864 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
865 .name = "counter",
866 .sysc = &omap44xx_counter_sysc,
867 };
868
869 /* counter_32k */
870 static struct omap_hwmod omap44xx_counter_32k_hwmod;
871 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
872 {
873 .pa_start = 0x4a304000,
874 .pa_end = 0x4a30401f,
875 .flags = ADDR_TYPE_RT
876 },
877 { }
878 };
879
880 /* l4_wkup -> counter_32k */
881 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
882 .master = &omap44xx_l4_wkup_hwmod,
883 .slave = &omap44xx_counter_32k_hwmod,
884 .clk = "l4_wkup_clk_mux_ck",
885 .addr = omap44xx_counter_32k_addrs,
886 .user = OCP_USER_MPU | OCP_USER_SDMA,
887 };
888
889 /* counter_32k slave ports */
890 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
891 &omap44xx_l4_wkup__counter_32k,
892 };
893
894 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
895 .name = "counter_32k",
896 .class = &omap44xx_counter_hwmod_class,
897 .clkdm_name = "l4_wkup_clkdm",
898 .flags = HWMOD_SWSUP_SIDLE,
899 .main_clk = "sys_32k_ck",
900 .prcm = {
901 .omap4 = {
902 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
903 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
904 },
905 },
906 .slaves = omap44xx_counter_32k_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
908 };
909
910 /*
911 * 'dma' class
912 * dma controller for data exchange between memory to memory (i.e. internal or
913 * external memory) and gp peripherals to memory or memory to gp peripherals
914 */
915
916 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
917 .rev_offs = 0x0000,
918 .sysc_offs = 0x002c,
919 .syss_offs = 0x0028,
920 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
921 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
922 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
923 SYSS_HAS_RESET_STATUS),
924 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
925 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
926 .sysc_fields = &omap_hwmod_sysc_type1,
927 };
928
929 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
930 .name = "dma",
931 .sysc = &omap44xx_dma_sysc,
932 };
933
934 /* dma dev_attr */
935 static struct omap_dma_dev_attr dma_dev_attr = {
936 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
937 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
938 .lch_count = 32,
939 };
940
941 /* dma_system */
942 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
943 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
944 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
945 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
946 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
947 { .irq = -1 }
948 };
949
950 /* dma_system master ports */
951 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
952 &omap44xx_dma_system__l3_main_2,
953 };
954
955 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
956 {
957 .pa_start = 0x4a056000,
958 .pa_end = 0x4a056fff,
959 .flags = ADDR_TYPE_RT
960 },
961 { }
962 };
963
964 /* l4_cfg -> dma_system */
965 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
966 .master = &omap44xx_l4_cfg_hwmod,
967 .slave = &omap44xx_dma_system_hwmod,
968 .clk = "l4_div_ck",
969 .addr = omap44xx_dma_system_addrs,
970 .user = OCP_USER_MPU | OCP_USER_SDMA,
971 };
972
973 /* dma_system slave ports */
974 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
975 &omap44xx_l4_cfg__dma_system,
976 };
977
978 static struct omap_hwmod omap44xx_dma_system_hwmod = {
979 .name = "dma_system",
980 .class = &omap44xx_dma_hwmod_class,
981 .clkdm_name = "l3_dma_clkdm",
982 .mpu_irqs = omap44xx_dma_system_irqs,
983 .main_clk = "l3_div_ck",
984 .prcm = {
985 .omap4 = {
986 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
987 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
988 },
989 },
990 .dev_attr = &dma_dev_attr,
991 .slaves = omap44xx_dma_system_slaves,
992 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
993 .masters = omap44xx_dma_system_masters,
994 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
995 };
996
997 /*
998 * 'dmic' class
999 * digital microphone controller
1000 */
1001
1002 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1003 .rev_offs = 0x0000,
1004 .sysc_offs = 0x0010,
1005 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1006 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1007 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1008 SIDLE_SMART_WKUP),
1009 .sysc_fields = &omap_hwmod_sysc_type2,
1010 };
1011
1012 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1013 .name = "dmic",
1014 .sysc = &omap44xx_dmic_sysc,
1015 };
1016
1017 /* dmic */
1018 static struct omap_hwmod omap44xx_dmic_hwmod;
1019 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1020 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1021 { .irq = -1 }
1022 };
1023
1024 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1025 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1026 { .dma_req = -1 }
1027 };
1028
1029 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1030 {
1031 .pa_start = 0x4012e000,
1032 .pa_end = 0x4012e07f,
1033 .flags = ADDR_TYPE_RT
1034 },
1035 { }
1036 };
1037
1038 /* l4_abe -> dmic */
1039 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1040 .master = &omap44xx_l4_abe_hwmod,
1041 .slave = &omap44xx_dmic_hwmod,
1042 .clk = "ocp_abe_iclk",
1043 .addr = omap44xx_dmic_addrs,
1044 .user = OCP_USER_MPU,
1045 };
1046
1047 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1048 {
1049 .pa_start = 0x4902e000,
1050 .pa_end = 0x4902e07f,
1051 .flags = ADDR_TYPE_RT
1052 },
1053 { }
1054 };
1055
1056 /* l4_abe -> dmic (dma) */
1057 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1058 .master = &omap44xx_l4_abe_hwmod,
1059 .slave = &omap44xx_dmic_hwmod,
1060 .clk = "ocp_abe_iclk",
1061 .addr = omap44xx_dmic_dma_addrs,
1062 .user = OCP_USER_SDMA,
1063 };
1064
1065 /* dmic slave ports */
1066 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1067 &omap44xx_l4_abe__dmic,
1068 &omap44xx_l4_abe__dmic_dma,
1069 };
1070
1071 static struct omap_hwmod omap44xx_dmic_hwmod = {
1072 .name = "dmic",
1073 .class = &omap44xx_dmic_hwmod_class,
1074 .clkdm_name = "abe_clkdm",
1075 .mpu_irqs = omap44xx_dmic_irqs,
1076 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1077 .main_clk = "dmic_fck",
1078 .prcm = {
1079 .omap4 = {
1080 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1081 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1082 .modulemode = MODULEMODE_SWCTRL,
1083 },
1084 },
1085 .slaves = omap44xx_dmic_slaves,
1086 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1087 };
1088
1089 /*
1090 * 'dsp' class
1091 * dsp sub-system
1092 */
1093
1094 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1095 .name = "dsp",
1096 };
1097
1098 /* dsp */
1099 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1100 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1101 { .irq = -1 }
1102 };
1103
1104 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1105 { .name = "mmu_cache", .rst_shift = 1 },
1106 };
1107
1108 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1109 { .name = "dsp", .rst_shift = 0 },
1110 };
1111
1112 /* dsp -> iva */
1113 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1114 .master = &omap44xx_dsp_hwmod,
1115 .slave = &omap44xx_iva_hwmod,
1116 .clk = "dpll_iva_m5x2_ck",
1117 };
1118
1119 /* dsp master ports */
1120 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1121 &omap44xx_dsp__l3_main_1,
1122 &omap44xx_dsp__l4_abe,
1123 &omap44xx_dsp__iva,
1124 };
1125
1126 /* l4_cfg -> dsp */
1127 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1128 .master = &omap44xx_l4_cfg_hwmod,
1129 .slave = &omap44xx_dsp_hwmod,
1130 .clk = "l4_div_ck",
1131 .user = OCP_USER_MPU | OCP_USER_SDMA,
1132 };
1133
1134 /* dsp slave ports */
1135 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1136 &omap44xx_l4_cfg__dsp,
1137 };
1138
1139 /* Pseudo hwmod for reset control purpose only */
1140 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1141 .name = "dsp_c0",
1142 .class = &omap44xx_dsp_hwmod_class,
1143 .clkdm_name = "tesla_clkdm",
1144 .flags = HWMOD_INIT_NO_RESET,
1145 .rst_lines = omap44xx_dsp_c0_resets,
1146 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1147 .prcm = {
1148 .omap4 = {
1149 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1150 },
1151 },
1152 };
1153
1154 static struct omap_hwmod omap44xx_dsp_hwmod = {
1155 .name = "dsp",
1156 .class = &omap44xx_dsp_hwmod_class,
1157 .clkdm_name = "tesla_clkdm",
1158 .mpu_irqs = omap44xx_dsp_irqs,
1159 .rst_lines = omap44xx_dsp_resets,
1160 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1161 .main_clk = "dsp_fck",
1162 .prcm = {
1163 .omap4 = {
1164 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1165 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1166 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1167 .modulemode = MODULEMODE_HWCTRL,
1168 },
1169 },
1170 .slaves = omap44xx_dsp_slaves,
1171 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1172 .masters = omap44xx_dsp_masters,
1173 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1174 };
1175
1176 /*
1177 * 'dss' class
1178 * display sub-system
1179 */
1180
1181 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1182 .rev_offs = 0x0000,
1183 .syss_offs = 0x0014,
1184 .sysc_flags = SYSS_HAS_RESET_STATUS,
1185 };
1186
1187 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1188 .name = "dss",
1189 .sysc = &omap44xx_dss_sysc,
1190 };
1191
1192 /* dss */
1193 /* dss master ports */
1194 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1195 &omap44xx_dss__l3_main_1,
1196 };
1197
1198 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1199 {
1200 .pa_start = 0x58000000,
1201 .pa_end = 0x5800007f,
1202 .flags = ADDR_TYPE_RT
1203 },
1204 { }
1205 };
1206
1207 /* l3_main_2 -> dss */
1208 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1209 .master = &omap44xx_l3_main_2_hwmod,
1210 .slave = &omap44xx_dss_hwmod,
1211 .clk = "dss_fck",
1212 .addr = omap44xx_dss_dma_addrs,
1213 .user = OCP_USER_SDMA,
1214 };
1215
1216 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1217 {
1218 .pa_start = 0x48040000,
1219 .pa_end = 0x4804007f,
1220 .flags = ADDR_TYPE_RT
1221 },
1222 { }
1223 };
1224
1225 /* l4_per -> dss */
1226 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1227 .master = &omap44xx_l4_per_hwmod,
1228 .slave = &omap44xx_dss_hwmod,
1229 .clk = "l4_div_ck",
1230 .addr = omap44xx_dss_addrs,
1231 .user = OCP_USER_MPU,
1232 };
1233
1234 /* dss slave ports */
1235 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1236 &omap44xx_l3_main_2__dss,
1237 &omap44xx_l4_per__dss,
1238 };
1239
1240 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1241 { .role = "sys_clk", .clk = "dss_sys_clk" },
1242 { .role = "tv_clk", .clk = "dss_tv_clk" },
1243 { .role = "dss_clk", .clk = "dss_dss_clk" },
1244 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1245 };
1246
1247 static struct omap_hwmod omap44xx_dss_hwmod = {
1248 .name = "dss_core",
1249 .class = &omap44xx_dss_hwmod_class,
1250 .clkdm_name = "l3_dss_clkdm",
1251 .main_clk = "dss_dss_clk",
1252 .prcm = {
1253 .omap4 = {
1254 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1255 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1256 },
1257 },
1258 .opt_clks = dss_opt_clks,
1259 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1260 .slaves = omap44xx_dss_slaves,
1261 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1262 .masters = omap44xx_dss_masters,
1263 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1264 };
1265
1266 /*
1267 * 'dispc' class
1268 * display controller
1269 */
1270
1271 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1272 .rev_offs = 0x0000,
1273 .sysc_offs = 0x0010,
1274 .syss_offs = 0x0014,
1275 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1276 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1277 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1278 SYSS_HAS_RESET_STATUS),
1279 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1280 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1281 .sysc_fields = &omap_hwmod_sysc_type1,
1282 };
1283
1284 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1285 .name = "dispc",
1286 .sysc = &omap44xx_dispc_sysc,
1287 };
1288
1289 /* dss_dispc */
1290 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1291 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1292 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1293 { .irq = -1 }
1294 };
1295
1296 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1297 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1298 { .dma_req = -1 }
1299 };
1300
1301 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1302 {
1303 .pa_start = 0x58001000,
1304 .pa_end = 0x58001fff,
1305 .flags = ADDR_TYPE_RT
1306 },
1307 { }
1308 };
1309
1310 /* l3_main_2 -> dss_dispc */
1311 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1312 .master = &omap44xx_l3_main_2_hwmod,
1313 .slave = &omap44xx_dss_dispc_hwmod,
1314 .clk = "dss_fck",
1315 .addr = omap44xx_dss_dispc_dma_addrs,
1316 .user = OCP_USER_SDMA,
1317 };
1318
1319 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1320 {
1321 .pa_start = 0x48041000,
1322 .pa_end = 0x48041fff,
1323 .flags = ADDR_TYPE_RT
1324 },
1325 { }
1326 };
1327
1328 /* l4_per -> dss_dispc */
1329 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1330 .master = &omap44xx_l4_per_hwmod,
1331 .slave = &omap44xx_dss_dispc_hwmod,
1332 .clk = "l4_div_ck",
1333 .addr = omap44xx_dss_dispc_addrs,
1334 .user = OCP_USER_MPU,
1335 };
1336
1337 /* dss_dispc slave ports */
1338 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1339 &omap44xx_l3_main_2__dss_dispc,
1340 &omap44xx_l4_per__dss_dispc,
1341 };
1342
1343 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1344 { .role = "sys_clk", .clk = "dss_sys_clk" },
1345 { .role = "tv_clk", .clk = "dss_tv_clk" },
1346 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1347 };
1348
1349 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1350 .name = "dss_dispc",
1351 .class = &omap44xx_dispc_hwmod_class,
1352 .clkdm_name = "l3_dss_clkdm",
1353 .mpu_irqs = omap44xx_dss_dispc_irqs,
1354 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1355 .main_clk = "dss_dss_clk",
1356 .prcm = {
1357 .omap4 = {
1358 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1359 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1360 },
1361 },
1362 .opt_clks = dss_dispc_opt_clks,
1363 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
1364 .slaves = omap44xx_dss_dispc_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1366 };
1367
1368 /*
1369 * 'dsi' class
1370 * display serial interface controller
1371 */
1372
1373 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1374 .rev_offs = 0x0000,
1375 .sysc_offs = 0x0010,
1376 .syss_offs = 0x0014,
1377 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1378 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1379 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1380 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1381 .sysc_fields = &omap_hwmod_sysc_type1,
1382 };
1383
1384 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1385 .name = "dsi",
1386 .sysc = &omap44xx_dsi_sysc,
1387 };
1388
1389 /* dss_dsi1 */
1390 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1391 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1392 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1393 { .irq = -1 }
1394 };
1395
1396 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1397 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1398 { .dma_req = -1 }
1399 };
1400
1401 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1402 {
1403 .pa_start = 0x58004000,
1404 .pa_end = 0x580041ff,
1405 .flags = ADDR_TYPE_RT
1406 },
1407 { }
1408 };
1409
1410 /* l3_main_2 -> dss_dsi1 */
1411 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1412 .master = &omap44xx_l3_main_2_hwmod,
1413 .slave = &omap44xx_dss_dsi1_hwmod,
1414 .clk = "dss_fck",
1415 .addr = omap44xx_dss_dsi1_dma_addrs,
1416 .user = OCP_USER_SDMA,
1417 };
1418
1419 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1420 {
1421 .pa_start = 0x48044000,
1422 .pa_end = 0x480441ff,
1423 .flags = ADDR_TYPE_RT
1424 },
1425 { }
1426 };
1427
1428 /* l4_per -> dss_dsi1 */
1429 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1430 .master = &omap44xx_l4_per_hwmod,
1431 .slave = &omap44xx_dss_dsi1_hwmod,
1432 .clk = "l4_div_ck",
1433 .addr = omap44xx_dss_dsi1_addrs,
1434 .user = OCP_USER_MPU,
1435 };
1436
1437 /* dss_dsi1 slave ports */
1438 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1439 &omap44xx_l3_main_2__dss_dsi1,
1440 &omap44xx_l4_per__dss_dsi1,
1441 };
1442
1443 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1444 { .role = "sys_clk", .clk = "dss_sys_clk" },
1445 };
1446
1447 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1448 .name = "dss_dsi1",
1449 .class = &omap44xx_dsi_hwmod_class,
1450 .clkdm_name = "l3_dss_clkdm",
1451 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1452 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1453 .main_clk = "dss_dss_clk",
1454 .prcm = {
1455 .omap4 = {
1456 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1457 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1458 },
1459 },
1460 .opt_clks = dss_dsi1_opt_clks,
1461 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1462 .slaves = omap44xx_dss_dsi1_slaves,
1463 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1464 };
1465
1466 /* dss_dsi2 */
1467 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1468 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1469 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1470 { .irq = -1 }
1471 };
1472
1473 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1474 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1475 { .dma_req = -1 }
1476 };
1477
1478 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1479 {
1480 .pa_start = 0x58005000,
1481 .pa_end = 0x580051ff,
1482 .flags = ADDR_TYPE_RT
1483 },
1484 { }
1485 };
1486
1487 /* l3_main_2 -> dss_dsi2 */
1488 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1489 .master = &omap44xx_l3_main_2_hwmod,
1490 .slave = &omap44xx_dss_dsi2_hwmod,
1491 .clk = "dss_fck",
1492 .addr = omap44xx_dss_dsi2_dma_addrs,
1493 .user = OCP_USER_SDMA,
1494 };
1495
1496 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1497 {
1498 .pa_start = 0x48045000,
1499 .pa_end = 0x480451ff,
1500 .flags = ADDR_TYPE_RT
1501 },
1502 { }
1503 };
1504
1505 /* l4_per -> dss_dsi2 */
1506 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1507 .master = &omap44xx_l4_per_hwmod,
1508 .slave = &omap44xx_dss_dsi2_hwmod,
1509 .clk = "l4_div_ck",
1510 .addr = omap44xx_dss_dsi2_addrs,
1511 .user = OCP_USER_MPU,
1512 };
1513
1514 /* dss_dsi2 slave ports */
1515 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1516 &omap44xx_l3_main_2__dss_dsi2,
1517 &omap44xx_l4_per__dss_dsi2,
1518 };
1519
1520 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1521 { .role = "sys_clk", .clk = "dss_sys_clk" },
1522 };
1523
1524 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1525 .name = "dss_dsi2",
1526 .class = &omap44xx_dsi_hwmod_class,
1527 .clkdm_name = "l3_dss_clkdm",
1528 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1529 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1530 .main_clk = "dss_dss_clk",
1531 .prcm = {
1532 .omap4 = {
1533 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1534 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1535 },
1536 },
1537 .opt_clks = dss_dsi2_opt_clks,
1538 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1539 .slaves = omap44xx_dss_dsi2_slaves,
1540 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1541 };
1542
1543 /*
1544 * 'hdmi' class
1545 * hdmi controller
1546 */
1547
1548 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1549 .rev_offs = 0x0000,
1550 .sysc_offs = 0x0010,
1551 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1552 SYSC_HAS_SOFTRESET),
1553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1554 SIDLE_SMART_WKUP),
1555 .sysc_fields = &omap_hwmod_sysc_type2,
1556 };
1557
1558 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1559 .name = "hdmi",
1560 .sysc = &omap44xx_hdmi_sysc,
1561 };
1562
1563 /* dss_hdmi */
1564 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1565 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1566 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1567 { .irq = -1 }
1568 };
1569
1570 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1571 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1572 { .dma_req = -1 }
1573 };
1574
1575 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1576 {
1577 .pa_start = 0x58006000,
1578 .pa_end = 0x58006fff,
1579 .flags = ADDR_TYPE_RT
1580 },
1581 { }
1582 };
1583
1584 /* l3_main_2 -> dss_hdmi */
1585 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1586 .master = &omap44xx_l3_main_2_hwmod,
1587 .slave = &omap44xx_dss_hdmi_hwmod,
1588 .clk = "dss_fck",
1589 .addr = omap44xx_dss_hdmi_dma_addrs,
1590 .user = OCP_USER_SDMA,
1591 };
1592
1593 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1594 {
1595 .pa_start = 0x48046000,
1596 .pa_end = 0x48046fff,
1597 .flags = ADDR_TYPE_RT
1598 },
1599 { }
1600 };
1601
1602 /* l4_per -> dss_hdmi */
1603 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1604 .master = &omap44xx_l4_per_hwmod,
1605 .slave = &omap44xx_dss_hdmi_hwmod,
1606 .clk = "l4_div_ck",
1607 .addr = omap44xx_dss_hdmi_addrs,
1608 .user = OCP_USER_MPU,
1609 };
1610
1611 /* dss_hdmi slave ports */
1612 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1613 &omap44xx_l3_main_2__dss_hdmi,
1614 &omap44xx_l4_per__dss_hdmi,
1615 };
1616
1617 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1618 { .role = "sys_clk", .clk = "dss_sys_clk" },
1619 };
1620
1621 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1622 .name = "dss_hdmi",
1623 .class = &omap44xx_hdmi_hwmod_class,
1624 .clkdm_name = "l3_dss_clkdm",
1625 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1626 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1627 .main_clk = "dss_dss_clk",
1628 .prcm = {
1629 .omap4 = {
1630 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1631 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1632 },
1633 },
1634 .opt_clks = dss_hdmi_opt_clks,
1635 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1636 .slaves = omap44xx_dss_hdmi_slaves,
1637 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1638 };
1639
1640 /*
1641 * 'rfbi' class
1642 * remote frame buffer interface
1643 */
1644
1645 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1646 .rev_offs = 0x0000,
1647 .sysc_offs = 0x0010,
1648 .syss_offs = 0x0014,
1649 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1650 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1651 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1652 .sysc_fields = &omap_hwmod_sysc_type1,
1653 };
1654
1655 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1656 .name = "rfbi",
1657 .sysc = &omap44xx_rfbi_sysc,
1658 };
1659
1660 /* dss_rfbi */
1661 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1662 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1663 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1664 { .dma_req = -1 }
1665 };
1666
1667 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1668 {
1669 .pa_start = 0x58002000,
1670 .pa_end = 0x580020ff,
1671 .flags = ADDR_TYPE_RT
1672 },
1673 { }
1674 };
1675
1676 /* l3_main_2 -> dss_rfbi */
1677 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1678 .master = &omap44xx_l3_main_2_hwmod,
1679 .slave = &omap44xx_dss_rfbi_hwmod,
1680 .clk = "dss_fck",
1681 .addr = omap44xx_dss_rfbi_dma_addrs,
1682 .user = OCP_USER_SDMA,
1683 };
1684
1685 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1686 {
1687 .pa_start = 0x48042000,
1688 .pa_end = 0x480420ff,
1689 .flags = ADDR_TYPE_RT
1690 },
1691 { }
1692 };
1693
1694 /* l4_per -> dss_rfbi */
1695 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1696 .master = &omap44xx_l4_per_hwmod,
1697 .slave = &omap44xx_dss_rfbi_hwmod,
1698 .clk = "l4_div_ck",
1699 .addr = omap44xx_dss_rfbi_addrs,
1700 .user = OCP_USER_MPU,
1701 };
1702
1703 /* dss_rfbi slave ports */
1704 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1705 &omap44xx_l3_main_2__dss_rfbi,
1706 &omap44xx_l4_per__dss_rfbi,
1707 };
1708
1709 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1710 { .role = "ick", .clk = "dss_fck" },
1711 };
1712
1713 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1714 .name = "dss_rfbi",
1715 .class = &omap44xx_rfbi_hwmod_class,
1716 .clkdm_name = "l3_dss_clkdm",
1717 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1718 .main_clk = "dss_dss_clk",
1719 .prcm = {
1720 .omap4 = {
1721 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1722 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1723 },
1724 },
1725 .opt_clks = dss_rfbi_opt_clks,
1726 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1727 .slaves = omap44xx_dss_rfbi_slaves,
1728 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1729 };
1730
1731 /*
1732 * 'venc' class
1733 * video encoder
1734 */
1735
1736 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1737 .name = "venc",
1738 };
1739
1740 /* dss_venc */
1741 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1742 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1743 {
1744 .pa_start = 0x58003000,
1745 .pa_end = 0x580030ff,
1746 .flags = ADDR_TYPE_RT
1747 },
1748 { }
1749 };
1750
1751 /* l3_main_2 -> dss_venc */
1752 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1753 .master = &omap44xx_l3_main_2_hwmod,
1754 .slave = &omap44xx_dss_venc_hwmod,
1755 .clk = "dss_fck",
1756 .addr = omap44xx_dss_venc_dma_addrs,
1757 .user = OCP_USER_SDMA,
1758 };
1759
1760 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1761 {
1762 .pa_start = 0x48043000,
1763 .pa_end = 0x480430ff,
1764 .flags = ADDR_TYPE_RT
1765 },
1766 { }
1767 };
1768
1769 /* l4_per -> dss_venc */
1770 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1771 .master = &omap44xx_l4_per_hwmod,
1772 .slave = &omap44xx_dss_venc_hwmod,
1773 .clk = "l4_div_ck",
1774 .addr = omap44xx_dss_venc_addrs,
1775 .user = OCP_USER_MPU,
1776 };
1777
1778 /* dss_venc slave ports */
1779 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1780 &omap44xx_l3_main_2__dss_venc,
1781 &omap44xx_l4_per__dss_venc,
1782 };
1783
1784 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1785 .name = "dss_venc",
1786 .class = &omap44xx_venc_hwmod_class,
1787 .clkdm_name = "l3_dss_clkdm",
1788 .main_clk = "dss_dss_clk",
1789 .prcm = {
1790 .omap4 = {
1791 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1792 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1793 },
1794 },
1795 .slaves = omap44xx_dss_venc_slaves,
1796 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1797 };
1798
1799 /*
1800 * 'gpio' class
1801 * general purpose io module
1802 */
1803
1804 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1805 .rev_offs = 0x0000,
1806 .sysc_offs = 0x0010,
1807 .syss_offs = 0x0114,
1808 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1809 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1810 SYSS_HAS_RESET_STATUS),
1811 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1812 SIDLE_SMART_WKUP),
1813 .sysc_fields = &omap_hwmod_sysc_type1,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1817 .name = "gpio",
1818 .sysc = &omap44xx_gpio_sysc,
1819 .rev = 2,
1820 };
1821
1822 /* gpio dev_attr */
1823 static struct omap_gpio_dev_attr gpio_dev_attr = {
1824 .bank_width = 32,
1825 .dbck_flag = true,
1826 };
1827
1828 /* gpio1 */
1829 static struct omap_hwmod omap44xx_gpio1_hwmod;
1830 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1831 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1832 { .irq = -1 }
1833 };
1834
1835 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1836 {
1837 .pa_start = 0x4a310000,
1838 .pa_end = 0x4a3101ff,
1839 .flags = ADDR_TYPE_RT
1840 },
1841 { }
1842 };
1843
1844 /* l4_wkup -> gpio1 */
1845 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1846 .master = &omap44xx_l4_wkup_hwmod,
1847 .slave = &omap44xx_gpio1_hwmod,
1848 .clk = "l4_wkup_clk_mux_ck",
1849 .addr = omap44xx_gpio1_addrs,
1850 .user = OCP_USER_MPU | OCP_USER_SDMA,
1851 };
1852
1853 /* gpio1 slave ports */
1854 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1855 &omap44xx_l4_wkup__gpio1,
1856 };
1857
1858 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1859 { .role = "dbclk", .clk = "gpio1_dbclk" },
1860 };
1861
1862 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1863 .name = "gpio1",
1864 .class = &omap44xx_gpio_hwmod_class,
1865 .clkdm_name = "l4_wkup_clkdm",
1866 .mpu_irqs = omap44xx_gpio1_irqs,
1867 .main_clk = "gpio1_ick",
1868 .prcm = {
1869 .omap4 = {
1870 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1871 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1872 .modulemode = MODULEMODE_HWCTRL,
1873 },
1874 },
1875 .opt_clks = gpio1_opt_clks,
1876 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1877 .dev_attr = &gpio_dev_attr,
1878 .slaves = omap44xx_gpio1_slaves,
1879 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1880 };
1881
1882 /* gpio2 */
1883 static struct omap_hwmod omap44xx_gpio2_hwmod;
1884 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1885 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1886 { .irq = -1 }
1887 };
1888
1889 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1890 {
1891 .pa_start = 0x48055000,
1892 .pa_end = 0x480551ff,
1893 .flags = ADDR_TYPE_RT
1894 },
1895 { }
1896 };
1897
1898 /* l4_per -> gpio2 */
1899 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1900 .master = &omap44xx_l4_per_hwmod,
1901 .slave = &omap44xx_gpio2_hwmod,
1902 .clk = "l4_div_ck",
1903 .addr = omap44xx_gpio2_addrs,
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905 };
1906
1907 /* gpio2 slave ports */
1908 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1909 &omap44xx_l4_per__gpio2,
1910 };
1911
1912 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1913 { .role = "dbclk", .clk = "gpio2_dbclk" },
1914 };
1915
1916 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1917 .name = "gpio2",
1918 .class = &omap44xx_gpio_hwmod_class,
1919 .clkdm_name = "l4_per_clkdm",
1920 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1921 .mpu_irqs = omap44xx_gpio2_irqs,
1922 .main_clk = "gpio2_ick",
1923 .prcm = {
1924 .omap4 = {
1925 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1926 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1927 .modulemode = MODULEMODE_HWCTRL,
1928 },
1929 },
1930 .opt_clks = gpio2_opt_clks,
1931 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1932 .dev_attr = &gpio_dev_attr,
1933 .slaves = omap44xx_gpio2_slaves,
1934 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1935 };
1936
1937 /* gpio3 */
1938 static struct omap_hwmod omap44xx_gpio3_hwmod;
1939 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1940 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1941 { .irq = -1 }
1942 };
1943
1944 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1945 {
1946 .pa_start = 0x48057000,
1947 .pa_end = 0x480571ff,
1948 .flags = ADDR_TYPE_RT
1949 },
1950 { }
1951 };
1952
1953 /* l4_per -> gpio3 */
1954 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1955 .master = &omap44xx_l4_per_hwmod,
1956 .slave = &omap44xx_gpio3_hwmod,
1957 .clk = "l4_div_ck",
1958 .addr = omap44xx_gpio3_addrs,
1959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1960 };
1961
1962 /* gpio3 slave ports */
1963 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1964 &omap44xx_l4_per__gpio3,
1965 };
1966
1967 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1968 { .role = "dbclk", .clk = "gpio3_dbclk" },
1969 };
1970
1971 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1972 .name = "gpio3",
1973 .class = &omap44xx_gpio_hwmod_class,
1974 .clkdm_name = "l4_per_clkdm",
1975 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1976 .mpu_irqs = omap44xx_gpio3_irqs,
1977 .main_clk = "gpio3_ick",
1978 .prcm = {
1979 .omap4 = {
1980 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1981 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1982 .modulemode = MODULEMODE_HWCTRL,
1983 },
1984 },
1985 .opt_clks = gpio3_opt_clks,
1986 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1987 .dev_attr = &gpio_dev_attr,
1988 .slaves = omap44xx_gpio3_slaves,
1989 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1990 };
1991
1992 /* gpio4 */
1993 static struct omap_hwmod omap44xx_gpio4_hwmod;
1994 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1995 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1996 { .irq = -1 }
1997 };
1998
1999 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2000 {
2001 .pa_start = 0x48059000,
2002 .pa_end = 0x480591ff,
2003 .flags = ADDR_TYPE_RT
2004 },
2005 { }
2006 };
2007
2008 /* l4_per -> gpio4 */
2009 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2010 .master = &omap44xx_l4_per_hwmod,
2011 .slave = &omap44xx_gpio4_hwmod,
2012 .clk = "l4_div_ck",
2013 .addr = omap44xx_gpio4_addrs,
2014 .user = OCP_USER_MPU | OCP_USER_SDMA,
2015 };
2016
2017 /* gpio4 slave ports */
2018 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2019 &omap44xx_l4_per__gpio4,
2020 };
2021
2022 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2023 { .role = "dbclk", .clk = "gpio4_dbclk" },
2024 };
2025
2026 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2027 .name = "gpio4",
2028 .class = &omap44xx_gpio_hwmod_class,
2029 .clkdm_name = "l4_per_clkdm",
2030 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2031 .mpu_irqs = omap44xx_gpio4_irqs,
2032 .main_clk = "gpio4_ick",
2033 .prcm = {
2034 .omap4 = {
2035 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2036 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2037 .modulemode = MODULEMODE_HWCTRL,
2038 },
2039 },
2040 .opt_clks = gpio4_opt_clks,
2041 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2042 .dev_attr = &gpio_dev_attr,
2043 .slaves = omap44xx_gpio4_slaves,
2044 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
2045 };
2046
2047 /* gpio5 */
2048 static struct omap_hwmod omap44xx_gpio5_hwmod;
2049 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2050 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2051 { .irq = -1 }
2052 };
2053
2054 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2055 {
2056 .pa_start = 0x4805b000,
2057 .pa_end = 0x4805b1ff,
2058 .flags = ADDR_TYPE_RT
2059 },
2060 { }
2061 };
2062
2063 /* l4_per -> gpio5 */
2064 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2065 .master = &omap44xx_l4_per_hwmod,
2066 .slave = &omap44xx_gpio5_hwmod,
2067 .clk = "l4_div_ck",
2068 .addr = omap44xx_gpio5_addrs,
2069 .user = OCP_USER_MPU | OCP_USER_SDMA,
2070 };
2071
2072 /* gpio5 slave ports */
2073 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2074 &omap44xx_l4_per__gpio5,
2075 };
2076
2077 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2078 { .role = "dbclk", .clk = "gpio5_dbclk" },
2079 };
2080
2081 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2082 .name = "gpio5",
2083 .class = &omap44xx_gpio_hwmod_class,
2084 .clkdm_name = "l4_per_clkdm",
2085 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2086 .mpu_irqs = omap44xx_gpio5_irqs,
2087 .main_clk = "gpio5_ick",
2088 .prcm = {
2089 .omap4 = {
2090 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2091 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2092 .modulemode = MODULEMODE_HWCTRL,
2093 },
2094 },
2095 .opt_clks = gpio5_opt_clks,
2096 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2097 .dev_attr = &gpio_dev_attr,
2098 .slaves = omap44xx_gpio5_slaves,
2099 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
2100 };
2101
2102 /* gpio6 */
2103 static struct omap_hwmod omap44xx_gpio6_hwmod;
2104 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2105 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2106 { .irq = -1 }
2107 };
2108
2109 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2110 {
2111 .pa_start = 0x4805d000,
2112 .pa_end = 0x4805d1ff,
2113 .flags = ADDR_TYPE_RT
2114 },
2115 { }
2116 };
2117
2118 /* l4_per -> gpio6 */
2119 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2120 .master = &omap44xx_l4_per_hwmod,
2121 .slave = &omap44xx_gpio6_hwmod,
2122 .clk = "l4_div_ck",
2123 .addr = omap44xx_gpio6_addrs,
2124 .user = OCP_USER_MPU | OCP_USER_SDMA,
2125 };
2126
2127 /* gpio6 slave ports */
2128 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2129 &omap44xx_l4_per__gpio6,
2130 };
2131
2132 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2133 { .role = "dbclk", .clk = "gpio6_dbclk" },
2134 };
2135
2136 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2137 .name = "gpio6",
2138 .class = &omap44xx_gpio_hwmod_class,
2139 .clkdm_name = "l4_per_clkdm",
2140 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2141 .mpu_irqs = omap44xx_gpio6_irqs,
2142 .main_clk = "gpio6_ick",
2143 .prcm = {
2144 .omap4 = {
2145 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2146 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2147 .modulemode = MODULEMODE_HWCTRL,
2148 },
2149 },
2150 .opt_clks = gpio6_opt_clks,
2151 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2152 .dev_attr = &gpio_dev_attr,
2153 .slaves = omap44xx_gpio6_slaves,
2154 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2155 };
2156
2157 /*
2158 * 'hsi' class
2159 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2160 * serial if)
2161 */
2162
2163 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2164 .rev_offs = 0x0000,
2165 .sysc_offs = 0x0010,
2166 .syss_offs = 0x0014,
2167 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2168 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2169 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2170 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2171 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2172 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2173 .sysc_fields = &omap_hwmod_sysc_type1,
2174 };
2175
2176 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2177 .name = "hsi",
2178 .sysc = &omap44xx_hsi_sysc,
2179 };
2180
2181 /* hsi */
2182 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2183 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2184 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2185 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2186 { .irq = -1 }
2187 };
2188
2189 /* hsi master ports */
2190 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2191 &omap44xx_hsi__l3_main_2,
2192 };
2193
2194 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2195 {
2196 .pa_start = 0x4a058000,
2197 .pa_end = 0x4a05bfff,
2198 .flags = ADDR_TYPE_RT
2199 },
2200 { }
2201 };
2202
2203 /* l4_cfg -> hsi */
2204 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2205 .master = &omap44xx_l4_cfg_hwmod,
2206 .slave = &omap44xx_hsi_hwmod,
2207 .clk = "l4_div_ck",
2208 .addr = omap44xx_hsi_addrs,
2209 .user = OCP_USER_MPU | OCP_USER_SDMA,
2210 };
2211
2212 /* hsi slave ports */
2213 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2214 &omap44xx_l4_cfg__hsi,
2215 };
2216
2217 static struct omap_hwmod omap44xx_hsi_hwmod = {
2218 .name = "hsi",
2219 .class = &omap44xx_hsi_hwmod_class,
2220 .clkdm_name = "l3_init_clkdm",
2221 .mpu_irqs = omap44xx_hsi_irqs,
2222 .main_clk = "hsi_fck",
2223 .prcm = {
2224 .omap4 = {
2225 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2226 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2227 .modulemode = MODULEMODE_HWCTRL,
2228 },
2229 },
2230 .slaves = omap44xx_hsi_slaves,
2231 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2232 .masters = omap44xx_hsi_masters,
2233 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2234 };
2235
2236 /*
2237 * 'i2c' class
2238 * multimaster high-speed i2c controller
2239 */
2240
2241 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2242 .sysc_offs = 0x0010,
2243 .syss_offs = 0x0090,
2244 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2245 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2246 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2247 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2248 SIDLE_SMART_WKUP),
2249 .sysc_fields = &omap_hwmod_sysc_type1,
2250 };
2251
2252 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2253 .name = "i2c",
2254 .sysc = &omap44xx_i2c_sysc,
2255 .rev = OMAP_I2C_IP_VERSION_2,
2256 .reset = &omap_i2c_reset,
2257 };
2258
2259 static struct omap_i2c_dev_attr i2c_dev_attr = {
2260 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2261 };
2262
2263 /* i2c1 */
2264 static struct omap_hwmod omap44xx_i2c1_hwmod;
2265 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2266 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2267 { .irq = -1 }
2268 };
2269
2270 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2271 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2272 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2273 { .dma_req = -1 }
2274 };
2275
2276 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2277 {
2278 .pa_start = 0x48070000,
2279 .pa_end = 0x480700ff,
2280 .flags = ADDR_TYPE_RT
2281 },
2282 { }
2283 };
2284
2285 /* l4_per -> i2c1 */
2286 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2287 .master = &omap44xx_l4_per_hwmod,
2288 .slave = &omap44xx_i2c1_hwmod,
2289 .clk = "l4_div_ck",
2290 .addr = omap44xx_i2c1_addrs,
2291 .user = OCP_USER_MPU | OCP_USER_SDMA,
2292 };
2293
2294 /* i2c1 slave ports */
2295 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2296 &omap44xx_l4_per__i2c1,
2297 };
2298
2299 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2300 .name = "i2c1",
2301 .class = &omap44xx_i2c_hwmod_class,
2302 .clkdm_name = "l4_per_clkdm",
2303 .flags = HWMOD_16BIT_REG,
2304 .mpu_irqs = omap44xx_i2c1_irqs,
2305 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2306 .main_clk = "i2c1_fck",
2307 .prcm = {
2308 .omap4 = {
2309 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2310 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2311 .modulemode = MODULEMODE_SWCTRL,
2312 },
2313 },
2314 .slaves = omap44xx_i2c1_slaves,
2315 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2316 .dev_attr = &i2c_dev_attr,
2317 };
2318
2319 /* i2c2 */
2320 static struct omap_hwmod omap44xx_i2c2_hwmod;
2321 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2322 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2323 { .irq = -1 }
2324 };
2325
2326 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2327 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2328 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2329 { .dma_req = -1 }
2330 };
2331
2332 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2333 {
2334 .pa_start = 0x48072000,
2335 .pa_end = 0x480720ff,
2336 .flags = ADDR_TYPE_RT
2337 },
2338 { }
2339 };
2340
2341 /* l4_per -> i2c2 */
2342 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2343 .master = &omap44xx_l4_per_hwmod,
2344 .slave = &omap44xx_i2c2_hwmod,
2345 .clk = "l4_div_ck",
2346 .addr = omap44xx_i2c2_addrs,
2347 .user = OCP_USER_MPU | OCP_USER_SDMA,
2348 };
2349
2350 /* i2c2 slave ports */
2351 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2352 &omap44xx_l4_per__i2c2,
2353 };
2354
2355 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2356 .name = "i2c2",
2357 .class = &omap44xx_i2c_hwmod_class,
2358 .clkdm_name = "l4_per_clkdm",
2359 .flags = HWMOD_16BIT_REG,
2360 .mpu_irqs = omap44xx_i2c2_irqs,
2361 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2362 .main_clk = "i2c2_fck",
2363 .prcm = {
2364 .omap4 = {
2365 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2366 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2367 .modulemode = MODULEMODE_SWCTRL,
2368 },
2369 },
2370 .slaves = omap44xx_i2c2_slaves,
2371 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2372 .dev_attr = &i2c_dev_attr,
2373 };
2374
2375 /* i2c3 */
2376 static struct omap_hwmod omap44xx_i2c3_hwmod;
2377 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2378 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2379 { .irq = -1 }
2380 };
2381
2382 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2383 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2384 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2385 { .dma_req = -1 }
2386 };
2387
2388 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2389 {
2390 .pa_start = 0x48060000,
2391 .pa_end = 0x480600ff,
2392 .flags = ADDR_TYPE_RT
2393 },
2394 { }
2395 };
2396
2397 /* l4_per -> i2c3 */
2398 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2399 .master = &omap44xx_l4_per_hwmod,
2400 .slave = &omap44xx_i2c3_hwmod,
2401 .clk = "l4_div_ck",
2402 .addr = omap44xx_i2c3_addrs,
2403 .user = OCP_USER_MPU | OCP_USER_SDMA,
2404 };
2405
2406 /* i2c3 slave ports */
2407 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2408 &omap44xx_l4_per__i2c3,
2409 };
2410
2411 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2412 .name = "i2c3",
2413 .class = &omap44xx_i2c_hwmod_class,
2414 .clkdm_name = "l4_per_clkdm",
2415 .flags = HWMOD_16BIT_REG,
2416 .mpu_irqs = omap44xx_i2c3_irqs,
2417 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2418 .main_clk = "i2c3_fck",
2419 .prcm = {
2420 .omap4 = {
2421 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2422 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2423 .modulemode = MODULEMODE_SWCTRL,
2424 },
2425 },
2426 .slaves = omap44xx_i2c3_slaves,
2427 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2428 .dev_attr = &i2c_dev_attr,
2429 };
2430
2431 /* i2c4 */
2432 static struct omap_hwmod omap44xx_i2c4_hwmod;
2433 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2434 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2435 { .irq = -1 }
2436 };
2437
2438 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2439 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2440 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2441 { .dma_req = -1 }
2442 };
2443
2444 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2445 {
2446 .pa_start = 0x48350000,
2447 .pa_end = 0x483500ff,
2448 .flags = ADDR_TYPE_RT
2449 },
2450 { }
2451 };
2452
2453 /* l4_per -> i2c4 */
2454 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2455 .master = &omap44xx_l4_per_hwmod,
2456 .slave = &omap44xx_i2c4_hwmod,
2457 .clk = "l4_div_ck",
2458 .addr = omap44xx_i2c4_addrs,
2459 .user = OCP_USER_MPU | OCP_USER_SDMA,
2460 };
2461
2462 /* i2c4 slave ports */
2463 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2464 &omap44xx_l4_per__i2c4,
2465 };
2466
2467 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2468 .name = "i2c4",
2469 .class = &omap44xx_i2c_hwmod_class,
2470 .clkdm_name = "l4_per_clkdm",
2471 .flags = HWMOD_16BIT_REG,
2472 .mpu_irqs = omap44xx_i2c4_irqs,
2473 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2474 .main_clk = "i2c4_fck",
2475 .prcm = {
2476 .omap4 = {
2477 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2478 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2479 .modulemode = MODULEMODE_SWCTRL,
2480 },
2481 },
2482 .slaves = omap44xx_i2c4_slaves,
2483 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2484 .dev_attr = &i2c_dev_attr,
2485 };
2486
2487 /*
2488 * 'ipu' class
2489 * imaging processor unit
2490 */
2491
2492 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2493 .name = "ipu",
2494 };
2495
2496 /* ipu */
2497 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2498 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2499 { .irq = -1 }
2500 };
2501
2502 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2503 { .name = "cpu0", .rst_shift = 0 },
2504 };
2505
2506 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2507 { .name = "cpu1", .rst_shift = 1 },
2508 };
2509
2510 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2511 { .name = "mmu_cache", .rst_shift = 2 },
2512 };
2513
2514 /* ipu master ports */
2515 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2516 &omap44xx_ipu__l3_main_2,
2517 };
2518
2519 /* l3_main_2 -> ipu */
2520 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2521 .master = &omap44xx_l3_main_2_hwmod,
2522 .slave = &omap44xx_ipu_hwmod,
2523 .clk = "l3_div_ck",
2524 .user = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 /* ipu slave ports */
2528 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2529 &omap44xx_l3_main_2__ipu,
2530 };
2531
2532 /* Pseudo hwmod for reset control purpose only */
2533 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2534 .name = "ipu_c0",
2535 .class = &omap44xx_ipu_hwmod_class,
2536 .clkdm_name = "ducati_clkdm",
2537 .flags = HWMOD_INIT_NO_RESET,
2538 .rst_lines = omap44xx_ipu_c0_resets,
2539 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2540 .prcm = {
2541 .omap4 = {
2542 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2543 },
2544 },
2545 };
2546
2547 /* Pseudo hwmod for reset control purpose only */
2548 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2549 .name = "ipu_c1",
2550 .class = &omap44xx_ipu_hwmod_class,
2551 .clkdm_name = "ducati_clkdm",
2552 .flags = HWMOD_INIT_NO_RESET,
2553 .rst_lines = omap44xx_ipu_c1_resets,
2554 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2555 .prcm = {
2556 .omap4 = {
2557 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2558 },
2559 },
2560 };
2561
2562 static struct omap_hwmod omap44xx_ipu_hwmod = {
2563 .name = "ipu",
2564 .class = &omap44xx_ipu_hwmod_class,
2565 .clkdm_name = "ducati_clkdm",
2566 .mpu_irqs = omap44xx_ipu_irqs,
2567 .rst_lines = omap44xx_ipu_resets,
2568 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2569 .main_clk = "ipu_fck",
2570 .prcm = {
2571 .omap4 = {
2572 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2573 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2574 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2575 .modulemode = MODULEMODE_HWCTRL,
2576 },
2577 },
2578 .slaves = omap44xx_ipu_slaves,
2579 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2580 .masters = omap44xx_ipu_masters,
2581 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2582 };
2583
2584 /*
2585 * 'iss' class
2586 * external images sensor pixel data processor
2587 */
2588
2589 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2590 .rev_offs = 0x0000,
2591 .sysc_offs = 0x0010,
2592 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2593 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2594 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2595 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2596 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2597 .sysc_fields = &omap_hwmod_sysc_type2,
2598 };
2599
2600 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2601 .name = "iss",
2602 .sysc = &omap44xx_iss_sysc,
2603 };
2604
2605 /* iss */
2606 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2607 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2608 { .irq = -1 }
2609 };
2610
2611 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2612 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2613 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2614 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2615 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2616 { .dma_req = -1 }
2617 };
2618
2619 /* iss master ports */
2620 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2621 &omap44xx_iss__l3_main_2,
2622 };
2623
2624 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2625 {
2626 .pa_start = 0x52000000,
2627 .pa_end = 0x520000ff,
2628 .flags = ADDR_TYPE_RT
2629 },
2630 { }
2631 };
2632
2633 /* l3_main_2 -> iss */
2634 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2635 .master = &omap44xx_l3_main_2_hwmod,
2636 .slave = &omap44xx_iss_hwmod,
2637 .clk = "l3_div_ck",
2638 .addr = omap44xx_iss_addrs,
2639 .user = OCP_USER_MPU | OCP_USER_SDMA,
2640 };
2641
2642 /* iss slave ports */
2643 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2644 &omap44xx_l3_main_2__iss,
2645 };
2646
2647 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2648 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2649 };
2650
2651 static struct omap_hwmod omap44xx_iss_hwmod = {
2652 .name = "iss",
2653 .class = &omap44xx_iss_hwmod_class,
2654 .clkdm_name = "iss_clkdm",
2655 .mpu_irqs = omap44xx_iss_irqs,
2656 .sdma_reqs = omap44xx_iss_sdma_reqs,
2657 .main_clk = "iss_fck",
2658 .prcm = {
2659 .omap4 = {
2660 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2661 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2662 .modulemode = MODULEMODE_SWCTRL,
2663 },
2664 },
2665 .opt_clks = iss_opt_clks,
2666 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2667 .slaves = omap44xx_iss_slaves,
2668 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2669 .masters = omap44xx_iss_masters,
2670 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2671 };
2672
2673 /*
2674 * 'iva' class
2675 * multi-standard video encoder/decoder hardware accelerator
2676 */
2677
2678 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2679 .name = "iva",
2680 };
2681
2682 /* iva */
2683 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2684 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2685 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2686 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2687 { .irq = -1 }
2688 };
2689
2690 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2691 { .name = "logic", .rst_shift = 2 },
2692 };
2693
2694 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2695 { .name = "seq0", .rst_shift = 0 },
2696 };
2697
2698 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2699 { .name = "seq1", .rst_shift = 1 },
2700 };
2701
2702 /* iva master ports */
2703 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2704 &omap44xx_iva__l3_main_2,
2705 &omap44xx_iva__l3_instr,
2706 };
2707
2708 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2709 {
2710 .pa_start = 0x5a000000,
2711 .pa_end = 0x5a07ffff,
2712 .flags = ADDR_TYPE_RT
2713 },
2714 { }
2715 };
2716
2717 /* l3_main_2 -> iva */
2718 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2719 .master = &omap44xx_l3_main_2_hwmod,
2720 .slave = &omap44xx_iva_hwmod,
2721 .clk = "l3_div_ck",
2722 .addr = omap44xx_iva_addrs,
2723 .user = OCP_USER_MPU,
2724 };
2725
2726 /* iva slave ports */
2727 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2728 &omap44xx_dsp__iva,
2729 &omap44xx_l3_main_2__iva,
2730 };
2731
2732 /* Pseudo hwmod for reset control purpose only */
2733 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2734 .name = "iva_seq0",
2735 .class = &omap44xx_iva_hwmod_class,
2736 .clkdm_name = "ivahd_clkdm",
2737 .flags = HWMOD_INIT_NO_RESET,
2738 .rst_lines = omap44xx_iva_seq0_resets,
2739 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2740 .prcm = {
2741 .omap4 = {
2742 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2743 },
2744 },
2745 };
2746
2747 /* Pseudo hwmod for reset control purpose only */
2748 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2749 .name = "iva_seq1",
2750 .class = &omap44xx_iva_hwmod_class,
2751 .clkdm_name = "ivahd_clkdm",
2752 .flags = HWMOD_INIT_NO_RESET,
2753 .rst_lines = omap44xx_iva_seq1_resets,
2754 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2755 .prcm = {
2756 .omap4 = {
2757 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2758 },
2759 },
2760 };
2761
2762 static struct omap_hwmod omap44xx_iva_hwmod = {
2763 .name = "iva",
2764 .class = &omap44xx_iva_hwmod_class,
2765 .clkdm_name = "ivahd_clkdm",
2766 .mpu_irqs = omap44xx_iva_irqs,
2767 .rst_lines = omap44xx_iva_resets,
2768 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2769 .main_clk = "iva_fck",
2770 .prcm = {
2771 .omap4 = {
2772 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2773 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2774 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2775 .modulemode = MODULEMODE_HWCTRL,
2776 },
2777 },
2778 .slaves = omap44xx_iva_slaves,
2779 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2780 .masters = omap44xx_iva_masters,
2781 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2782 };
2783
2784 /*
2785 * 'kbd' class
2786 * keyboard controller
2787 */
2788
2789 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2790 .rev_offs = 0x0000,
2791 .sysc_offs = 0x0010,
2792 .syss_offs = 0x0014,
2793 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2794 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2795 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2796 SYSS_HAS_RESET_STATUS),
2797 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2798 .sysc_fields = &omap_hwmod_sysc_type1,
2799 };
2800
2801 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2802 .name = "kbd",
2803 .sysc = &omap44xx_kbd_sysc,
2804 };
2805
2806 /* kbd */
2807 static struct omap_hwmod omap44xx_kbd_hwmod;
2808 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2809 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2810 { .irq = -1 }
2811 };
2812
2813 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2814 {
2815 .pa_start = 0x4a31c000,
2816 .pa_end = 0x4a31c07f,
2817 .flags = ADDR_TYPE_RT
2818 },
2819 { }
2820 };
2821
2822 /* l4_wkup -> kbd */
2823 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2824 .master = &omap44xx_l4_wkup_hwmod,
2825 .slave = &omap44xx_kbd_hwmod,
2826 .clk = "l4_wkup_clk_mux_ck",
2827 .addr = omap44xx_kbd_addrs,
2828 .user = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* kbd slave ports */
2832 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2833 &omap44xx_l4_wkup__kbd,
2834 };
2835
2836 static struct omap_hwmod omap44xx_kbd_hwmod = {
2837 .name = "kbd",
2838 .class = &omap44xx_kbd_hwmod_class,
2839 .clkdm_name = "l4_wkup_clkdm",
2840 .mpu_irqs = omap44xx_kbd_irqs,
2841 .main_clk = "kbd_fck",
2842 .prcm = {
2843 .omap4 = {
2844 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2845 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2846 .modulemode = MODULEMODE_SWCTRL,
2847 },
2848 },
2849 .slaves = omap44xx_kbd_slaves,
2850 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2851 };
2852
2853 /*
2854 * 'mailbox' class
2855 * mailbox module allowing communication between the on-chip processors using a
2856 * queued mailbox-interrupt mechanism.
2857 */
2858
2859 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2860 .rev_offs = 0x0000,
2861 .sysc_offs = 0x0010,
2862 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2863 SYSC_HAS_SOFTRESET),
2864 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2865 .sysc_fields = &omap_hwmod_sysc_type2,
2866 };
2867
2868 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2869 .name = "mailbox",
2870 .sysc = &omap44xx_mailbox_sysc,
2871 };
2872
2873 /* mailbox */
2874 static struct omap_hwmod omap44xx_mailbox_hwmod;
2875 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2876 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2877 { .irq = -1 }
2878 };
2879
2880 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2881 {
2882 .pa_start = 0x4a0f4000,
2883 .pa_end = 0x4a0f41ff,
2884 .flags = ADDR_TYPE_RT
2885 },
2886 { }
2887 };
2888
2889 /* l4_cfg -> mailbox */
2890 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2891 .master = &omap44xx_l4_cfg_hwmod,
2892 .slave = &omap44xx_mailbox_hwmod,
2893 .clk = "l4_div_ck",
2894 .addr = omap44xx_mailbox_addrs,
2895 .user = OCP_USER_MPU | OCP_USER_SDMA,
2896 };
2897
2898 /* mailbox slave ports */
2899 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2900 &omap44xx_l4_cfg__mailbox,
2901 };
2902
2903 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2904 .name = "mailbox",
2905 .class = &omap44xx_mailbox_hwmod_class,
2906 .clkdm_name = "l4_cfg_clkdm",
2907 .mpu_irqs = omap44xx_mailbox_irqs,
2908 .prcm = {
2909 .omap4 = {
2910 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2911 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2912 },
2913 },
2914 .slaves = omap44xx_mailbox_slaves,
2915 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2916 };
2917
2918 /*
2919 * 'mcbsp' class
2920 * multi channel buffered serial port controller
2921 */
2922
2923 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2924 .sysc_offs = 0x008c,
2925 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2926 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2927 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2928 .sysc_fields = &omap_hwmod_sysc_type1,
2929 };
2930
2931 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2932 .name = "mcbsp",
2933 .sysc = &omap44xx_mcbsp_sysc,
2934 .rev = MCBSP_CONFIG_TYPE4,
2935 };
2936
2937 /* mcbsp1 */
2938 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2939 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2940 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2941 { .irq = -1 }
2942 };
2943
2944 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2945 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2946 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2947 { .dma_req = -1 }
2948 };
2949
2950 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2951 {
2952 .name = "mpu",
2953 .pa_start = 0x40122000,
2954 .pa_end = 0x401220ff,
2955 .flags = ADDR_TYPE_RT
2956 },
2957 { }
2958 };
2959
2960 /* l4_abe -> mcbsp1 */
2961 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2962 .master = &omap44xx_l4_abe_hwmod,
2963 .slave = &omap44xx_mcbsp1_hwmod,
2964 .clk = "ocp_abe_iclk",
2965 .addr = omap44xx_mcbsp1_addrs,
2966 .user = OCP_USER_MPU,
2967 };
2968
2969 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2970 {
2971 .name = "dma",
2972 .pa_start = 0x49022000,
2973 .pa_end = 0x490220ff,
2974 .flags = ADDR_TYPE_RT
2975 },
2976 { }
2977 };
2978
2979 /* l4_abe -> mcbsp1 (dma) */
2980 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2981 .master = &omap44xx_l4_abe_hwmod,
2982 .slave = &omap44xx_mcbsp1_hwmod,
2983 .clk = "ocp_abe_iclk",
2984 .addr = omap44xx_mcbsp1_dma_addrs,
2985 .user = OCP_USER_SDMA,
2986 };
2987
2988 /* mcbsp1 slave ports */
2989 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2990 &omap44xx_l4_abe__mcbsp1,
2991 &omap44xx_l4_abe__mcbsp1_dma,
2992 };
2993
2994 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2995 .name = "mcbsp1",
2996 .class = &omap44xx_mcbsp_hwmod_class,
2997 .clkdm_name = "abe_clkdm",
2998 .mpu_irqs = omap44xx_mcbsp1_irqs,
2999 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
3000 .main_clk = "mcbsp1_fck",
3001 .prcm = {
3002 .omap4 = {
3003 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3004 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3005 .modulemode = MODULEMODE_SWCTRL,
3006 },
3007 },
3008 .slaves = omap44xx_mcbsp1_slaves,
3009 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3010 };
3011
3012 /* mcbsp2 */
3013 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3014 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3015 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3016 { .irq = -1 }
3017 };
3018
3019 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3020 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3021 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3022 { .dma_req = -1 }
3023 };
3024
3025 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3026 {
3027 .name = "mpu",
3028 .pa_start = 0x40124000,
3029 .pa_end = 0x401240ff,
3030 .flags = ADDR_TYPE_RT
3031 },
3032 { }
3033 };
3034
3035 /* l4_abe -> mcbsp2 */
3036 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3037 .master = &omap44xx_l4_abe_hwmod,
3038 .slave = &omap44xx_mcbsp2_hwmod,
3039 .clk = "ocp_abe_iclk",
3040 .addr = omap44xx_mcbsp2_addrs,
3041 .user = OCP_USER_MPU,
3042 };
3043
3044 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3045 {
3046 .name = "dma",
3047 .pa_start = 0x49024000,
3048 .pa_end = 0x490240ff,
3049 .flags = ADDR_TYPE_RT
3050 },
3051 { }
3052 };
3053
3054 /* l4_abe -> mcbsp2 (dma) */
3055 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3056 .master = &omap44xx_l4_abe_hwmod,
3057 .slave = &omap44xx_mcbsp2_hwmod,
3058 .clk = "ocp_abe_iclk",
3059 .addr = omap44xx_mcbsp2_dma_addrs,
3060 .user = OCP_USER_SDMA,
3061 };
3062
3063 /* mcbsp2 slave ports */
3064 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3065 &omap44xx_l4_abe__mcbsp2,
3066 &omap44xx_l4_abe__mcbsp2_dma,
3067 };
3068
3069 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3070 .name = "mcbsp2",
3071 .class = &omap44xx_mcbsp_hwmod_class,
3072 .clkdm_name = "abe_clkdm",
3073 .mpu_irqs = omap44xx_mcbsp2_irqs,
3074 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
3075 .main_clk = "mcbsp2_fck",
3076 .prcm = {
3077 .omap4 = {
3078 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3079 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3080 .modulemode = MODULEMODE_SWCTRL,
3081 },
3082 },
3083 .slaves = omap44xx_mcbsp2_slaves,
3084 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3085 };
3086
3087 /* mcbsp3 */
3088 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3089 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3090 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3091 { .irq = -1 }
3092 };
3093
3094 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3095 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3096 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3097 { .dma_req = -1 }
3098 };
3099
3100 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3101 {
3102 .name = "mpu",
3103 .pa_start = 0x40126000,
3104 .pa_end = 0x401260ff,
3105 .flags = ADDR_TYPE_RT
3106 },
3107 { }
3108 };
3109
3110 /* l4_abe -> mcbsp3 */
3111 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3112 .master = &omap44xx_l4_abe_hwmod,
3113 .slave = &omap44xx_mcbsp3_hwmod,
3114 .clk = "ocp_abe_iclk",
3115 .addr = omap44xx_mcbsp3_addrs,
3116 .user = OCP_USER_MPU,
3117 };
3118
3119 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3120 {
3121 .name = "dma",
3122 .pa_start = 0x49026000,
3123 .pa_end = 0x490260ff,
3124 .flags = ADDR_TYPE_RT
3125 },
3126 { }
3127 };
3128
3129 /* l4_abe -> mcbsp3 (dma) */
3130 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3131 .master = &omap44xx_l4_abe_hwmod,
3132 .slave = &omap44xx_mcbsp3_hwmod,
3133 .clk = "ocp_abe_iclk",
3134 .addr = omap44xx_mcbsp3_dma_addrs,
3135 .user = OCP_USER_SDMA,
3136 };
3137
3138 /* mcbsp3 slave ports */
3139 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3140 &omap44xx_l4_abe__mcbsp3,
3141 &omap44xx_l4_abe__mcbsp3_dma,
3142 };
3143
3144 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3145 .name = "mcbsp3",
3146 .class = &omap44xx_mcbsp_hwmod_class,
3147 .clkdm_name = "abe_clkdm",
3148 .mpu_irqs = omap44xx_mcbsp3_irqs,
3149 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
3150 .main_clk = "mcbsp3_fck",
3151 .prcm = {
3152 .omap4 = {
3153 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3154 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3155 .modulemode = MODULEMODE_SWCTRL,
3156 },
3157 },
3158 .slaves = omap44xx_mcbsp3_slaves,
3159 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3160 };
3161
3162 /* mcbsp4 */
3163 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3164 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3165 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3166 { .irq = -1 }
3167 };
3168
3169 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3170 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3171 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3172 { .dma_req = -1 }
3173 };
3174
3175 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3176 {
3177 .pa_start = 0x48096000,
3178 .pa_end = 0x480960ff,
3179 .flags = ADDR_TYPE_RT
3180 },
3181 { }
3182 };
3183
3184 /* l4_per -> mcbsp4 */
3185 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3186 .master = &omap44xx_l4_per_hwmod,
3187 .slave = &omap44xx_mcbsp4_hwmod,
3188 .clk = "l4_div_ck",
3189 .addr = omap44xx_mcbsp4_addrs,
3190 .user = OCP_USER_MPU | OCP_USER_SDMA,
3191 };
3192
3193 /* mcbsp4 slave ports */
3194 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3195 &omap44xx_l4_per__mcbsp4,
3196 };
3197
3198 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3199 .name = "mcbsp4",
3200 .class = &omap44xx_mcbsp_hwmod_class,
3201 .clkdm_name = "l4_per_clkdm",
3202 .mpu_irqs = omap44xx_mcbsp4_irqs,
3203 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3204 .main_clk = "mcbsp4_fck",
3205 .prcm = {
3206 .omap4 = {
3207 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3208 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3209 .modulemode = MODULEMODE_SWCTRL,
3210 },
3211 },
3212 .slaves = omap44xx_mcbsp4_slaves,
3213 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3214 };
3215
3216 /*
3217 * 'mcpdm' class
3218 * multi channel pdm controller (proprietary interface with phoenix power
3219 * ic)
3220 */
3221
3222 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3223 .rev_offs = 0x0000,
3224 .sysc_offs = 0x0010,
3225 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3226 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3227 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3228 SIDLE_SMART_WKUP),
3229 .sysc_fields = &omap_hwmod_sysc_type2,
3230 };
3231
3232 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3233 .name = "mcpdm",
3234 .sysc = &omap44xx_mcpdm_sysc,
3235 };
3236
3237 /* mcpdm */
3238 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3239 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3240 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3241 { .irq = -1 }
3242 };
3243
3244 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3245 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3246 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3247 { .dma_req = -1 }
3248 };
3249
3250 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3251 {
3252 .pa_start = 0x40132000,
3253 .pa_end = 0x4013207f,
3254 .flags = ADDR_TYPE_RT
3255 },
3256 { }
3257 };
3258
3259 /* l4_abe -> mcpdm */
3260 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3261 .master = &omap44xx_l4_abe_hwmod,
3262 .slave = &omap44xx_mcpdm_hwmod,
3263 .clk = "ocp_abe_iclk",
3264 .addr = omap44xx_mcpdm_addrs,
3265 .user = OCP_USER_MPU,
3266 };
3267
3268 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3269 {
3270 .pa_start = 0x49032000,
3271 .pa_end = 0x4903207f,
3272 .flags = ADDR_TYPE_RT
3273 },
3274 { }
3275 };
3276
3277 /* l4_abe -> mcpdm (dma) */
3278 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3279 .master = &omap44xx_l4_abe_hwmod,
3280 .slave = &omap44xx_mcpdm_hwmod,
3281 .clk = "ocp_abe_iclk",
3282 .addr = omap44xx_mcpdm_dma_addrs,
3283 .user = OCP_USER_SDMA,
3284 };
3285
3286 /* mcpdm slave ports */
3287 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3288 &omap44xx_l4_abe__mcpdm,
3289 &omap44xx_l4_abe__mcpdm_dma,
3290 };
3291
3292 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3293 .name = "mcpdm",
3294 .class = &omap44xx_mcpdm_hwmod_class,
3295 .clkdm_name = "abe_clkdm",
3296 .mpu_irqs = omap44xx_mcpdm_irqs,
3297 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3298 .main_clk = "mcpdm_fck",
3299 .prcm = {
3300 .omap4 = {
3301 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3302 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3303 .modulemode = MODULEMODE_SWCTRL,
3304 },
3305 },
3306 .slaves = omap44xx_mcpdm_slaves,
3307 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3308 };
3309
3310 /*
3311 * 'mcspi' class
3312 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3313 * bus
3314 */
3315
3316 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3317 .rev_offs = 0x0000,
3318 .sysc_offs = 0x0010,
3319 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3320 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3321 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3322 SIDLE_SMART_WKUP),
3323 .sysc_fields = &omap_hwmod_sysc_type2,
3324 };
3325
3326 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3327 .name = "mcspi",
3328 .sysc = &omap44xx_mcspi_sysc,
3329 .rev = OMAP4_MCSPI_REV,
3330 };
3331
3332 /* mcspi1 */
3333 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3334 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3335 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3336 { .irq = -1 }
3337 };
3338
3339 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3340 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3341 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3342 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3343 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3344 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3345 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3346 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3347 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3348 { .dma_req = -1 }
3349 };
3350
3351 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3352 {
3353 .pa_start = 0x48098000,
3354 .pa_end = 0x480981ff,
3355 .flags = ADDR_TYPE_RT
3356 },
3357 { }
3358 };
3359
3360 /* l4_per -> mcspi1 */
3361 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3362 .master = &omap44xx_l4_per_hwmod,
3363 .slave = &omap44xx_mcspi1_hwmod,
3364 .clk = "l4_div_ck",
3365 .addr = omap44xx_mcspi1_addrs,
3366 .user = OCP_USER_MPU | OCP_USER_SDMA,
3367 };
3368
3369 /* mcspi1 slave ports */
3370 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3371 &omap44xx_l4_per__mcspi1,
3372 };
3373
3374 /* mcspi1 dev_attr */
3375 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3376 .num_chipselect = 4,
3377 };
3378
3379 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3380 .name = "mcspi1",
3381 .class = &omap44xx_mcspi_hwmod_class,
3382 .clkdm_name = "l4_per_clkdm",
3383 .mpu_irqs = omap44xx_mcspi1_irqs,
3384 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3385 .main_clk = "mcspi1_fck",
3386 .prcm = {
3387 .omap4 = {
3388 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3389 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3390 .modulemode = MODULEMODE_SWCTRL,
3391 },
3392 },
3393 .dev_attr = &mcspi1_dev_attr,
3394 .slaves = omap44xx_mcspi1_slaves,
3395 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3396 };
3397
3398 /* mcspi2 */
3399 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3400 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3401 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3402 { .irq = -1 }
3403 };
3404
3405 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3406 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3407 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3408 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3409 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3410 { .dma_req = -1 }
3411 };
3412
3413 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3414 {
3415 .pa_start = 0x4809a000,
3416 .pa_end = 0x4809a1ff,
3417 .flags = ADDR_TYPE_RT
3418 },
3419 { }
3420 };
3421
3422 /* l4_per -> mcspi2 */
3423 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3424 .master = &omap44xx_l4_per_hwmod,
3425 .slave = &omap44xx_mcspi2_hwmod,
3426 .clk = "l4_div_ck",
3427 .addr = omap44xx_mcspi2_addrs,
3428 .user = OCP_USER_MPU | OCP_USER_SDMA,
3429 };
3430
3431 /* mcspi2 slave ports */
3432 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3433 &omap44xx_l4_per__mcspi2,
3434 };
3435
3436 /* mcspi2 dev_attr */
3437 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3438 .num_chipselect = 2,
3439 };
3440
3441 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3442 .name = "mcspi2",
3443 .class = &omap44xx_mcspi_hwmod_class,
3444 .clkdm_name = "l4_per_clkdm",
3445 .mpu_irqs = omap44xx_mcspi2_irqs,
3446 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3447 .main_clk = "mcspi2_fck",
3448 .prcm = {
3449 .omap4 = {
3450 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3451 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3452 .modulemode = MODULEMODE_SWCTRL,
3453 },
3454 },
3455 .dev_attr = &mcspi2_dev_attr,
3456 .slaves = omap44xx_mcspi2_slaves,
3457 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3458 };
3459
3460 /* mcspi3 */
3461 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3462 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3463 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3464 { .irq = -1 }
3465 };
3466
3467 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3468 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3469 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3470 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3471 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3472 { .dma_req = -1 }
3473 };
3474
3475 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3476 {
3477 .pa_start = 0x480b8000,
3478 .pa_end = 0x480b81ff,
3479 .flags = ADDR_TYPE_RT
3480 },
3481 { }
3482 };
3483
3484 /* l4_per -> mcspi3 */
3485 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3486 .master = &omap44xx_l4_per_hwmod,
3487 .slave = &omap44xx_mcspi3_hwmod,
3488 .clk = "l4_div_ck",
3489 .addr = omap44xx_mcspi3_addrs,
3490 .user = OCP_USER_MPU | OCP_USER_SDMA,
3491 };
3492
3493 /* mcspi3 slave ports */
3494 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3495 &omap44xx_l4_per__mcspi3,
3496 };
3497
3498 /* mcspi3 dev_attr */
3499 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3500 .num_chipselect = 2,
3501 };
3502
3503 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3504 .name = "mcspi3",
3505 .class = &omap44xx_mcspi_hwmod_class,
3506 .clkdm_name = "l4_per_clkdm",
3507 .mpu_irqs = omap44xx_mcspi3_irqs,
3508 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3509 .main_clk = "mcspi3_fck",
3510 .prcm = {
3511 .omap4 = {
3512 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3513 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3514 .modulemode = MODULEMODE_SWCTRL,
3515 },
3516 },
3517 .dev_attr = &mcspi3_dev_attr,
3518 .slaves = omap44xx_mcspi3_slaves,
3519 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3520 };
3521
3522 /* mcspi4 */
3523 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3524 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3525 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3526 { .irq = -1 }
3527 };
3528
3529 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3530 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3531 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3532 { .dma_req = -1 }
3533 };
3534
3535 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3536 {
3537 .pa_start = 0x480ba000,
3538 .pa_end = 0x480ba1ff,
3539 .flags = ADDR_TYPE_RT
3540 },
3541 { }
3542 };
3543
3544 /* l4_per -> mcspi4 */
3545 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3546 .master = &omap44xx_l4_per_hwmod,
3547 .slave = &omap44xx_mcspi4_hwmod,
3548 .clk = "l4_div_ck",
3549 .addr = omap44xx_mcspi4_addrs,
3550 .user = OCP_USER_MPU | OCP_USER_SDMA,
3551 };
3552
3553 /* mcspi4 slave ports */
3554 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3555 &omap44xx_l4_per__mcspi4,
3556 };
3557
3558 /* mcspi4 dev_attr */
3559 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3560 .num_chipselect = 1,
3561 };
3562
3563 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3564 .name = "mcspi4",
3565 .class = &omap44xx_mcspi_hwmod_class,
3566 .clkdm_name = "l4_per_clkdm",
3567 .mpu_irqs = omap44xx_mcspi4_irqs,
3568 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3569 .main_clk = "mcspi4_fck",
3570 .prcm = {
3571 .omap4 = {
3572 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3573 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3574 .modulemode = MODULEMODE_SWCTRL,
3575 },
3576 },
3577 .dev_attr = &mcspi4_dev_attr,
3578 .slaves = omap44xx_mcspi4_slaves,
3579 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3580 };
3581
3582 /*
3583 * 'mmc' class
3584 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3585 */
3586
3587 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3588 .rev_offs = 0x0000,
3589 .sysc_offs = 0x0010,
3590 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3591 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3592 SYSC_HAS_SOFTRESET),
3593 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3594 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3595 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3596 .sysc_fields = &omap_hwmod_sysc_type2,
3597 };
3598
3599 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3600 .name = "mmc",
3601 .sysc = &omap44xx_mmc_sysc,
3602 };
3603
3604 /* mmc1 */
3605 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3606 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3607 { .irq = -1 }
3608 };
3609
3610 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3611 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3612 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3613 { .dma_req = -1 }
3614 };
3615
3616 /* mmc1 master ports */
3617 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3618 &omap44xx_mmc1__l3_main_1,
3619 };
3620
3621 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3622 {
3623 .pa_start = 0x4809c000,
3624 .pa_end = 0x4809c3ff,
3625 .flags = ADDR_TYPE_RT
3626 },
3627 { }
3628 };
3629
3630 /* l4_per -> mmc1 */
3631 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3632 .master = &omap44xx_l4_per_hwmod,
3633 .slave = &omap44xx_mmc1_hwmod,
3634 .clk = "l4_div_ck",
3635 .addr = omap44xx_mmc1_addrs,
3636 .user = OCP_USER_MPU | OCP_USER_SDMA,
3637 };
3638
3639 /* mmc1 slave ports */
3640 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3641 &omap44xx_l4_per__mmc1,
3642 };
3643
3644 /* mmc1 dev_attr */
3645 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3646 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3647 };
3648
3649 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3650 .name = "mmc1",
3651 .class = &omap44xx_mmc_hwmod_class,
3652 .clkdm_name = "l3_init_clkdm",
3653 .mpu_irqs = omap44xx_mmc1_irqs,
3654 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3655 .main_clk = "mmc1_fck",
3656 .prcm = {
3657 .omap4 = {
3658 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3659 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3660 .modulemode = MODULEMODE_SWCTRL,
3661 },
3662 },
3663 .dev_attr = &mmc1_dev_attr,
3664 .slaves = omap44xx_mmc1_slaves,
3665 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3666 .masters = omap44xx_mmc1_masters,
3667 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3668 };
3669
3670 /* mmc2 */
3671 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3672 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3673 { .irq = -1 }
3674 };
3675
3676 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3677 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3678 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3679 { .dma_req = -1 }
3680 };
3681
3682 /* mmc2 master ports */
3683 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3684 &omap44xx_mmc2__l3_main_1,
3685 };
3686
3687 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3688 {
3689 .pa_start = 0x480b4000,
3690 .pa_end = 0x480b43ff,
3691 .flags = ADDR_TYPE_RT
3692 },
3693 { }
3694 };
3695
3696 /* l4_per -> mmc2 */
3697 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3698 .master = &omap44xx_l4_per_hwmod,
3699 .slave = &omap44xx_mmc2_hwmod,
3700 .clk = "l4_div_ck",
3701 .addr = omap44xx_mmc2_addrs,
3702 .user = OCP_USER_MPU | OCP_USER_SDMA,
3703 };
3704
3705 /* mmc2 slave ports */
3706 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3707 &omap44xx_l4_per__mmc2,
3708 };
3709
3710 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3711 .name = "mmc2",
3712 .class = &omap44xx_mmc_hwmod_class,
3713 .clkdm_name = "l3_init_clkdm",
3714 .mpu_irqs = omap44xx_mmc2_irqs,
3715 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3716 .main_clk = "mmc2_fck",
3717 .prcm = {
3718 .omap4 = {
3719 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3720 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3721 .modulemode = MODULEMODE_SWCTRL,
3722 },
3723 },
3724 .slaves = omap44xx_mmc2_slaves,
3725 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3726 .masters = omap44xx_mmc2_masters,
3727 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3728 };
3729
3730 /* mmc3 */
3731 static struct omap_hwmod omap44xx_mmc3_hwmod;
3732 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3733 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3734 { .irq = -1 }
3735 };
3736
3737 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3738 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3739 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3740 { .dma_req = -1 }
3741 };
3742
3743 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3744 {
3745 .pa_start = 0x480ad000,
3746 .pa_end = 0x480ad3ff,
3747 .flags = ADDR_TYPE_RT
3748 },
3749 { }
3750 };
3751
3752 /* l4_per -> mmc3 */
3753 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3754 .master = &omap44xx_l4_per_hwmod,
3755 .slave = &omap44xx_mmc3_hwmod,
3756 .clk = "l4_div_ck",
3757 .addr = omap44xx_mmc3_addrs,
3758 .user = OCP_USER_MPU | OCP_USER_SDMA,
3759 };
3760
3761 /* mmc3 slave ports */
3762 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3763 &omap44xx_l4_per__mmc3,
3764 };
3765
3766 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3767 .name = "mmc3",
3768 .class = &omap44xx_mmc_hwmod_class,
3769 .clkdm_name = "l4_per_clkdm",
3770 .mpu_irqs = omap44xx_mmc3_irqs,
3771 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3772 .main_clk = "mmc3_fck",
3773 .prcm = {
3774 .omap4 = {
3775 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3776 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3777 .modulemode = MODULEMODE_SWCTRL,
3778 },
3779 },
3780 .slaves = omap44xx_mmc3_slaves,
3781 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3782 };
3783
3784 /* mmc4 */
3785 static struct omap_hwmod omap44xx_mmc4_hwmod;
3786 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3787 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3788 { .irq = -1 }
3789 };
3790
3791 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3792 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3793 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3794 { .dma_req = -1 }
3795 };
3796
3797 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3798 {
3799 .pa_start = 0x480d1000,
3800 .pa_end = 0x480d13ff,
3801 .flags = ADDR_TYPE_RT
3802 },
3803 { }
3804 };
3805
3806 /* l4_per -> mmc4 */
3807 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3808 .master = &omap44xx_l4_per_hwmod,
3809 .slave = &omap44xx_mmc4_hwmod,
3810 .clk = "l4_div_ck",
3811 .addr = omap44xx_mmc4_addrs,
3812 .user = OCP_USER_MPU | OCP_USER_SDMA,
3813 };
3814
3815 /* mmc4 slave ports */
3816 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3817 &omap44xx_l4_per__mmc4,
3818 };
3819
3820 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3821 .name = "mmc4",
3822 .class = &omap44xx_mmc_hwmod_class,
3823 .clkdm_name = "l4_per_clkdm",
3824 .mpu_irqs = omap44xx_mmc4_irqs,
3825
3826 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3827 .main_clk = "mmc4_fck",
3828 .prcm = {
3829 .omap4 = {
3830 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3831 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3832 .modulemode = MODULEMODE_SWCTRL,
3833 },
3834 },
3835 .slaves = omap44xx_mmc4_slaves,
3836 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3837 };
3838
3839 /* mmc5 */
3840 static struct omap_hwmod omap44xx_mmc5_hwmod;
3841 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3842 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3843 { .irq = -1 }
3844 };
3845
3846 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3847 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3848 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3849 { .dma_req = -1 }
3850 };
3851
3852 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3853 {
3854 .pa_start = 0x480d5000,
3855 .pa_end = 0x480d53ff,
3856 .flags = ADDR_TYPE_RT
3857 },
3858 { }
3859 };
3860
3861 /* l4_per -> mmc5 */
3862 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3863 .master = &omap44xx_l4_per_hwmod,
3864 .slave = &omap44xx_mmc5_hwmod,
3865 .clk = "l4_div_ck",
3866 .addr = omap44xx_mmc5_addrs,
3867 .user = OCP_USER_MPU | OCP_USER_SDMA,
3868 };
3869
3870 /* mmc5 slave ports */
3871 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3872 &omap44xx_l4_per__mmc5,
3873 };
3874
3875 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3876 .name = "mmc5",
3877 .class = &omap44xx_mmc_hwmod_class,
3878 .clkdm_name = "l4_per_clkdm",
3879 .mpu_irqs = omap44xx_mmc5_irqs,
3880 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3881 .main_clk = "mmc5_fck",
3882 .prcm = {
3883 .omap4 = {
3884 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3885 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3886 .modulemode = MODULEMODE_SWCTRL,
3887 },
3888 },
3889 .slaves = omap44xx_mmc5_slaves,
3890 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3891 };
3892
3893 /*
3894 * 'mpu' class
3895 * mpu sub-system
3896 */
3897
3898 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3899 .name = "mpu",
3900 };
3901
3902 /* mpu */
3903 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3904 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3905 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3906 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3907 { .irq = -1 }
3908 };
3909
3910 /* mpu master ports */
3911 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3912 &omap44xx_mpu__l3_main_1,
3913 &omap44xx_mpu__l4_abe,
3914 &omap44xx_mpu__dmm,
3915 };
3916
3917 static struct omap_hwmod omap44xx_mpu_hwmod = {
3918 .name = "mpu",
3919 .class = &omap44xx_mpu_hwmod_class,
3920 .clkdm_name = "mpuss_clkdm",
3921 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3922 .mpu_irqs = omap44xx_mpu_irqs,
3923 .main_clk = "dpll_mpu_m2_ck",
3924 .prcm = {
3925 .omap4 = {
3926 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3927 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3928 },
3929 },
3930 .masters = omap44xx_mpu_masters,
3931 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
3932 };
3933
3934 /*
3935 * 'smartreflex' class
3936 * smartreflex module (monitor silicon performance and outputs a measure of
3937 * performance error)
3938 */
3939
3940 /* The IP is not compliant to type1 / type2 scheme */
3941 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3942 .sidle_shift = 24,
3943 .enwkup_shift = 26,
3944 };
3945
3946 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3947 .sysc_offs = 0x0038,
3948 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3949 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3950 SIDLE_SMART_WKUP),
3951 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3952 };
3953
3954 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3955 .name = "smartreflex",
3956 .sysc = &omap44xx_smartreflex_sysc,
3957 .rev = 2,
3958 };
3959
3960 /* smartreflex_core */
3961 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3962 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3963 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3964 { .irq = -1 }
3965 };
3966
3967 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3968 {
3969 .pa_start = 0x4a0dd000,
3970 .pa_end = 0x4a0dd03f,
3971 .flags = ADDR_TYPE_RT
3972 },
3973 { }
3974 };
3975
3976 /* l4_cfg -> smartreflex_core */
3977 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3978 .master = &omap44xx_l4_cfg_hwmod,
3979 .slave = &omap44xx_smartreflex_core_hwmod,
3980 .clk = "l4_div_ck",
3981 .addr = omap44xx_smartreflex_core_addrs,
3982 .user = OCP_USER_MPU | OCP_USER_SDMA,
3983 };
3984
3985 /* smartreflex_core slave ports */
3986 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3987 &omap44xx_l4_cfg__smartreflex_core,
3988 };
3989
3990 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3991 .name = "smartreflex_core",
3992 .class = &omap44xx_smartreflex_hwmod_class,
3993 .clkdm_name = "l4_ao_clkdm",
3994 .mpu_irqs = omap44xx_smartreflex_core_irqs,
3995
3996 .main_clk = "smartreflex_core_fck",
3997 .vdd_name = "core",
3998 .prcm = {
3999 .omap4 = {
4000 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4001 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4002 .modulemode = MODULEMODE_SWCTRL,
4003 },
4004 },
4005 .slaves = omap44xx_smartreflex_core_slaves,
4006 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4007 };
4008
4009 /* smartreflex_iva */
4010 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4011 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4012 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4013 { .irq = -1 }
4014 };
4015
4016 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4017 {
4018 .pa_start = 0x4a0db000,
4019 .pa_end = 0x4a0db03f,
4020 .flags = ADDR_TYPE_RT
4021 },
4022 { }
4023 };
4024
4025 /* l4_cfg -> smartreflex_iva */
4026 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4027 .master = &omap44xx_l4_cfg_hwmod,
4028 .slave = &omap44xx_smartreflex_iva_hwmod,
4029 .clk = "l4_div_ck",
4030 .addr = omap44xx_smartreflex_iva_addrs,
4031 .user = OCP_USER_MPU | OCP_USER_SDMA,
4032 };
4033
4034 /* smartreflex_iva slave ports */
4035 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4036 &omap44xx_l4_cfg__smartreflex_iva,
4037 };
4038
4039 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4040 .name = "smartreflex_iva",
4041 .class = &omap44xx_smartreflex_hwmod_class,
4042 .clkdm_name = "l4_ao_clkdm",
4043 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
4044 .main_clk = "smartreflex_iva_fck",
4045 .vdd_name = "iva",
4046 .prcm = {
4047 .omap4 = {
4048 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4049 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4050 .modulemode = MODULEMODE_SWCTRL,
4051 },
4052 },
4053 .slaves = omap44xx_smartreflex_iva_slaves,
4054 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4055 };
4056
4057 /* smartreflex_mpu */
4058 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4059 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4060 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4061 { .irq = -1 }
4062 };
4063
4064 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4065 {
4066 .pa_start = 0x4a0d9000,
4067 .pa_end = 0x4a0d903f,
4068 .flags = ADDR_TYPE_RT
4069 },
4070 { }
4071 };
4072
4073 /* l4_cfg -> smartreflex_mpu */
4074 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4075 .master = &omap44xx_l4_cfg_hwmod,
4076 .slave = &omap44xx_smartreflex_mpu_hwmod,
4077 .clk = "l4_div_ck",
4078 .addr = omap44xx_smartreflex_mpu_addrs,
4079 .user = OCP_USER_MPU | OCP_USER_SDMA,
4080 };
4081
4082 /* smartreflex_mpu slave ports */
4083 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4084 &omap44xx_l4_cfg__smartreflex_mpu,
4085 };
4086
4087 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4088 .name = "smartreflex_mpu",
4089 .class = &omap44xx_smartreflex_hwmod_class,
4090 .clkdm_name = "l4_ao_clkdm",
4091 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
4092 .main_clk = "smartreflex_mpu_fck",
4093 .vdd_name = "mpu",
4094 .prcm = {
4095 .omap4 = {
4096 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4097 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4098 .modulemode = MODULEMODE_SWCTRL,
4099 },
4100 },
4101 .slaves = omap44xx_smartreflex_mpu_slaves,
4102 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4103 };
4104
4105 /*
4106 * 'spinlock' class
4107 * spinlock provides hardware assistance for synchronizing the processes
4108 * running on multiple processors
4109 */
4110
4111 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4112 .rev_offs = 0x0000,
4113 .sysc_offs = 0x0010,
4114 .syss_offs = 0x0014,
4115 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4116 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4117 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4118 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4119 SIDLE_SMART_WKUP),
4120 .sysc_fields = &omap_hwmod_sysc_type1,
4121 };
4122
4123 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4124 .name = "spinlock",
4125 .sysc = &omap44xx_spinlock_sysc,
4126 };
4127
4128 /* spinlock */
4129 static struct omap_hwmod omap44xx_spinlock_hwmod;
4130 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4131 {
4132 .pa_start = 0x4a0f6000,
4133 .pa_end = 0x4a0f6fff,
4134 .flags = ADDR_TYPE_RT
4135 },
4136 { }
4137 };
4138
4139 /* l4_cfg -> spinlock */
4140 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4141 .master = &omap44xx_l4_cfg_hwmod,
4142 .slave = &omap44xx_spinlock_hwmod,
4143 .clk = "l4_div_ck",
4144 .addr = omap44xx_spinlock_addrs,
4145 .user = OCP_USER_MPU | OCP_USER_SDMA,
4146 };
4147
4148 /* spinlock slave ports */
4149 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4150 &omap44xx_l4_cfg__spinlock,
4151 };
4152
4153 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4154 .name = "spinlock",
4155 .class = &omap44xx_spinlock_hwmod_class,
4156 .clkdm_name = "l4_cfg_clkdm",
4157 .prcm = {
4158 .omap4 = {
4159 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4160 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4161 },
4162 },
4163 .slaves = omap44xx_spinlock_slaves,
4164 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4165 };
4166
4167 /*
4168 * 'timer' class
4169 * general purpose timer module with accurate 1ms tick
4170 * This class contains several variants: ['timer_1ms', 'timer']
4171 */
4172
4173 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4174 .rev_offs = 0x0000,
4175 .sysc_offs = 0x0010,
4176 .syss_offs = 0x0014,
4177 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4178 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4179 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4180 SYSS_HAS_RESET_STATUS),
4181 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4182 .sysc_fields = &omap_hwmod_sysc_type1,
4183 };
4184
4185 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4186 .name = "timer",
4187 .sysc = &omap44xx_timer_1ms_sysc,
4188 };
4189
4190 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4191 .rev_offs = 0x0000,
4192 .sysc_offs = 0x0010,
4193 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4194 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4195 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4196 SIDLE_SMART_WKUP),
4197 .sysc_fields = &omap_hwmod_sysc_type2,
4198 };
4199
4200 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4201 .name = "timer",
4202 .sysc = &omap44xx_timer_sysc,
4203 };
4204
4205 /* always-on timers dev attribute */
4206 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4207 .timer_capability = OMAP_TIMER_ALWON,
4208 };
4209
4210 /* pwm timers dev attribute */
4211 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4212 .timer_capability = OMAP_TIMER_HAS_PWM,
4213 };
4214
4215 /* timer1 */
4216 static struct omap_hwmod omap44xx_timer1_hwmod;
4217 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4218 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4219 { .irq = -1 }
4220 };
4221
4222 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4223 {
4224 .pa_start = 0x4a318000,
4225 .pa_end = 0x4a31807f,
4226 .flags = ADDR_TYPE_RT
4227 },
4228 { }
4229 };
4230
4231 /* l4_wkup -> timer1 */
4232 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4233 .master = &omap44xx_l4_wkup_hwmod,
4234 .slave = &omap44xx_timer1_hwmod,
4235 .clk = "l4_wkup_clk_mux_ck",
4236 .addr = omap44xx_timer1_addrs,
4237 .user = OCP_USER_MPU | OCP_USER_SDMA,
4238 };
4239
4240 /* timer1 slave ports */
4241 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4242 &omap44xx_l4_wkup__timer1,
4243 };
4244
4245 static struct omap_hwmod omap44xx_timer1_hwmod = {
4246 .name = "timer1",
4247 .class = &omap44xx_timer_1ms_hwmod_class,
4248 .clkdm_name = "l4_wkup_clkdm",
4249 .mpu_irqs = omap44xx_timer1_irqs,
4250 .main_clk = "timer1_fck",
4251 .prcm = {
4252 .omap4 = {
4253 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4254 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4255 .modulemode = MODULEMODE_SWCTRL,
4256 },
4257 },
4258 .dev_attr = &capability_alwon_dev_attr,
4259 .slaves = omap44xx_timer1_slaves,
4260 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4261 };
4262
4263 /* timer2 */
4264 static struct omap_hwmod omap44xx_timer2_hwmod;
4265 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4266 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4267 { .irq = -1 }
4268 };
4269
4270 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4271 {
4272 .pa_start = 0x48032000,
4273 .pa_end = 0x4803207f,
4274 .flags = ADDR_TYPE_RT
4275 },
4276 { }
4277 };
4278
4279 /* l4_per -> timer2 */
4280 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4281 .master = &omap44xx_l4_per_hwmod,
4282 .slave = &omap44xx_timer2_hwmod,
4283 .clk = "l4_div_ck",
4284 .addr = omap44xx_timer2_addrs,
4285 .user = OCP_USER_MPU | OCP_USER_SDMA,
4286 };
4287
4288 /* timer2 slave ports */
4289 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4290 &omap44xx_l4_per__timer2,
4291 };
4292
4293 static struct omap_hwmod omap44xx_timer2_hwmod = {
4294 .name = "timer2",
4295 .class = &omap44xx_timer_1ms_hwmod_class,
4296 .clkdm_name = "l4_per_clkdm",
4297 .mpu_irqs = omap44xx_timer2_irqs,
4298 .main_clk = "timer2_fck",
4299 .prcm = {
4300 .omap4 = {
4301 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4302 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4303 .modulemode = MODULEMODE_SWCTRL,
4304 },
4305 },
4306 .dev_attr = &capability_alwon_dev_attr,
4307 .slaves = omap44xx_timer2_slaves,
4308 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4309 };
4310
4311 /* timer3 */
4312 static struct omap_hwmod omap44xx_timer3_hwmod;
4313 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4314 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4315 { .irq = -1 }
4316 };
4317
4318 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4319 {
4320 .pa_start = 0x48034000,
4321 .pa_end = 0x4803407f,
4322 .flags = ADDR_TYPE_RT
4323 },
4324 { }
4325 };
4326
4327 /* l4_per -> timer3 */
4328 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4329 .master = &omap44xx_l4_per_hwmod,
4330 .slave = &omap44xx_timer3_hwmod,
4331 .clk = "l4_div_ck",
4332 .addr = omap44xx_timer3_addrs,
4333 .user = OCP_USER_MPU | OCP_USER_SDMA,
4334 };
4335
4336 /* timer3 slave ports */
4337 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4338 &omap44xx_l4_per__timer3,
4339 };
4340
4341 static struct omap_hwmod omap44xx_timer3_hwmod = {
4342 .name = "timer3",
4343 .class = &omap44xx_timer_hwmod_class,
4344 .clkdm_name = "l4_per_clkdm",
4345 .mpu_irqs = omap44xx_timer3_irqs,
4346 .main_clk = "timer3_fck",
4347 .prcm = {
4348 .omap4 = {
4349 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4350 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4351 .modulemode = MODULEMODE_SWCTRL,
4352 },
4353 },
4354 .dev_attr = &capability_alwon_dev_attr,
4355 .slaves = omap44xx_timer3_slaves,
4356 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4357 };
4358
4359 /* timer4 */
4360 static struct omap_hwmod omap44xx_timer4_hwmod;
4361 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4362 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4363 { .irq = -1 }
4364 };
4365
4366 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4367 {
4368 .pa_start = 0x48036000,
4369 .pa_end = 0x4803607f,
4370 .flags = ADDR_TYPE_RT
4371 },
4372 { }
4373 };
4374
4375 /* l4_per -> timer4 */
4376 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4377 .master = &omap44xx_l4_per_hwmod,
4378 .slave = &omap44xx_timer4_hwmod,
4379 .clk = "l4_div_ck",
4380 .addr = omap44xx_timer4_addrs,
4381 .user = OCP_USER_MPU | OCP_USER_SDMA,
4382 };
4383
4384 /* timer4 slave ports */
4385 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4386 &omap44xx_l4_per__timer4,
4387 };
4388
4389 static struct omap_hwmod omap44xx_timer4_hwmod = {
4390 .name = "timer4",
4391 .class = &omap44xx_timer_hwmod_class,
4392 .clkdm_name = "l4_per_clkdm",
4393 .mpu_irqs = omap44xx_timer4_irqs,
4394 .main_clk = "timer4_fck",
4395 .prcm = {
4396 .omap4 = {
4397 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4398 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4399 .modulemode = MODULEMODE_SWCTRL,
4400 },
4401 },
4402 .dev_attr = &capability_alwon_dev_attr,
4403 .slaves = omap44xx_timer4_slaves,
4404 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4405 };
4406
4407 /* timer5 */
4408 static struct omap_hwmod omap44xx_timer5_hwmod;
4409 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4410 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4411 { .irq = -1 }
4412 };
4413
4414 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4415 {
4416 .pa_start = 0x40138000,
4417 .pa_end = 0x4013807f,
4418 .flags = ADDR_TYPE_RT
4419 },
4420 { }
4421 };
4422
4423 /* l4_abe -> timer5 */
4424 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4425 .master = &omap44xx_l4_abe_hwmod,
4426 .slave = &omap44xx_timer5_hwmod,
4427 .clk = "ocp_abe_iclk",
4428 .addr = omap44xx_timer5_addrs,
4429 .user = OCP_USER_MPU,
4430 };
4431
4432 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4433 {
4434 .pa_start = 0x49038000,
4435 .pa_end = 0x4903807f,
4436 .flags = ADDR_TYPE_RT
4437 },
4438 { }
4439 };
4440
4441 /* l4_abe -> timer5 (dma) */
4442 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4443 .master = &omap44xx_l4_abe_hwmod,
4444 .slave = &omap44xx_timer5_hwmod,
4445 .clk = "ocp_abe_iclk",
4446 .addr = omap44xx_timer5_dma_addrs,
4447 .user = OCP_USER_SDMA,
4448 };
4449
4450 /* timer5 slave ports */
4451 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4452 &omap44xx_l4_abe__timer5,
4453 &omap44xx_l4_abe__timer5_dma,
4454 };
4455
4456 static struct omap_hwmod omap44xx_timer5_hwmod = {
4457 .name = "timer5",
4458 .class = &omap44xx_timer_hwmod_class,
4459 .clkdm_name = "abe_clkdm",
4460 .mpu_irqs = omap44xx_timer5_irqs,
4461 .main_clk = "timer5_fck",
4462 .prcm = {
4463 .omap4 = {
4464 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4465 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4466 .modulemode = MODULEMODE_SWCTRL,
4467 },
4468 },
4469 .dev_attr = &capability_alwon_dev_attr,
4470 .slaves = omap44xx_timer5_slaves,
4471 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4472 };
4473
4474 /* timer6 */
4475 static struct omap_hwmod omap44xx_timer6_hwmod;
4476 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4477 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4478 { .irq = -1 }
4479 };
4480
4481 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4482 {
4483 .pa_start = 0x4013a000,
4484 .pa_end = 0x4013a07f,
4485 .flags = ADDR_TYPE_RT
4486 },
4487 { }
4488 };
4489
4490 /* l4_abe -> timer6 */
4491 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4492 .master = &omap44xx_l4_abe_hwmod,
4493 .slave = &omap44xx_timer6_hwmod,
4494 .clk = "ocp_abe_iclk",
4495 .addr = omap44xx_timer6_addrs,
4496 .user = OCP_USER_MPU,
4497 };
4498
4499 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4500 {
4501 .pa_start = 0x4903a000,
4502 .pa_end = 0x4903a07f,
4503 .flags = ADDR_TYPE_RT
4504 },
4505 { }
4506 };
4507
4508 /* l4_abe -> timer6 (dma) */
4509 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4510 .master = &omap44xx_l4_abe_hwmod,
4511 .slave = &omap44xx_timer6_hwmod,
4512 .clk = "ocp_abe_iclk",
4513 .addr = omap44xx_timer6_dma_addrs,
4514 .user = OCP_USER_SDMA,
4515 };
4516
4517 /* timer6 slave ports */
4518 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4519 &omap44xx_l4_abe__timer6,
4520 &omap44xx_l4_abe__timer6_dma,
4521 };
4522
4523 static struct omap_hwmod omap44xx_timer6_hwmod = {
4524 .name = "timer6",
4525 .class = &omap44xx_timer_hwmod_class,
4526 .clkdm_name = "abe_clkdm",
4527 .mpu_irqs = omap44xx_timer6_irqs,
4528
4529 .main_clk = "timer6_fck",
4530 .prcm = {
4531 .omap4 = {
4532 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4533 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4534 .modulemode = MODULEMODE_SWCTRL,
4535 },
4536 },
4537 .dev_attr = &capability_alwon_dev_attr,
4538 .slaves = omap44xx_timer6_slaves,
4539 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4540 };
4541
4542 /* timer7 */
4543 static struct omap_hwmod omap44xx_timer7_hwmod;
4544 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4545 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4546 { .irq = -1 }
4547 };
4548
4549 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4550 {
4551 .pa_start = 0x4013c000,
4552 .pa_end = 0x4013c07f,
4553 .flags = ADDR_TYPE_RT
4554 },
4555 { }
4556 };
4557
4558 /* l4_abe -> timer7 */
4559 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4560 .master = &omap44xx_l4_abe_hwmod,
4561 .slave = &omap44xx_timer7_hwmod,
4562 .clk = "ocp_abe_iclk",
4563 .addr = omap44xx_timer7_addrs,
4564 .user = OCP_USER_MPU,
4565 };
4566
4567 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4568 {
4569 .pa_start = 0x4903c000,
4570 .pa_end = 0x4903c07f,
4571 .flags = ADDR_TYPE_RT
4572 },
4573 { }
4574 };
4575
4576 /* l4_abe -> timer7 (dma) */
4577 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4578 .master = &omap44xx_l4_abe_hwmod,
4579 .slave = &omap44xx_timer7_hwmod,
4580 .clk = "ocp_abe_iclk",
4581 .addr = omap44xx_timer7_dma_addrs,
4582 .user = OCP_USER_SDMA,
4583 };
4584
4585 /* timer7 slave ports */
4586 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4587 &omap44xx_l4_abe__timer7,
4588 &omap44xx_l4_abe__timer7_dma,
4589 };
4590
4591 static struct omap_hwmod omap44xx_timer7_hwmod = {
4592 .name = "timer7",
4593 .class = &omap44xx_timer_hwmod_class,
4594 .clkdm_name = "abe_clkdm",
4595 .mpu_irqs = omap44xx_timer7_irqs,
4596 .main_clk = "timer7_fck",
4597 .prcm = {
4598 .omap4 = {
4599 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4600 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4601 .modulemode = MODULEMODE_SWCTRL,
4602 },
4603 },
4604 .dev_attr = &capability_alwon_dev_attr,
4605 .slaves = omap44xx_timer7_slaves,
4606 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4607 };
4608
4609 /* timer8 */
4610 static struct omap_hwmod omap44xx_timer8_hwmod;
4611 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4612 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4613 { .irq = -1 }
4614 };
4615
4616 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4617 {
4618 .pa_start = 0x4013e000,
4619 .pa_end = 0x4013e07f,
4620 .flags = ADDR_TYPE_RT
4621 },
4622 { }
4623 };
4624
4625 /* l4_abe -> timer8 */
4626 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4627 .master = &omap44xx_l4_abe_hwmod,
4628 .slave = &omap44xx_timer8_hwmod,
4629 .clk = "ocp_abe_iclk",
4630 .addr = omap44xx_timer8_addrs,
4631 .user = OCP_USER_MPU,
4632 };
4633
4634 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4635 {
4636 .pa_start = 0x4903e000,
4637 .pa_end = 0x4903e07f,
4638 .flags = ADDR_TYPE_RT
4639 },
4640 { }
4641 };
4642
4643 /* l4_abe -> timer8 (dma) */
4644 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4645 .master = &omap44xx_l4_abe_hwmod,
4646 .slave = &omap44xx_timer8_hwmod,
4647 .clk = "ocp_abe_iclk",
4648 .addr = omap44xx_timer8_dma_addrs,
4649 .user = OCP_USER_SDMA,
4650 };
4651
4652 /* timer8 slave ports */
4653 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4654 &omap44xx_l4_abe__timer8,
4655 &omap44xx_l4_abe__timer8_dma,
4656 };
4657
4658 static struct omap_hwmod omap44xx_timer8_hwmod = {
4659 .name = "timer8",
4660 .class = &omap44xx_timer_hwmod_class,
4661 .clkdm_name = "abe_clkdm",
4662 .mpu_irqs = omap44xx_timer8_irqs,
4663 .main_clk = "timer8_fck",
4664 .prcm = {
4665 .omap4 = {
4666 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4667 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4668 .modulemode = MODULEMODE_SWCTRL,
4669 },
4670 },
4671 .dev_attr = &capability_pwm_dev_attr,
4672 .slaves = omap44xx_timer8_slaves,
4673 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4674 };
4675
4676 /* timer9 */
4677 static struct omap_hwmod omap44xx_timer9_hwmod;
4678 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4679 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4680 { .irq = -1 }
4681 };
4682
4683 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4684 {
4685 .pa_start = 0x4803e000,
4686 .pa_end = 0x4803e07f,
4687 .flags = ADDR_TYPE_RT
4688 },
4689 { }
4690 };
4691
4692 /* l4_per -> timer9 */
4693 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4694 .master = &omap44xx_l4_per_hwmod,
4695 .slave = &omap44xx_timer9_hwmod,
4696 .clk = "l4_div_ck",
4697 .addr = omap44xx_timer9_addrs,
4698 .user = OCP_USER_MPU | OCP_USER_SDMA,
4699 };
4700
4701 /* timer9 slave ports */
4702 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4703 &omap44xx_l4_per__timer9,
4704 };
4705
4706 static struct omap_hwmod omap44xx_timer9_hwmod = {
4707 .name = "timer9",
4708 .class = &omap44xx_timer_hwmod_class,
4709 .clkdm_name = "l4_per_clkdm",
4710 .mpu_irqs = omap44xx_timer9_irqs,
4711 .main_clk = "timer9_fck",
4712 .prcm = {
4713 .omap4 = {
4714 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4715 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4716 .modulemode = MODULEMODE_SWCTRL,
4717 },
4718 },
4719 .dev_attr = &capability_pwm_dev_attr,
4720 .slaves = omap44xx_timer9_slaves,
4721 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4722 };
4723
4724 /* timer10 */
4725 static struct omap_hwmod omap44xx_timer10_hwmod;
4726 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4727 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4728 { .irq = -1 }
4729 };
4730
4731 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4732 {
4733 .pa_start = 0x48086000,
4734 .pa_end = 0x4808607f,
4735 .flags = ADDR_TYPE_RT
4736 },
4737 { }
4738 };
4739
4740 /* l4_per -> timer10 */
4741 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4742 .master = &omap44xx_l4_per_hwmod,
4743 .slave = &omap44xx_timer10_hwmod,
4744 .clk = "l4_div_ck",
4745 .addr = omap44xx_timer10_addrs,
4746 .user = OCP_USER_MPU | OCP_USER_SDMA,
4747 };
4748
4749 /* timer10 slave ports */
4750 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4751 &omap44xx_l4_per__timer10,
4752 };
4753
4754 static struct omap_hwmod omap44xx_timer10_hwmod = {
4755 .name = "timer10",
4756 .class = &omap44xx_timer_1ms_hwmod_class,
4757 .clkdm_name = "l4_per_clkdm",
4758 .mpu_irqs = omap44xx_timer10_irqs,
4759 .main_clk = "timer10_fck",
4760 .prcm = {
4761 .omap4 = {
4762 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4763 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4764 .modulemode = MODULEMODE_SWCTRL,
4765 },
4766 },
4767 .dev_attr = &capability_pwm_dev_attr,
4768 .slaves = omap44xx_timer10_slaves,
4769 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4770 };
4771
4772 /* timer11 */
4773 static struct omap_hwmod omap44xx_timer11_hwmod;
4774 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4775 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4776 { .irq = -1 }
4777 };
4778
4779 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4780 {
4781 .pa_start = 0x48088000,
4782 .pa_end = 0x4808807f,
4783 .flags = ADDR_TYPE_RT
4784 },
4785 { }
4786 };
4787
4788 /* l4_per -> timer11 */
4789 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4790 .master = &omap44xx_l4_per_hwmod,
4791 .slave = &omap44xx_timer11_hwmod,
4792 .clk = "l4_div_ck",
4793 .addr = omap44xx_timer11_addrs,
4794 .user = OCP_USER_MPU | OCP_USER_SDMA,
4795 };
4796
4797 /* timer11 slave ports */
4798 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4799 &omap44xx_l4_per__timer11,
4800 };
4801
4802 static struct omap_hwmod omap44xx_timer11_hwmod = {
4803 .name = "timer11",
4804 .class = &omap44xx_timer_hwmod_class,
4805 .clkdm_name = "l4_per_clkdm",
4806 .mpu_irqs = omap44xx_timer11_irqs,
4807 .main_clk = "timer11_fck",
4808 .prcm = {
4809 .omap4 = {
4810 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4811 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4812 .modulemode = MODULEMODE_SWCTRL,
4813 },
4814 },
4815 .dev_attr = &capability_pwm_dev_attr,
4816 .slaves = omap44xx_timer11_slaves,
4817 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4818 };
4819
4820 /*
4821 * 'uart' class
4822 * universal asynchronous receiver/transmitter (uart)
4823 */
4824
4825 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4826 .rev_offs = 0x0050,
4827 .sysc_offs = 0x0054,
4828 .syss_offs = 0x0058,
4829 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4830 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4831 SYSS_HAS_RESET_STATUS),
4832 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4833 SIDLE_SMART_WKUP),
4834 .sysc_fields = &omap_hwmod_sysc_type1,
4835 };
4836
4837 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4838 .name = "uart",
4839 .sysc = &omap44xx_uart_sysc,
4840 };
4841
4842 /* uart1 */
4843 static struct omap_hwmod omap44xx_uart1_hwmod;
4844 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4845 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4846 { .irq = -1 }
4847 };
4848
4849 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4850 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4851 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4852 { .dma_req = -1 }
4853 };
4854
4855 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4856 {
4857 .pa_start = 0x4806a000,
4858 .pa_end = 0x4806a0ff,
4859 .flags = ADDR_TYPE_RT
4860 },
4861 { }
4862 };
4863
4864 /* l4_per -> uart1 */
4865 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4866 .master = &omap44xx_l4_per_hwmod,
4867 .slave = &omap44xx_uart1_hwmod,
4868 .clk = "l4_div_ck",
4869 .addr = omap44xx_uart1_addrs,
4870 .user = OCP_USER_MPU | OCP_USER_SDMA,
4871 };
4872
4873 /* uart1 slave ports */
4874 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4875 &omap44xx_l4_per__uart1,
4876 };
4877
4878 static struct omap_hwmod omap44xx_uart1_hwmod = {
4879 .name = "uart1",
4880 .class = &omap44xx_uart_hwmod_class,
4881 .clkdm_name = "l4_per_clkdm",
4882 .mpu_irqs = omap44xx_uart1_irqs,
4883 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4884 .main_clk = "uart1_fck",
4885 .prcm = {
4886 .omap4 = {
4887 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4888 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4889 .modulemode = MODULEMODE_SWCTRL,
4890 },
4891 },
4892 .slaves = omap44xx_uart1_slaves,
4893 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4894 };
4895
4896 /* uart2 */
4897 static struct omap_hwmod omap44xx_uart2_hwmod;
4898 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4899 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4900 { .irq = -1 }
4901 };
4902
4903 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4904 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4905 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4906 { .dma_req = -1 }
4907 };
4908
4909 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4910 {
4911 .pa_start = 0x4806c000,
4912 .pa_end = 0x4806c0ff,
4913 .flags = ADDR_TYPE_RT
4914 },
4915 { }
4916 };
4917
4918 /* l4_per -> uart2 */
4919 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4920 .master = &omap44xx_l4_per_hwmod,
4921 .slave = &omap44xx_uart2_hwmod,
4922 .clk = "l4_div_ck",
4923 .addr = omap44xx_uart2_addrs,
4924 .user = OCP_USER_MPU | OCP_USER_SDMA,
4925 };
4926
4927 /* uart2 slave ports */
4928 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4929 &omap44xx_l4_per__uart2,
4930 };
4931
4932 static struct omap_hwmod omap44xx_uart2_hwmod = {
4933 .name = "uart2",
4934 .class = &omap44xx_uart_hwmod_class,
4935 .clkdm_name = "l4_per_clkdm",
4936 .mpu_irqs = omap44xx_uart2_irqs,
4937 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4938 .main_clk = "uart2_fck",
4939 .prcm = {
4940 .omap4 = {
4941 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4942 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4943 .modulemode = MODULEMODE_SWCTRL,
4944 },
4945 },
4946 .slaves = omap44xx_uart2_slaves,
4947 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
4948 };
4949
4950 /* uart3 */
4951 static struct omap_hwmod omap44xx_uart3_hwmod;
4952 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4953 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4954 { .irq = -1 }
4955 };
4956
4957 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4958 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4959 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4960 { .dma_req = -1 }
4961 };
4962
4963 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4964 {
4965 .pa_start = 0x48020000,
4966 .pa_end = 0x480200ff,
4967 .flags = ADDR_TYPE_RT
4968 },
4969 { }
4970 };
4971
4972 /* l4_per -> uart3 */
4973 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4974 .master = &omap44xx_l4_per_hwmod,
4975 .slave = &omap44xx_uart3_hwmod,
4976 .clk = "l4_div_ck",
4977 .addr = omap44xx_uart3_addrs,
4978 .user = OCP_USER_MPU | OCP_USER_SDMA,
4979 };
4980
4981 /* uart3 slave ports */
4982 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4983 &omap44xx_l4_per__uart3,
4984 };
4985
4986 static struct omap_hwmod omap44xx_uart3_hwmod = {
4987 .name = "uart3",
4988 .class = &omap44xx_uart_hwmod_class,
4989 .clkdm_name = "l4_per_clkdm",
4990 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4991 .mpu_irqs = omap44xx_uart3_irqs,
4992 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4993 .main_clk = "uart3_fck",
4994 .prcm = {
4995 .omap4 = {
4996 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
4997 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
4998 .modulemode = MODULEMODE_SWCTRL,
4999 },
5000 },
5001 .slaves = omap44xx_uart3_slaves,
5002 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
5003 };
5004
5005 /* uart4 */
5006 static struct omap_hwmod omap44xx_uart4_hwmod;
5007 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5008 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5009 { .irq = -1 }
5010 };
5011
5012 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5013 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5014 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5015 { .dma_req = -1 }
5016 };
5017
5018 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5019 {
5020 .pa_start = 0x4806e000,
5021 .pa_end = 0x4806e0ff,
5022 .flags = ADDR_TYPE_RT
5023 },
5024 { }
5025 };
5026
5027 /* l4_per -> uart4 */
5028 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5029 .master = &omap44xx_l4_per_hwmod,
5030 .slave = &omap44xx_uart4_hwmod,
5031 .clk = "l4_div_ck",
5032 .addr = omap44xx_uart4_addrs,
5033 .user = OCP_USER_MPU | OCP_USER_SDMA,
5034 };
5035
5036 /* uart4 slave ports */
5037 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5038 &omap44xx_l4_per__uart4,
5039 };
5040
5041 static struct omap_hwmod omap44xx_uart4_hwmod = {
5042 .name = "uart4",
5043 .class = &omap44xx_uart_hwmod_class,
5044 .clkdm_name = "l4_per_clkdm",
5045 .mpu_irqs = omap44xx_uart4_irqs,
5046 .sdma_reqs = omap44xx_uart4_sdma_reqs,
5047 .main_clk = "uart4_fck",
5048 .prcm = {
5049 .omap4 = {
5050 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5051 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5052 .modulemode = MODULEMODE_SWCTRL,
5053 },
5054 },
5055 .slaves = omap44xx_uart4_slaves,
5056 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
5057 };
5058
5059 /*
5060 * 'usb_otg_hs' class
5061 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5062 */
5063
5064 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5065 .rev_offs = 0x0400,
5066 .sysc_offs = 0x0404,
5067 .syss_offs = 0x0408,
5068 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5069 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5070 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5071 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5072 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5073 MSTANDBY_SMART),
5074 .sysc_fields = &omap_hwmod_sysc_type1,
5075 };
5076
5077 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5078 .name = "usb_otg_hs",
5079 .sysc = &omap44xx_usb_otg_hs_sysc,
5080 };
5081
5082 /* usb_otg_hs */
5083 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5084 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5085 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5086 { .irq = -1 }
5087 };
5088
5089 /* usb_otg_hs master ports */
5090 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5091 &omap44xx_usb_otg_hs__l3_main_2,
5092 };
5093
5094 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5095 {
5096 .pa_start = 0x4a0ab000,
5097 .pa_end = 0x4a0ab003,
5098 .flags = ADDR_TYPE_RT
5099 },
5100 { }
5101 };
5102
5103 /* l4_cfg -> usb_otg_hs */
5104 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5105 .master = &omap44xx_l4_cfg_hwmod,
5106 .slave = &omap44xx_usb_otg_hs_hwmod,
5107 .clk = "l4_div_ck",
5108 .addr = omap44xx_usb_otg_hs_addrs,
5109 .user = OCP_USER_MPU | OCP_USER_SDMA,
5110 };
5111
5112 /* usb_otg_hs slave ports */
5113 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5114 &omap44xx_l4_cfg__usb_otg_hs,
5115 };
5116
5117 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5118 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5119 };
5120
5121 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5122 .name = "usb_otg_hs",
5123 .class = &omap44xx_usb_otg_hs_hwmod_class,
5124 .clkdm_name = "l3_init_clkdm",
5125 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5126 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5127 .main_clk = "usb_otg_hs_ick",
5128 .prcm = {
5129 .omap4 = {
5130 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5131 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5132 .modulemode = MODULEMODE_HWCTRL,
5133 },
5134 },
5135 .opt_clks = usb_otg_hs_opt_clks,
5136 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5137 .slaves = omap44xx_usb_otg_hs_slaves,
5138 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5139 .masters = omap44xx_usb_otg_hs_masters,
5140 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5141 };
5142
5143 /*
5144 * 'wd_timer' class
5145 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5146 * overflow condition
5147 */
5148
5149 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5150 .rev_offs = 0x0000,
5151 .sysc_offs = 0x0010,
5152 .syss_offs = 0x0014,
5153 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5154 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5156 SIDLE_SMART_WKUP),
5157 .sysc_fields = &omap_hwmod_sysc_type1,
5158 };
5159
5160 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5161 .name = "wd_timer",
5162 .sysc = &omap44xx_wd_timer_sysc,
5163 .pre_shutdown = &omap2_wd_timer_disable,
5164 };
5165
5166 /* wd_timer2 */
5167 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5168 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5169 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5170 { .irq = -1 }
5171 };
5172
5173 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5174 {
5175 .pa_start = 0x4a314000,
5176 .pa_end = 0x4a31407f,
5177 .flags = ADDR_TYPE_RT
5178 },
5179 { }
5180 };
5181
5182 /* l4_wkup -> wd_timer2 */
5183 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5184 .master = &omap44xx_l4_wkup_hwmod,
5185 .slave = &omap44xx_wd_timer2_hwmod,
5186 .clk = "l4_wkup_clk_mux_ck",
5187 .addr = omap44xx_wd_timer2_addrs,
5188 .user = OCP_USER_MPU | OCP_USER_SDMA,
5189 };
5190
5191 /* wd_timer2 slave ports */
5192 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5193 &omap44xx_l4_wkup__wd_timer2,
5194 };
5195
5196 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5197 .name = "wd_timer2",
5198 .class = &omap44xx_wd_timer_hwmod_class,
5199 .clkdm_name = "l4_wkup_clkdm",
5200 .mpu_irqs = omap44xx_wd_timer2_irqs,
5201 .main_clk = "wd_timer2_fck",
5202 .prcm = {
5203 .omap4 = {
5204 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5205 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5206 .modulemode = MODULEMODE_SWCTRL,
5207 },
5208 },
5209 .slaves = omap44xx_wd_timer2_slaves,
5210 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5211 };
5212
5213 /* wd_timer3 */
5214 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5215 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5216 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5217 { .irq = -1 }
5218 };
5219
5220 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5221 {
5222 .pa_start = 0x40130000,
5223 .pa_end = 0x4013007f,
5224 .flags = ADDR_TYPE_RT
5225 },
5226 { }
5227 };
5228
5229 /* l4_abe -> wd_timer3 */
5230 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5231 .master = &omap44xx_l4_abe_hwmod,
5232 .slave = &omap44xx_wd_timer3_hwmod,
5233 .clk = "ocp_abe_iclk",
5234 .addr = omap44xx_wd_timer3_addrs,
5235 .user = OCP_USER_MPU,
5236 };
5237
5238 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5239 {
5240 .pa_start = 0x49030000,
5241 .pa_end = 0x4903007f,
5242 .flags = ADDR_TYPE_RT
5243 },
5244 { }
5245 };
5246
5247 /* l4_abe -> wd_timer3 (dma) */
5248 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5249 .master = &omap44xx_l4_abe_hwmod,
5250 .slave = &omap44xx_wd_timer3_hwmod,
5251 .clk = "ocp_abe_iclk",
5252 .addr = omap44xx_wd_timer3_dma_addrs,
5253 .user = OCP_USER_SDMA,
5254 };
5255
5256 /* wd_timer3 slave ports */
5257 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5258 &omap44xx_l4_abe__wd_timer3,
5259 &omap44xx_l4_abe__wd_timer3_dma,
5260 };
5261
5262 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5263 .name = "wd_timer3",
5264 .class = &omap44xx_wd_timer_hwmod_class,
5265 .clkdm_name = "abe_clkdm",
5266 .mpu_irqs = omap44xx_wd_timer3_irqs,
5267 .main_clk = "wd_timer3_fck",
5268 .prcm = {
5269 .omap4 = {
5270 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5271 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5272 .modulemode = MODULEMODE_SWCTRL,
5273 },
5274 },
5275 .slaves = omap44xx_wd_timer3_slaves,
5276 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5277 };
5278
5279 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5280
5281 /* dmm class */
5282 &omap44xx_dmm_hwmod,
5283
5284 /* emif_fw class */
5285 &omap44xx_emif_fw_hwmod,
5286
5287 /* l3 class */
5288 &omap44xx_l3_instr_hwmod,
5289 &omap44xx_l3_main_1_hwmod,
5290 &omap44xx_l3_main_2_hwmod,
5291 &omap44xx_l3_main_3_hwmod,
5292
5293 /* l4 class */
5294 &omap44xx_l4_abe_hwmod,
5295 &omap44xx_l4_cfg_hwmod,
5296 &omap44xx_l4_per_hwmod,
5297 &omap44xx_l4_wkup_hwmod,
5298
5299 /* mpu_bus class */
5300 &omap44xx_mpu_private_hwmod,
5301
5302 /* aess class */
5303 /* &omap44xx_aess_hwmod, */
5304
5305 /* bandgap class */
5306 &omap44xx_bandgap_hwmod,
5307
5308 /* counter class */
5309 /* &omap44xx_counter_32k_hwmod, */
5310
5311 /* dma class */
5312 &omap44xx_dma_system_hwmod,
5313
5314 /* dmic class */
5315 &omap44xx_dmic_hwmod,
5316
5317 /* dsp class */
5318 &omap44xx_dsp_hwmod,
5319 &omap44xx_dsp_c0_hwmod,
5320
5321 /* dss class */
5322 &omap44xx_dss_hwmod,
5323 &omap44xx_dss_dispc_hwmod,
5324 &omap44xx_dss_dsi1_hwmod,
5325 &omap44xx_dss_dsi2_hwmod,
5326 &omap44xx_dss_hdmi_hwmod,
5327 &omap44xx_dss_rfbi_hwmod,
5328 &omap44xx_dss_venc_hwmod,
5329
5330 /* gpio class */
5331 &omap44xx_gpio1_hwmod,
5332 &omap44xx_gpio2_hwmod,
5333 &omap44xx_gpio3_hwmod,
5334 &omap44xx_gpio4_hwmod,
5335 &omap44xx_gpio5_hwmod,
5336 &omap44xx_gpio6_hwmod,
5337
5338 /* hsi class */
5339 /* &omap44xx_hsi_hwmod, */
5340
5341 /* i2c class */
5342 &omap44xx_i2c1_hwmod,
5343 &omap44xx_i2c2_hwmod,
5344 &omap44xx_i2c3_hwmod,
5345 &omap44xx_i2c4_hwmod,
5346
5347 /* ipu class */
5348 &omap44xx_ipu_hwmod,
5349 &omap44xx_ipu_c0_hwmod,
5350 &omap44xx_ipu_c1_hwmod,
5351
5352 /* iss class */
5353 /* &omap44xx_iss_hwmod, */
5354
5355 /* iva class */
5356 &omap44xx_iva_hwmod,
5357 &omap44xx_iva_seq0_hwmod,
5358 &omap44xx_iva_seq1_hwmod,
5359
5360 /* kbd class */
5361 &omap44xx_kbd_hwmod,
5362
5363 /* mailbox class */
5364 &omap44xx_mailbox_hwmod,
5365
5366 /* mcbsp class */
5367 &omap44xx_mcbsp1_hwmod,
5368 &omap44xx_mcbsp2_hwmod,
5369 &omap44xx_mcbsp3_hwmod,
5370 &omap44xx_mcbsp4_hwmod,
5371
5372 /* mcpdm class */
5373 &omap44xx_mcpdm_hwmod,
5374
5375 /* mcspi class */
5376 &omap44xx_mcspi1_hwmod,
5377 &omap44xx_mcspi2_hwmod,
5378 &omap44xx_mcspi3_hwmod,
5379 &omap44xx_mcspi4_hwmod,
5380
5381 /* mmc class */
5382 &omap44xx_mmc1_hwmod,
5383 &omap44xx_mmc2_hwmod,
5384 &omap44xx_mmc3_hwmod,
5385 &omap44xx_mmc4_hwmod,
5386 &omap44xx_mmc5_hwmod,
5387
5388 /* mpu class */
5389 &omap44xx_mpu_hwmod,
5390
5391 /* smartreflex class */
5392 &omap44xx_smartreflex_core_hwmod,
5393 &omap44xx_smartreflex_iva_hwmod,
5394 &omap44xx_smartreflex_mpu_hwmod,
5395
5396 /* spinlock class */
5397 &omap44xx_spinlock_hwmod,
5398
5399 /* timer class */
5400 &omap44xx_timer1_hwmod,
5401 &omap44xx_timer2_hwmod,
5402 &omap44xx_timer3_hwmod,
5403 &omap44xx_timer4_hwmod,
5404 &omap44xx_timer5_hwmod,
5405 &omap44xx_timer6_hwmod,
5406 &omap44xx_timer7_hwmod,
5407 &omap44xx_timer8_hwmod,
5408 &omap44xx_timer9_hwmod,
5409 &omap44xx_timer10_hwmod,
5410 &omap44xx_timer11_hwmod,
5411
5412 /* uart class */
5413 &omap44xx_uart1_hwmod,
5414 &omap44xx_uart2_hwmod,
5415 &omap44xx_uart3_hwmod,
5416 &omap44xx_uart4_hwmod,
5417
5418 /* usb_otg_hs class */
5419 &omap44xx_usb_otg_hs_hwmod,
5420
5421 /* wd_timer class */
5422 &omap44xx_wd_timer2_hwmod,
5423 &omap44xx_wd_timer3_hwmod,
5424
5425 NULL,
5426 };
5427
5428 int __init omap44xx_hwmod_init(void)
5429 {
5430 return omap_hwmod_register(omap44xx_hwmods);
5431 }
5432