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Revert "drivers: usb: Fix dependency for USB_HWA_HCD"
[zen-stable.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
blob61908dce978447156f557866055fe93da689fe52
1 /*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
11
12 #include <linux/dma-mapping.h>
13 #include <linux/gpio.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c-gpio.h>
16
17 #include <linux/fb.h>
18 #include <video/atmel_lcdc.h>
19
20 #include <mach/board.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91sam9rl_matrix.h>
23 #include <mach/at91sam9_smc.h>
24 #include <mach/at_hdmac.h>
25
26 #include "generic.h"
27
28
29 /* --------------------------------------------------------------------
30 * HDMAC - AHB DMA Controller
31 * -------------------------------------------------------------------- */
32
33 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
34 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
35
36 static struct at_dma_platform_data atdma_pdata = {
37 .nr_channels = 2,
38 };
39
40 static struct resource hdmac_resources[] = {
41 [0] = {
42 .start = AT91SAM9RL_BASE_DMA,
43 .end = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [2] = {
47 .start = AT91SAM9RL_ID_DMA,
48 .end = AT91SAM9RL_ID_DMA,
49 .flags = IORESOURCE_IRQ,
50 },
51 };
52
53 static struct platform_device at_hdmac_device = {
54 .name = "at_hdmac",
55 .id = -1,
56 .dev = {
57 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &atdma_pdata,
60 },
61 .resource = hdmac_resources,
62 .num_resources = ARRAY_SIZE(hdmac_resources),
63 };
64
65 void __init at91_add_device_hdmac(void)
66 {
67 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
68 platform_device_register(&at_hdmac_device);
69 }
70 #else
71 void __init at91_add_device_hdmac(void) {}
72 #endif
73
74 /* --------------------------------------------------------------------
75 * USB HS Device (Gadget)
76 * -------------------------------------------------------------------- */
77
78 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
79
80 static struct resource usba_udc_resources[] = {
81 [0] = {
82 .start = AT91SAM9RL_UDPHS_FIFO,
83 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
84 .flags = IORESOURCE_MEM,
85 },
86 [1] = {
87 .start = AT91SAM9RL_BASE_UDPHS,
88 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
89 .flags = IORESOURCE_MEM,
90 },
91 [2] = {
92 .start = AT91SAM9RL_ID_UDPHS,
93 .end = AT91SAM9RL_ID_UDPHS,
94 .flags = IORESOURCE_IRQ,
95 },
96 };
97
98 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
99 [idx] = { \
100 .name = nam, \
101 .index = idx, \
102 .fifo_size = maxpkt, \
103 .nr_banks = maxbk, \
104 .can_dma = dma, \
105 .can_isoc = isoc, \
106 }
107
108 static struct usba_ep_data usba_udc_ep[] __initdata = {
109 EP("ep0", 0, 64, 1, 0, 0),
110 EP("ep1", 1, 1024, 2, 1, 1),
111 EP("ep2", 2, 1024, 2, 1, 1),
112 EP("ep3", 3, 1024, 3, 1, 0),
113 EP("ep4", 4, 1024, 3, 1, 0),
114 EP("ep5", 5, 1024, 3, 1, 1),
115 EP("ep6", 6, 1024, 3, 1, 1),
116 };
117
118 #undef EP
119
120 /*
121 * pdata doesn't have room for any endpoints, so we need to
122 * append room for the ones we need right after it.
123 */
124 static struct {
125 struct usba_platform_data pdata;
126 struct usba_ep_data ep[7];
127 } usba_udc_data;
128
129 static struct platform_device at91_usba_udc_device = {
130 .name = "atmel_usba_udc",
131 .id = -1,
132 .dev = {
133 .platform_data = &usba_udc_data.pdata,
134 },
135 .resource = usba_udc_resources,
136 .num_resources = ARRAY_SIZE(usba_udc_resources),
137 };
138
139 void __init at91_add_device_usba(struct usba_platform_data *data)
140 {
141 /*
142 * Invalid pins are 0 on AT91, but the usba driver is shared
143 * with AVR32, which use negative values instead. Once/if
144 * gpio_is_valid() is ported to AT91, revisit this code.
145 */
146 usba_udc_data.pdata.vbus_pin = -EINVAL;
147 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
148 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
149
150 if (data && gpio_is_valid(data->vbus_pin)) {
151 at91_set_gpio_input(data->vbus_pin, 0);
152 at91_set_deglitch(data->vbus_pin, 1);
153 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
154 }
155
156 /* Pullup pin is handled internally by USB device peripheral */
157
158 platform_device_register(&at91_usba_udc_device);
159 }
160 #else
161 void __init at91_add_device_usba(struct usba_platform_data *data) {}
162 #endif
163
164
165 /* --------------------------------------------------------------------
166 * MMC / SD
167 * -------------------------------------------------------------------- */
168
169 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
170 static u64 mmc_dmamask = DMA_BIT_MASK(32);
171 static struct at91_mmc_data mmc_data;
172
173 static struct resource mmc_resources[] = {
174 [0] = {
175 .start = AT91SAM9RL_BASE_MCI,
176 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
177 .flags = IORESOURCE_MEM,
178 },
179 [1] = {
180 .start = AT91SAM9RL_ID_MCI,
181 .end = AT91SAM9RL_ID_MCI,
182 .flags = IORESOURCE_IRQ,
183 },
184 };
185
186 static struct platform_device at91sam9rl_mmc_device = {
187 .name = "at91_mci",
188 .id = -1,
189 .dev = {
190 .dma_mask = &mmc_dmamask,
191 .coherent_dma_mask = DMA_BIT_MASK(32),
192 .platform_data = &mmc_data,
193 },
194 .resource = mmc_resources,
195 .num_resources = ARRAY_SIZE(mmc_resources),
196 };
197
198 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
199 {
200 if (!data)
201 return;
202
203 /* input/irq */
204 if (gpio_is_valid(data->det_pin)) {
205 at91_set_gpio_input(data->det_pin, 1);
206 at91_set_deglitch(data->det_pin, 1);
207 }
208 if (gpio_is_valid(data->wp_pin))
209 at91_set_gpio_input(data->wp_pin, 1);
210 if (gpio_is_valid(data->vcc_pin))
211 at91_set_gpio_output(data->vcc_pin, 0);
212
213 /* CLK */
214 at91_set_A_periph(AT91_PIN_PA2, 0);
215
216 /* CMD */
217 at91_set_A_periph(AT91_PIN_PA1, 1);
218
219 /* DAT0, maybe DAT1..DAT3 */
220 at91_set_A_periph(AT91_PIN_PA0, 1);
221 if (data->wire4) {
222 at91_set_A_periph(AT91_PIN_PA3, 1);
223 at91_set_A_periph(AT91_PIN_PA4, 1);
224 at91_set_A_periph(AT91_PIN_PA5, 1);
225 }
226
227 mmc_data = *data;
228 platform_device_register(&at91sam9rl_mmc_device);
229 }
230 #else
231 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
232 #endif
233
234
235 /* --------------------------------------------------------------------
236 * NAND / SmartMedia
237 * -------------------------------------------------------------------- */
238
239 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
240 static struct atmel_nand_data nand_data;
241
242 #define NAND_BASE AT91_CHIPSELECT_3
243
244 static struct resource nand_resources[] = {
245 [0] = {
246 .start = NAND_BASE,
247 .end = NAND_BASE + SZ_256M - 1,
248 .flags = IORESOURCE_MEM,
249 },
250 [1] = {
251 .start = AT91SAM9RL_BASE_ECC,
252 .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
253 .flags = IORESOURCE_MEM,
254 }
255 };
256
257 static struct platform_device atmel_nand_device = {
258 .name = "atmel_nand",
259 .id = -1,
260 .dev = {
261 .platform_data = &nand_data,
262 },
263 .resource = nand_resources,
264 .num_resources = ARRAY_SIZE(nand_resources),
265 };
266
267 void __init at91_add_device_nand(struct atmel_nand_data *data)
268 {
269 unsigned long csa;
270
271 if (!data)
272 return;
273
274 csa = at91_sys_read(AT91_MATRIX_EBICSA);
275 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
276
277 /* enable pin */
278 if (gpio_is_valid(data->enable_pin))
279 at91_set_gpio_output(data->enable_pin, 1);
280
281 /* ready/busy pin */
282 if (gpio_is_valid(data->rdy_pin))
283 at91_set_gpio_input(data->rdy_pin, 1);
284
285 /* card detect pin */
286 if (gpio_is_valid(data->det_pin))
287 at91_set_gpio_input(data->det_pin, 1);
288
289 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
290 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
291
292 nand_data = *data;
293 platform_device_register(&atmel_nand_device);
294 }
295
296 #else
297 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
298 #endif
299
300
301 /* --------------------------------------------------------------------
302 * TWI (i2c)
303 * -------------------------------------------------------------------- */
304
305 /*
306 * Prefer the GPIO code since the TWI controller isn't robust
307 * (gets overruns and underruns under load) and can only issue
308 * repeated STARTs in one scenario (the driver doesn't yet handle them).
309 */
310 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
311
312 static struct i2c_gpio_platform_data pdata = {
313 .sda_pin = AT91_PIN_PA23,
314 .sda_is_open_drain = 1,
315 .scl_pin = AT91_PIN_PA24,
316 .scl_is_open_drain = 1,
317 .udelay = 2, /* ~100 kHz */
318 };
319
320 static struct platform_device at91sam9rl_twi_device = {
321 .name = "i2c-gpio",
322 .id = -1,
323 .dev.platform_data = &pdata,
324 };
325
326 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
327 {
328 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
329 at91_set_multi_drive(AT91_PIN_PA23, 1);
330
331 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
332 at91_set_multi_drive(AT91_PIN_PA24, 1);
333
334 i2c_register_board_info(0, devices, nr_devices);
335 platform_device_register(&at91sam9rl_twi_device);
336 }
337
338 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
339
340 static struct resource twi_resources[] = {
341 [0] = {
342 .start = AT91SAM9RL_BASE_TWI0,
343 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
344 .flags = IORESOURCE_MEM,
345 },
346 [1] = {
347 .start = AT91SAM9RL_ID_TWI0,
348 .end = AT91SAM9RL_ID_TWI0,
349 .flags = IORESOURCE_IRQ,
350 },
351 };
352
353 static struct platform_device at91sam9rl_twi_device = {
354 .name = "at91_i2c",
355 .id = -1,
356 .resource = twi_resources,
357 .num_resources = ARRAY_SIZE(twi_resources),
358 };
359
360 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
361 {
362 /* pins used for TWI interface */
363 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
364 at91_set_multi_drive(AT91_PIN_PA23, 1);
365
366 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
367 at91_set_multi_drive(AT91_PIN_PA24, 1);
368
369 i2c_register_board_info(0, devices, nr_devices);
370 platform_device_register(&at91sam9rl_twi_device);
371 }
372 #else
373 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
374 #endif
375
376
377 /* --------------------------------------------------------------------
378 * SPI
379 * -------------------------------------------------------------------- */
380
381 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
382 static u64 spi_dmamask = DMA_BIT_MASK(32);
383
384 static struct resource spi_resources[] = {
385 [0] = {
386 .start = AT91SAM9RL_BASE_SPI,
387 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
388 .flags = IORESOURCE_MEM,
389 },
390 [1] = {
391 .start = AT91SAM9RL_ID_SPI,
392 .end = AT91SAM9RL_ID_SPI,
393 .flags = IORESOURCE_IRQ,
394 },
395 };
396
397 static struct platform_device at91sam9rl_spi_device = {
398 .name = "atmel_spi",
399 .id = 0,
400 .dev = {
401 .dma_mask = &spi_dmamask,
402 .coherent_dma_mask = DMA_BIT_MASK(32),
403 },
404 .resource = spi_resources,
405 .num_resources = ARRAY_SIZE(spi_resources),
406 };
407
408 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
409
410
411 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
412 {
413 int i;
414 unsigned long cs_pin;
415
416 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
417 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
418 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
419
420 /* Enable SPI chip-selects */
421 for (i = 0; i < nr_devices; i++) {
422 if (devices[i].controller_data)
423 cs_pin = (unsigned long) devices[i].controller_data;
424 else
425 cs_pin = spi_standard_cs[devices[i].chip_select];
426
427 /* enable chip-select pin */
428 at91_set_gpio_output(cs_pin, 1);
429
430 /* pass chip-select pin to driver */
431 devices[i].controller_data = (void *) cs_pin;
432 }
433
434 spi_register_board_info(devices, nr_devices);
435 platform_device_register(&at91sam9rl_spi_device);
436 }
437 #else
438 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
439 #endif
440
441
442 /* --------------------------------------------------------------------
443 * AC97
444 * -------------------------------------------------------------------- */
445
446 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
447 static u64 ac97_dmamask = DMA_BIT_MASK(32);
448 static struct ac97c_platform_data ac97_data;
449
450 static struct resource ac97_resources[] = {
451 [0] = {
452 .start = AT91SAM9RL_BASE_AC97C,
453 .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1,
454 .flags = IORESOURCE_MEM,
455 },
456 [1] = {
457 .start = AT91SAM9RL_ID_AC97C,
458 .end = AT91SAM9RL_ID_AC97C,
459 .flags = IORESOURCE_IRQ,
460 },
461 };
462
463 static struct platform_device at91sam9rl_ac97_device = {
464 .name = "atmel_ac97c",
465 .id = 0,
466 .dev = {
467 .dma_mask = &ac97_dmamask,
468 .coherent_dma_mask = DMA_BIT_MASK(32),
469 .platform_data = &ac97_data,
470 },
471 .resource = ac97_resources,
472 .num_resources = ARRAY_SIZE(ac97_resources),
473 };
474
475 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
476 {
477 if (!data)
478 return;
479
480 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */
481 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */
482 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */
483 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
484
485 /* reset */
486 if (gpio_is_valid(data->reset_pin))
487 at91_set_gpio_output(data->reset_pin, 0);
488
489 ac97_data = *data;
490 platform_device_register(&at91sam9rl_ac97_device);
491 }
492 #else
493 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
494 #endif
495
496
497 /* --------------------------------------------------------------------
498 * LCD Controller
499 * -------------------------------------------------------------------- */
500
501 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
502 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
503 static struct atmel_lcdfb_info lcdc_data;
504
505 static struct resource lcdc_resources[] = {
506 [0] = {
507 .start = AT91SAM9RL_LCDC_BASE,
508 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
509 .flags = IORESOURCE_MEM,
510 },
511 [1] = {
512 .start = AT91SAM9RL_ID_LCDC,
513 .end = AT91SAM9RL_ID_LCDC,
514 .flags = IORESOURCE_IRQ,
515 },
516 };
517
518 static struct platform_device at91_lcdc_device = {
519 .name = "atmel_lcdfb",
520 .id = 0,
521 .dev = {
522 .dma_mask = &lcdc_dmamask,
523 .coherent_dma_mask = DMA_BIT_MASK(32),
524 .platform_data = &lcdc_data,
525 },
526 .resource = lcdc_resources,
527 .num_resources = ARRAY_SIZE(lcdc_resources),
528 };
529
530 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
531 {
532 if (!data) {
533 return;
534 }
535
536 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
537 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
538 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
539 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
540 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
541 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
542 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
543 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
544 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
545 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
546 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
547 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
548 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
549 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
550 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
551 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
552 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
553 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
554 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
555 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
556 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
557
558 lcdc_data = *data;
559 platform_device_register(&at91_lcdc_device);
560 }
561 #else
562 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
563 #endif
564
565
566 /* --------------------------------------------------------------------
567 * Timer/Counter block
568 * -------------------------------------------------------------------- */
569
570 #ifdef CONFIG_ATMEL_TCLIB
571
572 static struct resource tcb_resources[] = {
573 [0] = {
574 .start = AT91SAM9RL_BASE_TCB0,
575 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
576 .flags = IORESOURCE_MEM,
577 },
578 [1] = {
579 .start = AT91SAM9RL_ID_TC0,
580 .end = AT91SAM9RL_ID_TC0,
581 .flags = IORESOURCE_IRQ,
582 },
583 [2] = {
584 .start = AT91SAM9RL_ID_TC1,
585 .end = AT91SAM9RL_ID_TC1,
586 .flags = IORESOURCE_IRQ,
587 },
588 [3] = {
589 .start = AT91SAM9RL_ID_TC2,
590 .end = AT91SAM9RL_ID_TC2,
591 .flags = IORESOURCE_IRQ,
592 },
593 };
594
595 static struct platform_device at91sam9rl_tcb_device = {
596 .name = "atmel_tcb",
597 .id = 0,
598 .resource = tcb_resources,
599 .num_resources = ARRAY_SIZE(tcb_resources),
600 };
601
602 static void __init at91_add_device_tc(void)
603 {
604 platform_device_register(&at91sam9rl_tcb_device);
605 }
606 #else
607 static void __init at91_add_device_tc(void) { }
608 #endif
609
610
611 /* --------------------------------------------------------------------
612 * Touchscreen
613 * -------------------------------------------------------------------- */
614
615 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
616 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
617 static struct at91_tsadcc_data tsadcc_data;
618
619 static struct resource tsadcc_resources[] = {
620 [0] = {
621 .start = AT91SAM9RL_BASE_TSC,
622 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
623 .flags = IORESOURCE_MEM,
624 },
625 [1] = {
626 .start = AT91SAM9RL_ID_TSC,
627 .end = AT91SAM9RL_ID_TSC,
628 .flags = IORESOURCE_IRQ,
629 }
630 };
631
632 static struct platform_device at91sam9rl_tsadcc_device = {
633 .name = "atmel_tsadcc",
634 .id = -1,
635 .dev = {
636 .dma_mask = &tsadcc_dmamask,
637 .coherent_dma_mask = DMA_BIT_MASK(32),
638 .platform_data = &tsadcc_data,
639 },
640 .resource = tsadcc_resources,
641 .num_resources = ARRAY_SIZE(tsadcc_resources),
642 };
643
644 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
645 {
646 if (!data)
647 return;
648
649 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
650 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
651 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
652 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
653
654 tsadcc_data = *data;
655 platform_device_register(&at91sam9rl_tsadcc_device);
656 }
657 #else
658 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
659 #endif
660
661
662 /* --------------------------------------------------------------------
663 * RTC
664 * -------------------------------------------------------------------- */
665
666 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
667 static struct platform_device at91sam9rl_rtc_device = {
668 .name = "at91_rtc",
669 .id = -1,
670 .num_resources = 0,
671 };
672
673 static void __init at91_add_device_rtc(void)
674 {
675 platform_device_register(&at91sam9rl_rtc_device);
676 }
677 #else
678 static void __init at91_add_device_rtc(void) {}
679 #endif
680
681
682 /* --------------------------------------------------------------------
683 * RTT
684 * -------------------------------------------------------------------- */
685
686 static struct resource rtt_resources[] = {
687 {
688 .start = AT91SAM9RL_BASE_RTT,
689 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
690 .flags = IORESOURCE_MEM,
691 }
692 };
693
694 static struct platform_device at91sam9rl_rtt_device = {
695 .name = "at91_rtt",
696 .id = 0,
697 .resource = rtt_resources,
698 .num_resources = ARRAY_SIZE(rtt_resources),
699 };
700
701 static void __init at91_add_device_rtt(void)
702 {
703 platform_device_register(&at91sam9rl_rtt_device);
704 }
705
706
707 /* --------------------------------------------------------------------
708 * Watchdog
709 * -------------------------------------------------------------------- */
710
711 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
712 static struct resource wdt_resources[] = {
713 {
714 .start = AT91SAM9RL_BASE_WDT,
715 .end = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
716 .flags = IORESOURCE_MEM,
717 }
718 };
719
720 static struct platform_device at91sam9rl_wdt_device = {
721 .name = "at91_wdt",
722 .id = -1,
723 .resource = wdt_resources,
724 .num_resources = ARRAY_SIZE(wdt_resources),
725 };
726
727 static void __init at91_add_device_watchdog(void)
728 {
729 platform_device_register(&at91sam9rl_wdt_device);
730 }
731 #else
732 static void __init at91_add_device_watchdog(void) {}
733 #endif
734
735
736 /* --------------------------------------------------------------------
737 * PWM
738 * --------------------------------------------------------------------*/
739
740 #if defined(CONFIG_ATMEL_PWM)
741 static u32 pwm_mask;
742
743 static struct resource pwm_resources[] = {
744 [0] = {
745 .start = AT91SAM9RL_BASE_PWMC,
746 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
747 .flags = IORESOURCE_MEM,
748 },
749 [1] = {
750 .start = AT91SAM9RL_ID_PWMC,
751 .end = AT91SAM9RL_ID_PWMC,
752 .flags = IORESOURCE_IRQ,
753 },
754 };
755
756 static struct platform_device at91sam9rl_pwm0_device = {
757 .name = "atmel_pwm",
758 .id = -1,
759 .dev = {
760 .platform_data = &pwm_mask,
761 },
762 .resource = pwm_resources,
763 .num_resources = ARRAY_SIZE(pwm_resources),
764 };
765
766 void __init at91_add_device_pwm(u32 mask)
767 {
768 if (mask & (1 << AT91_PWM0))
769 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
770
771 if (mask & (1 << AT91_PWM1))
772 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
773
774 if (mask & (1 << AT91_PWM2))
775 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
776
777 if (mask & (1 << AT91_PWM3))
778 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
779
780 pwm_mask = mask;
781
782 platform_device_register(&at91sam9rl_pwm0_device);
783 }
784 #else
785 void __init at91_add_device_pwm(u32 mask) {}
786 #endif
787
788
789 /* --------------------------------------------------------------------
790 * SSC -- Synchronous Serial Controller
791 * -------------------------------------------------------------------- */
792
793 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
794 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
795
796 static struct resource ssc0_resources[] = {
797 [0] = {
798 .start = AT91SAM9RL_BASE_SSC0,
799 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
800 .flags = IORESOURCE_MEM,
801 },
802 [1] = {
803 .start = AT91SAM9RL_ID_SSC0,
804 .end = AT91SAM9RL_ID_SSC0,
805 .flags = IORESOURCE_IRQ,
806 },
807 };
808
809 static struct platform_device at91sam9rl_ssc0_device = {
810 .name = "ssc",
811 .id = 0,
812 .dev = {
813 .dma_mask = &ssc0_dmamask,
814 .coherent_dma_mask = DMA_BIT_MASK(32),
815 },
816 .resource = ssc0_resources,
817 .num_resources = ARRAY_SIZE(ssc0_resources),
818 };
819
820 static inline void configure_ssc0_pins(unsigned pins)
821 {
822 if (pins & ATMEL_SSC_TF)
823 at91_set_A_periph(AT91_PIN_PC0, 1);
824 if (pins & ATMEL_SSC_TK)
825 at91_set_A_periph(AT91_PIN_PC1, 1);
826 if (pins & ATMEL_SSC_TD)
827 at91_set_A_periph(AT91_PIN_PA15, 1);
828 if (pins & ATMEL_SSC_RD)
829 at91_set_A_periph(AT91_PIN_PA16, 1);
830 if (pins & ATMEL_SSC_RK)
831 at91_set_B_periph(AT91_PIN_PA10, 1);
832 if (pins & ATMEL_SSC_RF)
833 at91_set_B_periph(AT91_PIN_PA22, 1);
834 }
835
836 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
837
838 static struct resource ssc1_resources[] = {
839 [0] = {
840 .start = AT91SAM9RL_BASE_SSC1,
841 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
842 .flags = IORESOURCE_MEM,
843 },
844 [1] = {
845 .start = AT91SAM9RL_ID_SSC1,
846 .end = AT91SAM9RL_ID_SSC1,
847 .flags = IORESOURCE_IRQ,
848 },
849 };
850
851 static struct platform_device at91sam9rl_ssc1_device = {
852 .name = "ssc",
853 .id = 1,
854 .dev = {
855 .dma_mask = &ssc1_dmamask,
856 .coherent_dma_mask = DMA_BIT_MASK(32),
857 },
858 .resource = ssc1_resources,
859 .num_resources = ARRAY_SIZE(ssc1_resources),
860 };
861
862 static inline void configure_ssc1_pins(unsigned pins)
863 {
864 if (pins & ATMEL_SSC_TF)
865 at91_set_B_periph(AT91_PIN_PA29, 1);
866 if (pins & ATMEL_SSC_TK)
867 at91_set_B_periph(AT91_PIN_PA30, 1);
868 if (pins & ATMEL_SSC_TD)
869 at91_set_B_periph(AT91_PIN_PA13, 1);
870 if (pins & ATMEL_SSC_RD)
871 at91_set_B_periph(AT91_PIN_PA14, 1);
872 if (pins & ATMEL_SSC_RK)
873 at91_set_B_periph(AT91_PIN_PA9, 1);
874 if (pins & ATMEL_SSC_RF)
875 at91_set_B_periph(AT91_PIN_PA8, 1);
876 }
877
878 /*
879 * SSC controllers are accessed through library code, instead of any
880 * kind of all-singing/all-dancing driver. For example one could be
881 * used by a particular I2S audio codec's driver, while another one
882 * on the same system might be used by a custom data capture driver.
883 */
884 void __init at91_add_device_ssc(unsigned id, unsigned pins)
885 {
886 struct platform_device *pdev;
887
888 /*
889 * NOTE: caller is responsible for passing information matching
890 * "pins" to whatever will be using each particular controller.
891 */
892 switch (id) {
893 case AT91SAM9RL_ID_SSC0:
894 pdev = &at91sam9rl_ssc0_device;
895 configure_ssc0_pins(pins);
896 break;
897 case AT91SAM9RL_ID_SSC1:
898 pdev = &at91sam9rl_ssc1_device;
899 configure_ssc1_pins(pins);
900 break;
901 default:
902 return;
903 }
904
905 platform_device_register(pdev);
906 }
907
908 #else
909 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
910 #endif
911
912
913 /* --------------------------------------------------------------------
914 * UART
915 * -------------------------------------------------------------------- */
916
917 #if defined(CONFIG_SERIAL_ATMEL)
918 static struct resource dbgu_resources[] = {
919 [0] = {
920 .start = AT91SAM9RL_BASE_DBGU,
921 .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
922 .flags = IORESOURCE_MEM,
923 },
924 [1] = {
925 .start = AT91_ID_SYS,
926 .end = AT91_ID_SYS,
927 .flags = IORESOURCE_IRQ,
928 },
929 };
930
931 static struct atmel_uart_data dbgu_data = {
932 .use_dma_tx = 0,
933 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
934 };
935
936 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
937
938 static struct platform_device at91sam9rl_dbgu_device = {
939 .name = "atmel_usart",
940 .id = 0,
941 .dev = {
942 .dma_mask = &dbgu_dmamask,
943 .coherent_dma_mask = DMA_BIT_MASK(32),
944 .platform_data = &dbgu_data,
945 },
946 .resource = dbgu_resources,
947 .num_resources = ARRAY_SIZE(dbgu_resources),
948 };
949
950 static inline void configure_dbgu_pins(void)
951 {
952 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
953 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
954 }
955
956 static struct resource uart0_resources[] = {
957 [0] = {
958 .start = AT91SAM9RL_BASE_US0,
959 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
960 .flags = IORESOURCE_MEM,
961 },
962 [1] = {
963 .start = AT91SAM9RL_ID_US0,
964 .end = AT91SAM9RL_ID_US0,
965 .flags = IORESOURCE_IRQ,
966 },
967 };
968
969 static struct atmel_uart_data uart0_data = {
970 .use_dma_tx = 1,
971 .use_dma_rx = 1,
972 };
973
974 static u64 uart0_dmamask = DMA_BIT_MASK(32);
975
976 static struct platform_device at91sam9rl_uart0_device = {
977 .name = "atmel_usart",
978 .id = 1,
979 .dev = {
980 .dma_mask = &uart0_dmamask,
981 .coherent_dma_mask = DMA_BIT_MASK(32),
982 .platform_data = &uart0_data,
983 },
984 .resource = uart0_resources,
985 .num_resources = ARRAY_SIZE(uart0_resources),
986 };
987
988 static inline void configure_usart0_pins(unsigned pins)
989 {
990 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
991 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
992
993 if (pins & ATMEL_UART_RTS)
994 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
995 if (pins & ATMEL_UART_CTS)
996 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
997 if (pins & ATMEL_UART_DSR)
998 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
999 if (pins & ATMEL_UART_DTR)
1000 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
1001 if (pins & ATMEL_UART_DCD)
1002 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
1003 if (pins & ATMEL_UART_RI)
1004 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
1005 }
1006
1007 static struct resource uart1_resources[] = {
1008 [0] = {
1009 .start = AT91SAM9RL_BASE_US1,
1010 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1011 .flags = IORESOURCE_MEM,
1012 },
1013 [1] = {
1014 .start = AT91SAM9RL_ID_US1,
1015 .end = AT91SAM9RL_ID_US1,
1016 .flags = IORESOURCE_IRQ,
1017 },
1018 };
1019
1020 static struct atmel_uart_data uart1_data = {
1021 .use_dma_tx = 1,
1022 .use_dma_rx = 1,
1023 };
1024
1025 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1026
1027 static struct platform_device at91sam9rl_uart1_device = {
1028 .name = "atmel_usart",
1029 .id = 2,
1030 .dev = {
1031 .dma_mask = &uart1_dmamask,
1032 .coherent_dma_mask = DMA_BIT_MASK(32),
1033 .platform_data = &uart1_data,
1034 },
1035 .resource = uart1_resources,
1036 .num_resources = ARRAY_SIZE(uart1_resources),
1037 };
1038
1039 static inline void configure_usart1_pins(unsigned pins)
1040 {
1041 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
1042 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
1043
1044 if (pins & ATMEL_UART_RTS)
1045 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
1046 if (pins & ATMEL_UART_CTS)
1047 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
1048 }
1049
1050 static struct resource uart2_resources[] = {
1051 [0] = {
1052 .start = AT91SAM9RL_BASE_US2,
1053 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
1054 .flags = IORESOURCE_MEM,
1055 },
1056 [1] = {
1057 .start = AT91SAM9RL_ID_US2,
1058 .end = AT91SAM9RL_ID_US2,
1059 .flags = IORESOURCE_IRQ,
1060 },
1061 };
1062
1063 static struct atmel_uart_data uart2_data = {
1064 .use_dma_tx = 1,
1065 .use_dma_rx = 1,
1066 };
1067
1068 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1069
1070 static struct platform_device at91sam9rl_uart2_device = {
1071 .name = "atmel_usart",
1072 .id = 3,
1073 .dev = {
1074 .dma_mask = &uart2_dmamask,
1075 .coherent_dma_mask = DMA_BIT_MASK(32),
1076 .platform_data = &uart2_data,
1077 },
1078 .resource = uart2_resources,
1079 .num_resources = ARRAY_SIZE(uart2_resources),
1080 };
1081
1082 static inline void configure_usart2_pins(unsigned pins)
1083 {
1084 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1085 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
1086
1087 if (pins & ATMEL_UART_RTS)
1088 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1089 if (pins & ATMEL_UART_CTS)
1090 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
1091 }
1092
1093 static struct resource uart3_resources[] = {
1094 [0] = {
1095 .start = AT91SAM9RL_BASE_US3,
1096 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1097 .flags = IORESOURCE_MEM,
1098 },
1099 [1] = {
1100 .start = AT91SAM9RL_ID_US3,
1101 .end = AT91SAM9RL_ID_US3,
1102 .flags = IORESOURCE_IRQ,
1103 },
1104 };
1105
1106 static struct atmel_uart_data uart3_data = {
1107 .use_dma_tx = 1,
1108 .use_dma_rx = 1,
1109 };
1110
1111 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1112
1113 static struct platform_device at91sam9rl_uart3_device = {
1114 .name = "atmel_usart",
1115 .id = 4,
1116 .dev = {
1117 .dma_mask = &uart3_dmamask,
1118 .coherent_dma_mask = DMA_BIT_MASK(32),
1119 .platform_data = &uart3_data,
1120 },
1121 .resource = uart3_resources,
1122 .num_resources = ARRAY_SIZE(uart3_resources),
1123 };
1124
1125 static inline void configure_usart3_pins(unsigned pins)
1126 {
1127 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1128 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
1129
1130 if (pins & ATMEL_UART_RTS)
1131 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1132 if (pins & ATMEL_UART_CTS)
1133 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1134 }
1135
1136 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1137 struct platform_device *atmel_default_console_device; /* the serial console device */
1138
1139 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1140 {
1141 struct platform_device *pdev;
1142 struct atmel_uart_data *pdata;
1143
1144 switch (id) {
1145 case 0: /* DBGU */
1146 pdev = &at91sam9rl_dbgu_device;
1147 configure_dbgu_pins();
1148 break;
1149 case AT91SAM9RL_ID_US0:
1150 pdev = &at91sam9rl_uart0_device;
1151 configure_usart0_pins(pins);
1152 break;
1153 case AT91SAM9RL_ID_US1:
1154 pdev = &at91sam9rl_uart1_device;
1155 configure_usart1_pins(pins);
1156 break;
1157 case AT91SAM9RL_ID_US2:
1158 pdev = &at91sam9rl_uart2_device;
1159 configure_usart2_pins(pins);
1160 break;
1161 case AT91SAM9RL_ID_US3:
1162 pdev = &at91sam9rl_uart3_device;
1163 configure_usart3_pins(pins);
1164 break;
1165 default:
1166 return;
1167 }
1168 pdata = pdev->dev.platform_data;
1169 pdata->num = portnr; /* update to mapped ID */
1170
1171 if (portnr < ATMEL_MAX_UART)
1172 at91_uarts[portnr] = pdev;
1173 }
1174
1175 void __init at91_set_serial_console(unsigned portnr)
1176 {
1177 if (portnr < ATMEL_MAX_UART) {
1178 atmel_default_console_device = at91_uarts[portnr];
1179 at91sam9rl_set_console_clock(at91_uarts[portnr]->id);
1180 }
1181 }
1182
1183 void __init at91_add_device_serial(void)
1184 {
1185 int i;
1186
1187 for (i = 0; i < ATMEL_MAX_UART; i++) {
1188 if (at91_uarts[i])
1189 platform_device_register(at91_uarts[i]);
1190 }
1191
1192 if (!atmel_default_console_device)
1193 printk(KERN_INFO "AT91: No default serial console defined.\n");
1194 }
1195 #else
1196 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1197 void __init at91_set_serial_console(unsigned portnr) {}
1198 void __init at91_add_device_serial(void) {}
1199 #endif
1200
1201
1202 /* -------------------------------------------------------------------- */
1203
1204 /*
1205 * These devices are always present and don't need any board-specific
1206 * setup.
1207 */
1208 static int __init at91_add_standard_devices(void)
1209 {
1210 at91_add_device_hdmac();
1211 at91_add_device_rtc();
1212 at91_add_device_rtt();
1213 at91_add_device_watchdog();
1214 at91_add_device_tc();
1215 return 0;
1216 }
1217
1218 arch_initcall(at91_add_standard_devices);