arch/arm/mach-bcmring/core.c

   1 /*
   2  *  derived from linux/arch/arm/mach-versatile/core.c
   3  *  linux/arch/arm/mach-bcmring/core.c
   4  *
   5  *  Copyright (C) 1999 - 2003 ARM Limited
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 /* Portions copyright Broadcom 2008 */
  23
  24 #include <linux/init.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/amba/bus.h>
  30 #include <linux/clkdev.h>
  31
  32 #include <mach/csp/mm_addr.h>
  33 #include <mach/hardware.h>
  34 #include <linux/io.h>
  35 #include <asm/irq.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/timer-sp.h>
  38 #include <asm/mach-types.h>
  39
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/flash.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/time.h>
  44 #include <asm/mach/map.h>
  45
  46 #include <cfg_global.h>
  47
  48 #include "clock.h"
  49
  50 #include <csp/secHw.h>
  51 #include <mach/csp/secHw_def.h>
  52 #include <mach/csp/chipcHw_inline.h>
  53 #include <mach/csp/tmrHw_reg.h>
  54
  55 #define AMBA_DEVICE(name, initname, base, plat, size)       \
  56 static struct amba_device name##_device = {     \
  57    .dev = {                                     \
  58       .coherent_dma_mask = ~0,                  \
  59       .init_name = initname,                    \
  60       .platform_data = plat                     \
  61    },                                           \
  62    .res = {                                     \
  63       .start = MM_ADDR_IO_##base,               \
  64                 .end = MM_ADDR_IO_##base + (size) - 1,    \
  65       .flags = IORESOURCE_MEM                   \
  66    },                                           \
  67    .dma_mask = ~0,                              \
  68    .irq = {                                     \
  69       IRQ_##base                                \
  70    }                                            \
  71 }
  72
  73
  74 AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
  75 AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
  76
  77 static struct clk pll1_clk = {
  78         .name = "PLL1",
  79         .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
  80         .rate_hz = 2000000000,
  81         .use_cnt = 7,
  82 };
  83
  84 static struct clk uart_clk = {
  85         .name = "UART",
  86         .type = CLK_TYPE_PROGRAMMABLE,
  87         .csp_id = chipcHw_CLOCK_UART,
  88         .rate_hz = HW_CFG_UART_CLK_HZ,
  89         .parent = &pll1_clk,
  90 };
  91
  92 static struct clk dummy_apb_pclk = {
  93         .name = "BUSCLK",
  94         .type = CLK_TYPE_PRIMARY,
  95         .mode = CLK_MODE_XTAL,
  96 };
  97
  98 /* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
  99 #if defined(CONFIG_ARCH_FPGA11107)
 100 /* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
 101 /* slow down Linux's sense of time */
 102 #define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 103 #define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 104 #define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
 105 #define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
 106 #else
 107 #define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 108 #define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 109 #define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
 110 #define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
 111 #endif
 112
 113 static struct clk sp804_timer012_clk = {
 114         .name = "sp804-timer-0,1,2",
 115         .type = CLK_TYPE_PRIMARY,
 116         .mode = CLK_MODE_XTAL,
 117         .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
 118 };
 119
 120 static struct clk sp804_timer3_clk = {
 121         .name = "sp804-timer-3",
 122         .type = CLK_TYPE_PRIMARY,
 123         .mode = CLK_MODE_XTAL,
 124         .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
 125 };
 126
 127 static struct clk_lookup lookups[] = {
 128         {                       /* Bus clock */
 129                 .con_id = "apb_pclk",
 130                 .clk = &dummy_apb_pclk,
 131         }, {                    /* UART0 */
 132                 .dev_id = "uarta",
 133                 .clk = &uart_clk,
 134         }, {                    /* UART1 */
 135                 .dev_id = "uartb",
 136                 .clk = &uart_clk,
 137         }, {                    /* SP804 timer 0 */
 138                 .dev_id = "sp804",
 139                 .con_id = "timer0",
 140                 .clk = &sp804_timer012_clk,
 141         }, {                    /* SP804 timer 1 */
 142                 .dev_id = "sp804",
 143                 .con_id = "timer1",
 144                 .clk = &sp804_timer012_clk,
 145         }, {                    /* SP804 timer 3 */
 146                 .dev_id = "sp804",
 147                 .con_id = "timer3",
 148                 .clk = &sp804_timer3_clk,
 149         }
 150 };
 151
 152 static struct amba_device *amba_devs[] __initdata = {
 153         &uartA_device,
 154         &uartB_device,
 155 };
 156
 157 void __init bcmring_amba_init(void)
 158 {
 159         int i;
 160         u32 bus_clock;
 161
 162 /* Linux is run initially in non-secure mode. Secure peripherals */
 163 /* generate FIQ, and must be handled in secure mode. Until we have */
 164 /* a linux security monitor implementation, keep everything in */
 165 /* non-secure mode. */
 166         chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
 167         secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
 168                           secHw_BLK_MASK_KEY_SCAN |
 169                           secHw_BLK_MASK_TOUCH_SCREEN |
 170                           secHw_BLK_MASK_UART0 |
 171                           secHw_BLK_MASK_UART1 |
 172                           secHw_BLK_MASK_WATCHDOG |
 173                           secHw_BLK_MASK_SPUM |
 174                           secHw_BLK_MASK_DDR2 |
 175                           secHw_BLK_MASK_SPU |
 176                           secHw_BLK_MASK_PKA |
 177                           secHw_BLK_MASK_RNG |
 178                           secHw_BLK_MASK_RTC |
 179                           secHw_BLK_MASK_OTP |
 180                           secHw_BLK_MASK_BOOT |
 181                           secHw_BLK_MASK_MPU |
 182                           secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
 183
 184         /* Only the devices attached to the AMBA bus are enabled just before the bus is */
 185         /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
 186         /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
 187         /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
 188         bus_clock = chipcHw_REG_BUS_CLOCK_GE
 189             | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
 190
 191         chipcHw_busInterfaceClockEnable(bus_clock);
 192
 193         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 194                 struct amba_device *d = amba_devs[i];
 195                 amba_device_register(d, &iomem_resource);
 196         }
 197 }
 198
 199 /*
 200  * Where is the timer (VA)?
 201  */
 202 #define TIMER0_VA_BASE          ((void __iomem *)MM_IO_BASE_TMR)
 203 #define TIMER1_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
 204 #define TIMER2_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
 205 #define TIMER3_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
 206
 207 static int __init bcmring_clocksource_init(void)
 208 {
 209         /* setup timer1 as free-running clocksource */
 210         sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
 211
 212         /* setup timer3 as free-running clocksource */
 213         sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
 214
 215         return 0;
 216 }
 217
 218 /*
 219  * Set up timer interrupt, and return the current time in seconds.
 220  */
 221 void __init bcmring_init_timer(void)
 222 {
 223         printk(KERN_INFO "bcmring_init_timer\n");
 224         /*
 225          * Initialise to a known state (all timers off)
 226          */
 227         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 228         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 229         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 230         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 231
 232         /*
 233          * Make irqs happen for the system timer
 234          */
 235         bcmring_clocksource_init();
 236
 237         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
 238 }
 239
 240 struct sys_timer bcmring_timer = {
 241         .init = bcmring_init_timer,
 242 };
 243
 244 void __init bcmring_init_early(void)
 245 {
 246         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 247 }