drivers/gpu/drm/nouveau/nv50_evo.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_dma.h"
  29 #include "nouveau_ramht.h"
  30 #include "nv50_display.h"
  31
  32 static void
  33 nv50_evo_channel_del(struct nouveau_channel **pevo)
  34 {
  35         struct nouveau_channel *evo = *pevo;
  36
  37         if (!evo)
  38                 return;
  39         *pevo = NULL;
  40
  41         nouveau_gpuobj_channel_takedown(evo);
  42         nouveau_bo_unmap(evo->pushbuf_bo);
  43         nouveau_bo_ref(NULL, &evo->pushbuf_bo);
  44
  45         if (evo->user)
  46                 iounmap(evo->user);
  47
  48         kfree(evo);
  49 }
  50
  51 void
  52 nv50_evo_dmaobj_init(struct nouveau_gpuobj *obj, u32 memtype, u64 base, u64 size)
  53 {
  54         struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
  55         u32 flags5;
  56
  57         if (dev_priv->chipset < 0xc0) {
  58                 /* not supported on 0x50, specified in format mthd */
  59                 if (dev_priv->chipset == 0x50)
  60                         memtype = 0;
  61                 flags5 = 0x00010000;
  62         } else {
  63                 if (memtype & 0x80000000)
  64                         flags5 = 0x00000000; /* large pages */
  65                 else
  66                         flags5 = 0x00020000;
  67         }
  68
  69         nv50_gpuobj_dma_init(obj, 0, 0x3d, base, size, NV_MEM_TARGET_VRAM,
  70                              NV_MEM_ACCESS_RW, (memtype >> 8) & 0xff, 0);
  71         nv_wo32(obj, 0x14, flags5);
  72         dev_priv->engine.instmem.flush(obj->dev);
  73 }
  74
  75 int
  76 nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype,
  77                     u64 base, u64 size, struct nouveau_gpuobj **pobj)
  78 {
  79         struct nv50_display *disp = nv50_display(evo->dev);
  80         struct nouveau_gpuobj *obj = NULL;
  81         int ret;
  82
  83         ret = nouveau_gpuobj_new(evo->dev, disp->master, 6*4, 32, 0, &obj);
  84         if (ret)
  85                 return ret;
  86         obj->engine = NVOBJ_ENGINE_DISPLAY;
  87
  88         nv50_evo_dmaobj_init(obj, memtype, base, size);
  89
  90         ret = nouveau_ramht_insert(evo, handle, obj);
  91         if (ret)
  92                 goto out;
  93
  94         if (pobj)
  95                 nouveau_gpuobj_ref(obj, pobj);
  96 out:
  97         nouveau_gpuobj_ref(NULL, &obj);
  98         return ret;
  99 }
 100
 101 static int
 102 nv50_evo_channel_new(struct drm_device *dev, int chid,
 103                      struct nouveau_channel **pevo)
 104 {
 105         struct nv50_display *disp = nv50_display(dev);
 106         struct nouveau_channel *evo;
 107         int ret;
 108
 109         evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
 110         if (!evo)
 111                 return -ENOMEM;
 112         *pevo = evo;
 113
 114         evo->id = chid;
 115         evo->dev = dev;
 116         evo->user_get = 4;
 117         evo->user_put = 0;
 118
 119         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
 120                              &evo->pushbuf_bo);
 121         if (ret == 0)
 122                 ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
 123         if (ret) {
 124                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
 125                 nv50_evo_channel_del(pevo);
 126                 return ret;
 127         }
 128
 129         ret = nouveau_bo_map(evo->pushbuf_bo);
 130         if (ret) {
 131                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
 132                 nv50_evo_channel_del(pevo);
 133                 return ret;
 134         }
 135
 136         evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
 137                             NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
 138         if (!evo->user) {
 139                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
 140                 nv50_evo_channel_del(pevo);
 141                 return -ENOMEM;
 142         }
 143
 144         /* bind primary evo channel's ramht to the channel */
 145         if (disp->master && evo != disp->master)
 146                 nouveau_ramht_ref(disp->master->ramht, &evo->ramht, NULL);
 147
 148         return 0;
 149 }
 150
 151 static int
 152 nv50_evo_channel_init(struct nouveau_channel *evo)
 153 {
 154         struct drm_device *dev = evo->dev;
 155         int id = evo->id, ret, i;
 156         u64 pushbuf = evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT;
 157         u32 tmp;
 158
 159         tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
 160         if ((tmp & 0x009f0000) == 0x00020000)
 161                 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);
 162
 163         tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
 164         if ((tmp & 0x003f0000) == 0x00030000)
 165                 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);
 166
 167         /* initialise fifo */
 168         nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
 169                      NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
 170                      NV50_PDISPLAY_EVO_DMA_CB_VALID);
 171         nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
 172         nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
 173         nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
 174                      NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
 175
 176         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
 177         nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
 178                      NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
 179         if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
 180                 NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id,
 181                          nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
 182                 return -EBUSY;
 183         }
 184
 185         /* enable error reporting on the channel */
 186         nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
 187
 188         evo->dma.max = (4096/4) - 2;
 189         evo->dma.max &= ~7;
 190         evo->dma.put = 0;
 191         evo->dma.cur = evo->dma.put;
 192         evo->dma.free = evo->dma.max - evo->dma.cur;
 193
 194         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
 195         if (ret)
 196                 return ret;
 197
 198         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 199                 OUT_RING(evo, 0);
 200
 201         return 0;
 202 }
 203
 204 static void
 205 nv50_evo_channel_fini(struct nouveau_channel *evo)
 206 {
 207         struct drm_device *dev = evo->dev;
 208         int id = evo->id;
 209
 210         nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
 211         nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
 212         nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id));
 213         nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
 214         if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
 215                 NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id,
 216                          nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
 217         }
 218 }
 219
 220 static void
 221 nv50_evo_destroy(struct drm_device *dev)
 222 {
 223         struct nv50_display *disp = nv50_display(dev);
 224         int i;
 225
 226         for (i = 0; i < 2; i++) {
 227                 if (disp->crtc[i].sem.bo) {
 228                         nouveau_bo_unmap(disp->crtc[i].sem.bo);
 229                         nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo);
 230                 }
 231                 nv50_evo_channel_del(&disp->crtc[i].sync);
 232         }
 233         nouveau_gpuobj_ref(NULL, &disp->ntfy);
 234         nv50_evo_channel_del(&disp->master);
 235 }
 236
 237 static int
 238 nv50_evo_create(struct drm_device *dev)
 239 {
 240         struct drm_nouveau_private *dev_priv = dev->dev_private;
 241         struct nv50_display *disp = nv50_display(dev);
 242         struct nouveau_gpuobj *ramht = NULL;
 243         struct nouveau_channel *evo;
 244         int ret, i, j;
 245
 246         /* create primary evo channel, the one we use for modesetting
 247          * purporses
 248          */
 249         ret = nv50_evo_channel_new(dev, 0, &disp->master);
 250         if (ret)
 251                 return ret;
 252         evo = disp->master;
 253
 254         /* setup object management on it, any other evo channel will
 255          * use this also as there's no per-channel support on the
 256          * hardware
 257          */
 258         ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536,
 259                                  NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
 260         if (ret) {
 261                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
 262                 goto err;
 263         }
 264
 265         ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
 266         if (ret) {
 267                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
 268                 goto err;
 269         }
 270
 271         ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
 272         if (ret) {
 273                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
 274                 goto err;
 275         }
 276
 277         ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
 278         nouveau_gpuobj_ref(NULL, &ramht);
 279         if (ret)
 280                 goto err;
 281
 282         /* not sure exactly what this is..
 283          *
 284          * the first dword of the structure is used by nvidia to wait on
 285          * full completion of an EVO "update" command.
 286          *
 287          * method 0x8c on the master evo channel will fill a lot more of
 288          * this structure with some undefined info
 289          */
 290         ret = nouveau_gpuobj_new(dev, disp->master, 0x1000, 0,
 291                                  NVOBJ_FLAG_ZERO_ALLOC, &disp->ntfy);
 292         if (ret)
 293                 goto err;
 294
 295         ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000,
 296                                   disp->ntfy->vinst, disp->ntfy->size, NULL);
 297         if (ret)
 298                 goto err;
 299
 300         /* create some default objects for the scanout memtypes we support */
 301         ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000,
 302                                   0, dev_priv->vram_size, NULL);
 303         if (ret)
 304                 goto err;
 305
 306         ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000,
 307                                   0, dev_priv->vram_size, NULL);
 308         if (ret)
 309                 goto err;
 310
 311         ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 |
 312                                   (dev_priv->chipset < 0xc0 ? 0x7a00 : 0xfe00),
 313                                   0, dev_priv->vram_size, NULL);
 314         if (ret)
 315                 goto err;
 316
 317         ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 |
 318                                   (dev_priv->chipset < 0xc0 ? 0x7000 : 0xfe00),
 319                                   0, dev_priv->vram_size, NULL);
 320         if (ret)
 321                 goto err;
 322
 323         /* create "display sync" channels and other structures we need
 324          * to implement page flipping
 325          */
 326         for (i = 0; i < 2; i++) {
 327                 struct nv50_display_crtc *dispc = &disp->crtc[i];
 328                 u64 offset;
 329
 330                 ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync);
 331                 if (ret)
 332                         goto err;
 333
 334                 ret = nouveau_bo_new(dev, NULL, 4096, 0x1000, TTM_PL_FLAG_VRAM,
 335                                      0, 0x0000, &dispc->sem.bo);
 336                 if (!ret) {
 337                         offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT;
 338
 339                         ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM);
 340                         if (!ret)
 341                                 ret = nouveau_bo_map(dispc->sem.bo);
 342                         if (ret)
 343                                 nouveau_bo_ref(NULL, &dispc->sem.bo);
 344                 }
 345
 346                 if (ret)
 347                         goto err;
 348
 349                 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000,
 350                                           offset, 4096, NULL);
 351                 if (ret)
 352                         goto err;
 353
 354                 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
 355                                           0, dev_priv->vram_size, NULL);
 356                 if (ret)
 357                         goto err;
 358
 359                 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 |
 360                                           (dev_priv->chipset < 0xc0 ?
 361                                           0x7a00 : 0xfe00),
 362                                           0, dev_priv->vram_size, NULL);
 363                 if (ret)
 364                         goto err;
 365
 366                 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 |
 367                                           (dev_priv->chipset < 0xc0 ?
 368                                           0x7000 : 0xfe00),
 369                                           0, dev_priv->vram_size, NULL);
 370                 if (ret)
 371                         goto err;
 372
 373                 for (j = 0; j < 4096; j += 4)
 374                         nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000);
 375                 dispc->sem.offset = 0;
 376         }
 377
 378         return 0;
 379
 380 err:
 381         nv50_evo_destroy(dev);
 382         return ret;
 383 }
 384
 385 int
 386 nv50_evo_init(struct drm_device *dev)
 387 {
 388         struct nv50_display *disp = nv50_display(dev);
 389         int ret, i;
 390
 391         if (!disp->master) {
 392                 ret = nv50_evo_create(dev);
 393                 if (ret)
 394                         return ret;
 395         }
 396
 397         ret = nv50_evo_channel_init(disp->master);
 398         if (ret)
 399                 return ret;
 400
 401         for (i = 0; i < 2; i++) {
 402                 ret = nv50_evo_channel_init(disp->crtc[i].sync);
 403                 if (ret)
 404                         return ret;
 405         }
 406
 407         return 0;
 408 }
 409
 410 void
 411 nv50_evo_fini(struct drm_device *dev)
 412 {
 413         struct nv50_display *disp = nv50_display(dev);
 414         int i;
 415
 416         for (i = 0; i < 2; i++) {
 417                 if (disp->crtc[i].sync)
 418                         nv50_evo_channel_fini(disp->crtc[i].sync);
 419         }
 420
 421         if (disp->master)
 422                 nv50_evo_channel_fini(disp->master);
 423
 424         nv50_evo_destroy(dev);
 425 }