2 * Copyright (C) ST-Ericsson SA 2011
4 * License terms: GNU General Public License (GPL) version 2
8 #include <asm/cacheflush.h>
9 #include <asm/hardware/cache-l2x0.h>
10 #include <mach/hardware.h>
13 static void __iomem
*l2x0_base
;
15 static int __init
ux500_l2x0_unlock(void)
20 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
21 * apparently locks both caches before jumping to the kernel. The
22 * l2x0 core will not touch the unlock registers if the l2x0 is
23 * already enabled, so we do it right here instead. The PL310 has
24 * 8 sets of registers, one per possible CPU.
26 for (i
= 0; i
< 8; i
++) {
27 writel_relaxed(0x0, l2x0_base
+ L2X0_LOCKDOWN_WAY_D_BASE
+
28 i
* L2X0_LOCKDOWN_STRIDE
);
29 writel_relaxed(0x0, l2x0_base
+ L2X0_LOCKDOWN_WAY_I_BASE
+
30 i
* L2X0_LOCKDOWN_STRIDE
);
35 static int __init
ux500_l2x0_init(void)
38 l2x0_base
= __io_address(U5500_L2CC_BASE
);
39 else if (cpu_is_u8500())
40 l2x0_base
= __io_address(U8500_L2CC_BASE
);
44 /* Unlock before init */
47 /* 64KB way size, 8 way associativity, force WA */
48 l2x0_init(l2x0_base
, 0x3e060000, 0xc0000fff);
51 * We can't disable l2 as we are in non secure mode, currently
52 * this seems be called only during kexec path. So let's
53 * override outer.disable with nasty assignment until we have
54 * some SMI service available.
56 outer_cache
.disable
= NULL
;
61 early_initcall(ux500_l2x0_init
);