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mtip32xx: fix error handling in mtip_init()
[zen-stable.git] / sound / soc / codecs / wm8994.c
blobe5cc616d2c7984134b4d1cf70d88d2c275e74c67
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
48
49 static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53 };
54
55 static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59 };
60
61 static void wm8958_default_micdet(u16 status, void *data);
62
63 static const struct wm8958_micd_rate micdet_rates[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
68 };
69
70 static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75 };
76
77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78 {
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
82 const struct wm8958_micd_rate *rates;
83 int num_rates;
84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
107 best = 0;
108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
110 continue;
111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
113 best = i;
114 else if (rates[best].idle != idle)
115 best = i;
116 }
117
118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124 }
125
126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127 {
128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
169
170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177 }
178
179 static int configure_clock(struct snd_soc_codec *codec)
180 {
181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
182 int change, new;
183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
197 return 0;
198 }
199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
209
210 wm8958_micd_set_rate(codec);
211
212 return 0;
213 }
214
215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217 {
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228 }
229
230 static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232 };
233
234 static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
237 static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239 };
240
241 static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244 static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247 static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
257
258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266 {
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286 }
287
288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289 {
290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308 }
309
310 /* Icky as hell but saves code duplication */
311 static int wm8994_get_drc(const char *name)
312 {
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320 }
321
322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324 {
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342 }
343
344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346 {
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354 }
355
356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357 {
358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411 }
412
413 /* Icky as hell but saves code duplication */
414 static int wm8994_get_retune_mobile_block(const char *name)
415 {
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423 }
424
425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427 {
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445 }
446
447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449 {
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457 }
458
459 static const char *aif_chan_src_text[] = {
460 "Left", "Right"
461 };
462
463 static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466 static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469 static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472 static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
475 static const struct soc_enum aif1dacl_src =
476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
477
478 static const struct soc_enum aif1dacr_src =
479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
480
481 static const struct soc_enum aif2dacl_src =
482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
483
484 static const struct soc_enum aif2dacr_src =
485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
486
487 static const char *osr_text[] = {
488 "Low Power", "High Performance",
489 };
490
491 static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494 static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
512
513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
517
518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
564 SOC_ENUM("ADC OSR", adc_osr),
565 SOC_ENUM("DAC OSR", dac_osr),
566
567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
590 8, 1, 0),
591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
596 10, 15, 0, wm8994_3d_tlv),
597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
598 8, 1, 0),
599 };
600
601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634 };
635
636 static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638 };
639
640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648 static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
654
655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
675 };
676
677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682 };
683
684 /* We run all mode setting through a function to enforce audio mode */
685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686 {
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689 if (wm8994->active_refcount)
690 mode = WM1811_JACKDET_MODE_AUDIO;
691
692 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
693 WM1811_JACKDET_MODE_MASK, mode);
694
695 if (mode == WM1811_JACKDET_MODE_MIC)
696 msleep(2);
697 }
698
699 static void active_reference(struct snd_soc_codec *codec)
700 {
701 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
702
703 mutex_lock(&wm8994->accdet_lock);
704
705 wm8994->active_refcount++;
706
707 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
708 wm8994->active_refcount);
709
710 if (wm8994->active_refcount == 1) {
711 /* If we're using jack detection go into audio mode */
712 if (wm8994->jackdet && wm8994->jack_cb) {
713 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
714 WM1811_JACKDET_MODE_MASK,
715 WM1811_JACKDET_MODE_AUDIO);
716 msleep(2);
717 }
718 }
719
720 mutex_unlock(&wm8994->accdet_lock);
721 }
722
723 static void active_dereference(struct snd_soc_codec *codec)
724 {
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726 u16 mode;
727
728 mutex_lock(&wm8994->accdet_lock);
729
730 wm8994->active_refcount--;
731
732 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
733 wm8994->active_refcount);
734
735 if (wm8994->active_refcount == 0) {
736 /* Go into appropriate detection only mode */
737 if (wm8994->jackdet && wm8994->jack_cb) {
738 if (wm8994->jack_mic || wm8994->mic_detecting)
739 mode = WM1811_JACKDET_MODE_MIC;
740 else
741 mode = WM1811_JACKDET_MODE_JACK;
742
743 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
744 WM1811_JACKDET_MODE_MASK,
745 mode);
746 }
747 }
748
749 mutex_unlock(&wm8994->accdet_lock);
750 }
751
752 static int clk_sys_event(struct snd_soc_dapm_widget *w,
753 struct snd_kcontrol *kcontrol, int event)
754 {
755 struct snd_soc_codec *codec = w->codec;
756
757 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU:
759 return configure_clock(codec);
760
761 case SND_SOC_DAPM_POST_PMD:
762 configure_clock(codec);
763 break;
764 }
765
766 return 0;
767 }
768
769 static void vmid_reference(struct snd_soc_codec *codec)
770 {
771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
772
773 pm_runtime_get_sync(codec->dev);
774
775 wm8994->vmid_refcount++;
776
777 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
778 wm8994->vmid_refcount);
779
780 if (wm8994->vmid_refcount == 1) {
781 /* Startup bias, VMID ramp & buffer */
782 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
783 WM8994_STARTUP_BIAS_ENA |
784 WM8994_VMID_BUF_ENA |
785 WM8994_VMID_RAMP_MASK,
786 WM8994_STARTUP_BIAS_ENA |
787 WM8994_VMID_BUF_ENA |
788 (0x3 << WM8994_VMID_RAMP_SHIFT));
789
790 /* Remove discharge for line out */
791 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
792 WM8994_LINEOUT1_DISCH |
793 WM8994_LINEOUT2_DISCH, 0);
794
795 /* Main bias enable, VMID=2x40k */
796 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
797 WM8994_BIAS_ENA |
798 WM8994_VMID_SEL_MASK,
799 WM8994_BIAS_ENA | 0x2);
800
801 msleep(20);
802 }
803 }
804
805 static void vmid_dereference(struct snd_soc_codec *codec)
806 {
807 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
808
809 wm8994->vmid_refcount--;
810
811 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
812 wm8994->vmid_refcount);
813
814 if (wm8994->vmid_refcount == 0) {
815 /* Switch over to startup biases */
816 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
817 WM8994_BIAS_SRC |
818 WM8994_STARTUP_BIAS_ENA |
819 WM8994_VMID_BUF_ENA |
820 WM8994_VMID_RAMP_MASK,
821 WM8994_BIAS_SRC |
822 WM8994_STARTUP_BIAS_ENA |
823 WM8994_VMID_BUF_ENA |
824 (1 << WM8994_VMID_RAMP_SHIFT));
825
826 /* Disable main biases */
827 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
828 WM8994_BIAS_ENA |
829 WM8994_VMID_SEL_MASK, 0);
830
831 /* Discharge line */
832 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
833 WM8994_LINEOUT1_DISCH |
834 WM8994_LINEOUT2_DISCH,
835 WM8994_LINEOUT1_DISCH |
836 WM8994_LINEOUT2_DISCH);
837
838 msleep(5);
839
840 /* Switch off startup biases */
841 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
842 WM8994_BIAS_SRC |
843 WM8994_STARTUP_BIAS_ENA |
844 WM8994_VMID_BUF_ENA |
845 WM8994_VMID_RAMP_MASK, 0);
846 }
847
848 pm_runtime_put(codec->dev);
849 }
850
851 static int vmid_event(struct snd_soc_dapm_widget *w,
852 struct snd_kcontrol *kcontrol, int event)
853 {
854 struct snd_soc_codec *codec = w->codec;
855
856 switch (event) {
857 case SND_SOC_DAPM_PRE_PMU:
858 vmid_reference(codec);
859 break;
860
861 case SND_SOC_DAPM_POST_PMD:
862 vmid_dereference(codec);
863 break;
864 }
865
866 return 0;
867 }
868
869 static void wm8994_update_class_w(struct snd_soc_codec *codec)
870 {
871 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
872 int enable = 1;
873 int source = 0; /* GCC flow analysis can't track enable */
874 int reg, reg_r;
875
876 /* Only support direct DAC->headphone paths */
877 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
878 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
879 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
880 enable = 0;
881 }
882
883 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
884 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
885 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
886 enable = 0;
887 }
888
889 /* We also need the same setting for L/R and only one path */
890 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
891 switch (reg) {
892 case WM8994_AIF2DACL_TO_DAC1L:
893 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
894 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
895 break;
896 case WM8994_AIF1DAC2L_TO_DAC1L:
897 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
898 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
899 break;
900 case WM8994_AIF1DAC1L_TO_DAC1L:
901 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
902 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
903 break;
904 default:
905 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
906 enable = 0;
907 break;
908 }
909
910 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
911 if (reg_r != reg) {
912 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
913 enable = 0;
914 }
915
916 if (enable) {
917 dev_dbg(codec->dev, "Class W enabled\n");
918 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
919 WM8994_CP_DYN_PWR |
920 WM8994_CP_DYN_SRC_SEL_MASK,
921 source | WM8994_CP_DYN_PWR);
922 wm8994->hubs.class_w = true;
923
924 } else {
925 dev_dbg(codec->dev, "Class W disabled\n");
926 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
927 WM8994_CP_DYN_PWR, 0);
928 wm8994->hubs.class_w = false;
929 }
930 }
931
932 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
933 struct snd_kcontrol *kcontrol, int event)
934 {
935 struct snd_soc_codec *codec = w->codec;
936 struct wm8994 *control = codec->control_data;
937 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
938 int dac;
939 int adc;
940 int val;
941
942 switch (control->type) {
943 case WM8994:
944 case WM8958:
945 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
946 break;
947 default:
948 break;
949 }
950
951 switch (event) {
952 case SND_SOC_DAPM_PRE_PMU:
953 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
954 if ((val & WM8994_AIF1ADCL_SRC) &&
955 (val & WM8994_AIF1ADCR_SRC))
956 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
957 else if (!(val & WM8994_AIF1ADCL_SRC) &&
958 !(val & WM8994_AIF1ADCR_SRC))
959 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
960 else
961 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
962 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
963
964 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
965 if ((val & WM8994_AIF1DACL_SRC) &&
966 (val & WM8994_AIF1DACR_SRC))
967 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
968 else if (!(val & WM8994_AIF1DACL_SRC) &&
969 !(val & WM8994_AIF1DACR_SRC))
970 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
971 else
972 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
973 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
974
975 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
976 mask, adc);
977 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
978 mask, dac);
979 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
980 WM8994_AIF1DSPCLK_ENA |
981 WM8994_SYSDSPCLK_ENA,
982 WM8994_AIF1DSPCLK_ENA |
983 WM8994_SYSDSPCLK_ENA);
984 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
985 WM8994_AIF1ADC1R_ENA |
986 WM8994_AIF1ADC1L_ENA |
987 WM8994_AIF1ADC2R_ENA |
988 WM8994_AIF1ADC2L_ENA);
989 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
990 WM8994_AIF1DAC1R_ENA |
991 WM8994_AIF1DAC1L_ENA |
992 WM8994_AIF1DAC2R_ENA |
993 WM8994_AIF1DAC2L_ENA);
994 break;
995
996 case SND_SOC_DAPM_PRE_PMD:
997 case SND_SOC_DAPM_POST_PMD:
998 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
999 mask, 0);
1000 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1001 mask, 0);
1002
1003 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1004 if (val & WM8994_AIF2DSPCLK_ENA)
1005 val = WM8994_SYSDSPCLK_ENA;
1006 else
1007 val = 0;
1008 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1009 WM8994_SYSDSPCLK_ENA |
1010 WM8994_AIF1DSPCLK_ENA, val);
1011 break;
1012 }
1013
1014 return 0;
1015 }
1016
1017 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1018 struct snd_kcontrol *kcontrol, int event)
1019 {
1020 struct snd_soc_codec *codec = w->codec;
1021 int dac;
1022 int adc;
1023 int val;
1024
1025 switch (event) {
1026 case SND_SOC_DAPM_PRE_PMU:
1027 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1028 if ((val & WM8994_AIF2ADCL_SRC) &&
1029 (val & WM8994_AIF2ADCR_SRC))
1030 adc = WM8994_AIF2ADCR_ENA;
1031 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1032 !(val & WM8994_AIF2ADCR_SRC))
1033 adc = WM8994_AIF2ADCL_ENA;
1034 else
1035 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1036
1037
1038 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1039 if ((val & WM8994_AIF2DACL_SRC) &&
1040 (val & WM8994_AIF2DACR_SRC))
1041 dac = WM8994_AIF2DACR_ENA;
1042 else if (!(val & WM8994_AIF2DACL_SRC) &&
1043 !(val & WM8994_AIF2DACR_SRC))
1044 dac = WM8994_AIF2DACL_ENA;
1045 else
1046 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1047
1048 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1049 WM8994_AIF2ADCL_ENA |
1050 WM8994_AIF2ADCR_ENA, adc);
1051 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1052 WM8994_AIF2DACL_ENA |
1053 WM8994_AIF2DACR_ENA, dac);
1054 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1055 WM8994_AIF2DSPCLK_ENA |
1056 WM8994_SYSDSPCLK_ENA,
1057 WM8994_AIF2DSPCLK_ENA |
1058 WM8994_SYSDSPCLK_ENA);
1059 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1060 WM8994_AIF2ADCL_ENA |
1061 WM8994_AIF2ADCR_ENA,
1062 WM8994_AIF2ADCL_ENA |
1063 WM8994_AIF2ADCR_ENA);
1064 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1065 WM8994_AIF2DACL_ENA |
1066 WM8994_AIF2DACR_ENA,
1067 WM8994_AIF2DACL_ENA |
1068 WM8994_AIF2DACR_ENA);
1069 break;
1070
1071 case SND_SOC_DAPM_PRE_PMD:
1072 case SND_SOC_DAPM_POST_PMD:
1073 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1074 WM8994_AIF2DACL_ENA |
1075 WM8994_AIF2DACR_ENA, 0);
1076 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1077 WM8994_AIF2ADCL_ENA |
1078 WM8994_AIF2ADCR_ENA, 0);
1079
1080 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1081 if (val & WM8994_AIF1DSPCLK_ENA)
1082 val = WM8994_SYSDSPCLK_ENA;
1083 else
1084 val = 0;
1085 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1086 WM8994_SYSDSPCLK_ENA |
1087 WM8994_AIF2DSPCLK_ENA, val);
1088 break;
1089 }
1090
1091 return 0;
1092 }
1093
1094 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1095 struct snd_kcontrol *kcontrol, int event)
1096 {
1097 struct snd_soc_codec *codec = w->codec;
1098 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1099
1100 switch (event) {
1101 case SND_SOC_DAPM_PRE_PMU:
1102 wm8994->aif1clk_enable = 1;
1103 break;
1104 case SND_SOC_DAPM_POST_PMD:
1105 wm8994->aif1clk_disable = 1;
1106 break;
1107 }
1108
1109 return 0;
1110 }
1111
1112 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1113 struct snd_kcontrol *kcontrol, int event)
1114 {
1115 struct snd_soc_codec *codec = w->codec;
1116 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1117
1118 switch (event) {
1119 case SND_SOC_DAPM_PRE_PMU:
1120 wm8994->aif2clk_enable = 1;
1121 break;
1122 case SND_SOC_DAPM_POST_PMD:
1123 wm8994->aif2clk_disable = 1;
1124 break;
1125 }
1126
1127 return 0;
1128 }
1129
1130 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1131 struct snd_kcontrol *kcontrol, int event)
1132 {
1133 struct snd_soc_codec *codec = w->codec;
1134 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1135
1136 switch (event) {
1137 case SND_SOC_DAPM_PRE_PMU:
1138 if (wm8994->aif1clk_enable) {
1139 aif1clk_ev(w, kcontrol, event);
1140 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1141 WM8994_AIF1CLK_ENA_MASK,
1142 WM8994_AIF1CLK_ENA);
1143 wm8994->aif1clk_enable = 0;
1144 }
1145 if (wm8994->aif2clk_enable) {
1146 aif2clk_ev(w, kcontrol, event);
1147 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1148 WM8994_AIF2CLK_ENA_MASK,
1149 WM8994_AIF2CLK_ENA);
1150 wm8994->aif2clk_enable = 0;
1151 }
1152 break;
1153 }
1154
1155 /* We may also have postponed startup of DSP, handle that. */
1156 wm8958_aif_ev(w, kcontrol, event);
1157
1158 return 0;
1159 }
1160
1161 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1162 struct snd_kcontrol *kcontrol, int event)
1163 {
1164 struct snd_soc_codec *codec = w->codec;
1165 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1166
1167 switch (event) {
1168 case SND_SOC_DAPM_POST_PMD:
1169 if (wm8994->aif1clk_disable) {
1170 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1171 WM8994_AIF1CLK_ENA_MASK, 0);
1172 aif1clk_ev(w, kcontrol, event);
1173 wm8994->aif1clk_disable = 0;
1174 }
1175 if (wm8994->aif2clk_disable) {
1176 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1177 WM8994_AIF2CLK_ENA_MASK, 0);
1178 aif2clk_ev(w, kcontrol, event);
1179 wm8994->aif2clk_disable = 0;
1180 }
1181 break;
1182 }
1183
1184 return 0;
1185 }
1186
1187 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1188 struct snd_kcontrol *kcontrol, int event)
1189 {
1190 late_enable_ev(w, kcontrol, event);
1191 return 0;
1192 }
1193
1194 static int micbias_ev(struct snd_soc_dapm_widget *w,
1195 struct snd_kcontrol *kcontrol, int event)
1196 {
1197 late_enable_ev(w, kcontrol, event);
1198 return 0;
1199 }
1200
1201 static int dac_ev(struct snd_soc_dapm_widget *w,
1202 struct snd_kcontrol *kcontrol, int event)
1203 {
1204 struct snd_soc_codec *codec = w->codec;
1205 unsigned int mask = 1 << w->shift;
1206
1207 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1208 mask, mask);
1209 return 0;
1210 }
1211
1212 static const char *hp_mux_text[] = {
1213 "Mixer",
1214 "DAC",
1215 };
1216
1217 #define WM8994_HP_ENUM(xname, xenum) \
1218 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1219 .info = snd_soc_info_enum_double, \
1220 .get = snd_soc_dapm_get_enum_double, \
1221 .put = wm8994_put_hp_enum, \
1222 .private_value = (unsigned long)&xenum }
1223
1224 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1225 struct snd_ctl_elem_value *ucontrol)
1226 {
1227 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1228 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1229 struct snd_soc_codec *codec = w->codec;
1230 int ret;
1231
1232 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1233
1234 wm8994_update_class_w(codec);
1235
1236 return ret;
1237 }
1238
1239 static const struct soc_enum hpl_enum =
1240 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1241
1242 static const struct snd_kcontrol_new hpl_mux =
1243 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1244
1245 static const struct soc_enum hpr_enum =
1246 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1247
1248 static const struct snd_kcontrol_new hpr_mux =
1249 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1250
1251 static const char *adc_mux_text[] = {
1252 "ADC",
1253 "DMIC",
1254 };
1255
1256 static const struct soc_enum adc_enum =
1257 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1258
1259 static const struct snd_kcontrol_new adcl_mux =
1260 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1261
1262 static const struct snd_kcontrol_new adcr_mux =
1263 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1264
1265 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1266 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1267 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1268 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1269 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1270 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1271 };
1272
1273 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1274 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1275 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1276 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1277 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1278 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1279 };
1280
1281 /* Debugging; dump chip status after DAPM transitions */
1282 static int post_ev(struct snd_soc_dapm_widget *w,
1283 struct snd_kcontrol *kcontrol, int event)
1284 {
1285 struct snd_soc_codec *codec = w->codec;
1286 dev_dbg(codec->dev, "SRC status: %x\n",
1287 snd_soc_read(codec,
1288 WM8994_RATE_STATUS));
1289 return 0;
1290 }
1291
1292 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1293 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1294 1, 1, 0),
1295 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1296 0, 1, 0),
1297 };
1298
1299 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1300 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1301 1, 1, 0),
1302 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1303 0, 1, 0),
1304 };
1305
1306 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1307 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1308 1, 1, 0),
1309 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1310 0, 1, 0),
1311 };
1312
1313 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1314 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1315 1, 1, 0),
1316 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1317 0, 1, 0),
1318 };
1319
1320 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1321 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1322 5, 1, 0),
1323 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1324 4, 1, 0),
1325 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1326 2, 1, 0),
1327 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1328 1, 1, 0),
1329 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1330 0, 1, 0),
1331 };
1332
1333 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1334 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1335 5, 1, 0),
1336 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1337 4, 1, 0),
1338 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1339 2, 1, 0),
1340 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1341 1, 1, 0),
1342 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1343 0, 1, 0),
1344 };
1345
1346 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1347 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1348 .info = snd_soc_info_volsw, \
1349 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1350 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1351
1352 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1353 struct snd_ctl_elem_value *ucontrol)
1354 {
1355 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1356 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1357 struct snd_soc_codec *codec = w->codec;
1358 int ret;
1359
1360 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1361
1362 wm8994_update_class_w(codec);
1363
1364 return ret;
1365 }
1366
1367 static const struct snd_kcontrol_new dac1l_mix[] = {
1368 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1369 5, 1, 0),
1370 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1371 4, 1, 0),
1372 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1373 2, 1, 0),
1374 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1375 1, 1, 0),
1376 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1377 0, 1, 0),
1378 };
1379
1380 static const struct snd_kcontrol_new dac1r_mix[] = {
1381 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1382 5, 1, 0),
1383 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1384 4, 1, 0),
1385 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1386 2, 1, 0),
1387 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1388 1, 1, 0),
1389 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1390 0, 1, 0),
1391 };
1392
1393 static const char *sidetone_text[] = {
1394 "ADC/DMIC1", "DMIC2",
1395 };
1396
1397 static const struct soc_enum sidetone1_enum =
1398 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1399
1400 static const struct snd_kcontrol_new sidetone1_mux =
1401 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1402
1403 static const struct soc_enum sidetone2_enum =
1404 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1405
1406 static const struct snd_kcontrol_new sidetone2_mux =
1407 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1408
1409 static const char *aif1dac_text[] = {
1410 "AIF1DACDAT", "AIF3DACDAT",
1411 };
1412
1413 static const struct soc_enum aif1dac_enum =
1414 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1415
1416 static const struct snd_kcontrol_new aif1dac_mux =
1417 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1418
1419 static const char *aif2dac_text[] = {
1420 "AIF2DACDAT", "AIF3DACDAT",
1421 };
1422
1423 static const struct soc_enum aif2dac_enum =
1424 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1425
1426 static const struct snd_kcontrol_new aif2dac_mux =
1427 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1428
1429 static const char *aif2adc_text[] = {
1430 "AIF2ADCDAT", "AIF3DACDAT",
1431 };
1432
1433 static const struct soc_enum aif2adc_enum =
1434 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1435
1436 static const struct snd_kcontrol_new aif2adc_mux =
1437 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1438
1439 static const char *aif3adc_text[] = {
1440 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1441 };
1442
1443 static const struct soc_enum wm8994_aif3adc_enum =
1444 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1445
1446 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1447 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1448
1449 static const struct soc_enum wm8958_aif3adc_enum =
1450 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1451
1452 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1453 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1454
1455 static const char *mono_pcm_out_text[] = {
1456 "None", "AIF2ADCL", "AIF2ADCR",
1457 };
1458
1459 static const struct soc_enum mono_pcm_out_enum =
1460 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1461
1462 static const struct snd_kcontrol_new mono_pcm_out_mux =
1463 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1464
1465 static const char *aif2dac_src_text[] = {
1466 "AIF2", "AIF3",
1467 };
1468
1469 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1470 static const struct soc_enum aif2dacl_src_enum =
1471 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1472
1473 static const struct snd_kcontrol_new aif2dacl_src_mux =
1474 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1475
1476 static const struct soc_enum aif2dacr_src_enum =
1477 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1478
1479 static const struct snd_kcontrol_new aif2dacr_src_mux =
1480 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1481
1482 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1483 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1484 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1485 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1486 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1487
1488 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1489 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1490 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1491 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1492 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1493 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1494 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1495 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1496 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1497 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1498
1499 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1500 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1501 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1502 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1503 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1504 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1505 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1506 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1507 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1508 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1509
1510 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1511 };
1512
1513 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1514 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1515 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1516 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1517 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1518 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1519 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1520 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1521 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1522 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1523 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1524 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1525 };
1526
1527 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1528 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1529 dac_ev, SND_SOC_DAPM_PRE_PMU),
1530 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1531 dac_ev, SND_SOC_DAPM_PRE_PMU),
1532 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1533 dac_ev, SND_SOC_DAPM_PRE_PMU),
1534 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1535 dac_ev, SND_SOC_DAPM_PRE_PMU),
1536 };
1537
1538 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1539 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1540 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1541 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1542 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1543 };
1544
1545 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1546 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1547 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1548 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1549 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1550 };
1551
1552 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1553 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1554 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1555 };
1556
1557 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1558 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1559 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1560 SND_SOC_DAPM_INPUT("Clock"),
1561
1562 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1563 SND_SOC_DAPM_PRE_PMU),
1564 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1565 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1566
1567 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1568 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1569
1570 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1571 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1572 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1573
1574 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1575 0, SND_SOC_NOPM, 9, 0),
1576 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1577 0, SND_SOC_NOPM, 8, 0),
1578 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1579 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1580 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1581 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1582 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1583 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1584
1585 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1586 0, SND_SOC_NOPM, 11, 0),
1587 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1588 0, SND_SOC_NOPM, 10, 0),
1589 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1590 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1591 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1592 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1593 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1594 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1595
1596 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1597 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1598 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1599 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1600
1601 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1602 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1603 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1604 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1605
1606 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1607 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1608 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1609 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1610
1611 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1612 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1613
1614 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1615 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1616 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1617 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1618
1619 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1620 SND_SOC_NOPM, 13, 0),
1621 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1622 SND_SOC_NOPM, 12, 0),
1623 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1624 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1625 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1626 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1627 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1628 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1629
1630 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1631 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1632 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1633 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1634
1635 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1636 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1637 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1638
1639 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1640 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1641
1642 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1643
1644 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1645 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1646 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1647 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1648
1649 /* Power is done with the muxes since the ADC power also controls the
1650 * downsampling chain, the chip will automatically manage the analogue
1651 * specific portions.
1652 */
1653 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1654 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1655
1656 SND_SOC_DAPM_POST("Debug log", post_ev),
1657 };
1658
1659 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1660 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1661 };
1662
1663 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1664 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1665 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1666 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1667 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1668 };
1669
1670 static const struct snd_soc_dapm_route intercon[] = {
1671 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1672 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1673
1674 { "DSP1CLK", NULL, "CLK_SYS" },
1675 { "DSP2CLK", NULL, "CLK_SYS" },
1676 { "DSPINTCLK", NULL, "CLK_SYS" },
1677
1678 { "AIF1ADC1L", NULL, "AIF1CLK" },
1679 { "AIF1ADC1L", NULL, "DSP1CLK" },
1680 { "AIF1ADC1R", NULL, "AIF1CLK" },
1681 { "AIF1ADC1R", NULL, "DSP1CLK" },
1682 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1683
1684 { "AIF1DAC1L", NULL, "AIF1CLK" },
1685 { "AIF1DAC1L", NULL, "DSP1CLK" },
1686 { "AIF1DAC1R", NULL, "AIF1CLK" },
1687 { "AIF1DAC1R", NULL, "DSP1CLK" },
1688 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1689
1690 { "AIF1ADC2L", NULL, "AIF1CLK" },
1691 { "AIF1ADC2L", NULL, "DSP1CLK" },
1692 { "AIF1ADC2R", NULL, "AIF1CLK" },
1693 { "AIF1ADC2R", NULL, "DSP1CLK" },
1694 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1695
1696 { "AIF1DAC2L", NULL, "AIF1CLK" },
1697 { "AIF1DAC2L", NULL, "DSP1CLK" },
1698 { "AIF1DAC2R", NULL, "AIF1CLK" },
1699 { "AIF1DAC2R", NULL, "DSP1CLK" },
1700 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1701
1702 { "AIF2ADCL", NULL, "AIF2CLK" },
1703 { "AIF2ADCL", NULL, "DSP2CLK" },
1704 { "AIF2ADCR", NULL, "AIF2CLK" },
1705 { "AIF2ADCR", NULL, "DSP2CLK" },
1706 { "AIF2ADCR", NULL, "DSPINTCLK" },
1707
1708 { "AIF2DACL", NULL, "AIF2CLK" },
1709 { "AIF2DACL", NULL, "DSP2CLK" },
1710 { "AIF2DACR", NULL, "AIF2CLK" },
1711 { "AIF2DACR", NULL, "DSP2CLK" },
1712 { "AIF2DACR", NULL, "DSPINTCLK" },
1713
1714 { "DMIC1L", NULL, "DMIC1DAT" },
1715 { "DMIC1L", NULL, "CLK_SYS" },
1716 { "DMIC1R", NULL, "DMIC1DAT" },
1717 { "DMIC1R", NULL, "CLK_SYS" },
1718 { "DMIC2L", NULL, "DMIC2DAT" },
1719 { "DMIC2L", NULL, "CLK_SYS" },
1720 { "DMIC2R", NULL, "DMIC2DAT" },
1721 { "DMIC2R", NULL, "CLK_SYS" },
1722
1723 { "ADCL", NULL, "AIF1CLK" },
1724 { "ADCL", NULL, "DSP1CLK" },
1725 { "ADCL", NULL, "DSPINTCLK" },
1726
1727 { "ADCR", NULL, "AIF1CLK" },
1728 { "ADCR", NULL, "DSP1CLK" },
1729 { "ADCR", NULL, "DSPINTCLK" },
1730
1731 { "ADCL Mux", "ADC", "ADCL" },
1732 { "ADCL Mux", "DMIC", "DMIC1L" },
1733 { "ADCR Mux", "ADC", "ADCR" },
1734 { "ADCR Mux", "DMIC", "DMIC1R" },
1735
1736 { "DAC1L", NULL, "AIF1CLK" },
1737 { "DAC1L", NULL, "DSP1CLK" },
1738 { "DAC1L", NULL, "DSPINTCLK" },
1739
1740 { "DAC1R", NULL, "AIF1CLK" },
1741 { "DAC1R", NULL, "DSP1CLK" },
1742 { "DAC1R", NULL, "DSPINTCLK" },
1743
1744 { "DAC2L", NULL, "AIF2CLK" },
1745 { "DAC2L", NULL, "DSP2CLK" },
1746 { "DAC2L", NULL, "DSPINTCLK" },
1747
1748 { "DAC2R", NULL, "AIF2DACR" },
1749 { "DAC2R", NULL, "AIF2CLK" },
1750 { "DAC2R", NULL, "DSP2CLK" },
1751 { "DAC2R", NULL, "DSPINTCLK" },
1752
1753 { "TOCLK", NULL, "CLK_SYS" },
1754
1755 /* AIF1 outputs */
1756 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1757 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1758 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1759
1760 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1761 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1762 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1763
1764 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1765 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1766 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1767
1768 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1769 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1770 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1771
1772 /* Pin level routing for AIF3 */
1773 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1774 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1775 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1776 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1777
1778 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1779 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1780 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1781 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1782 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1783 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1784 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1785
1786 /* DAC1 inputs */
1787 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1788 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1789 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1790 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1791 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1792
1793 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1794 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1795 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1796 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1797 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1798
1799 /* DAC2/AIF2 outputs */
1800 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1801 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1802 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1803 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1804 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1805 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1806
1807 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1808 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1809 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1810 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1811 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1812 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1813
1814 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1815 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1816 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1817 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1818
1819 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1820
1821 /* AIF3 output */
1822 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1823 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1824 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1825 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1826 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1827 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1828 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1829 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1830
1831 /* Sidetone */
1832 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1833 { "Left Sidetone", "DMIC2", "DMIC2L" },
1834 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1835 { "Right Sidetone", "DMIC2", "DMIC2R" },
1836
1837 /* Output stages */
1838 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1839 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1840
1841 { "SPKL", "DAC1 Switch", "DAC1L" },
1842 { "SPKL", "DAC2 Switch", "DAC2L" },
1843
1844 { "SPKR", "DAC1 Switch", "DAC1R" },
1845 { "SPKR", "DAC2 Switch", "DAC2R" },
1846
1847 { "Left Headphone Mux", "DAC", "DAC1L" },
1848 { "Right Headphone Mux", "DAC", "DAC1R" },
1849 };
1850
1851 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1852 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1853 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1854 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1855 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1856 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1857 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1858 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1859 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1860 };
1861
1862 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1863 { "DAC1L", NULL, "DAC1L Mixer" },
1864 { "DAC1R", NULL, "DAC1R Mixer" },
1865 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1866 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1867 };
1868
1869 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1870 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1871 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1872 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1873 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1874 { "MICBIAS1", NULL, "CLK_SYS" },
1875 { "MICBIAS1", NULL, "MICBIAS Supply" },
1876 { "MICBIAS2", NULL, "CLK_SYS" },
1877 { "MICBIAS2", NULL, "MICBIAS Supply" },
1878 };
1879
1880 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1881 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1882 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1883 { "MICBIAS1", NULL, "VMID" },
1884 { "MICBIAS2", NULL, "VMID" },
1885 };
1886
1887 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1888 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1889 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1890
1891 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1892 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1893 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1894 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1895
1896 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1897 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1898
1899 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1900 };
1901
1902 /* The size in bits of the FLL divide multiplied by 10
1903 * to allow rounding later */
1904 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1905
1906 struct fll_div {
1907 u16 outdiv;
1908 u16 n;
1909 u16 k;
1910 u16 clk_ref_div;
1911 u16 fll_fratio;
1912 };
1913
1914 static int wm8994_get_fll_config(struct fll_div *fll,
1915 int freq_in, int freq_out)
1916 {
1917 u64 Kpart;
1918 unsigned int K, Ndiv, Nmod;
1919
1920 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1921
1922 /* Scale the input frequency down to <= 13.5MHz */
1923 fll->clk_ref_div = 0;
1924 while (freq_in > 13500000) {
1925 fll->clk_ref_div++;
1926 freq_in /= 2;
1927
1928 if (fll->clk_ref_div > 3)
1929 return -EINVAL;
1930 }
1931 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1932
1933 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1934 fll->outdiv = 3;
1935 while (freq_out * (fll->outdiv + 1) < 90000000) {
1936 fll->outdiv++;
1937 if (fll->outdiv > 63)
1938 return -EINVAL;
1939 }
1940 freq_out *= fll->outdiv + 1;
1941 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1942
1943 if (freq_in > 1000000) {
1944 fll->fll_fratio = 0;
1945 } else if (freq_in > 256000) {
1946 fll->fll_fratio = 1;
1947 freq_in *= 2;
1948 } else if (freq_in > 128000) {
1949 fll->fll_fratio = 2;
1950 freq_in *= 4;
1951 } else if (freq_in > 64000) {
1952 fll->fll_fratio = 3;
1953 freq_in *= 8;
1954 } else {
1955 fll->fll_fratio = 4;
1956 freq_in *= 16;
1957 }
1958 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1959
1960 /* Now, calculate N.K */
1961 Ndiv = freq_out / freq_in;
1962
1963 fll->n = Ndiv;
1964 Nmod = freq_out % freq_in;
1965 pr_debug("Nmod=%d\n", Nmod);
1966
1967 /* Calculate fractional part - scale up so we can round. */
1968 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1969
1970 do_div(Kpart, freq_in);
1971
1972 K = Kpart & 0xFFFFFFFF;
1973
1974 if ((K % 10) >= 5)
1975 K += 5;
1976
1977 /* Move down to proper range now rounding is done */
1978 fll->k = K / 10;
1979
1980 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1981
1982 return 0;
1983 }
1984
1985 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1986 unsigned int freq_in, unsigned int freq_out)
1987 {
1988 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1989 struct wm8994 *control = wm8994->wm8994;
1990 int reg_offset, ret;
1991 struct fll_div fll;
1992 u16 reg, aif1, aif2;
1993 unsigned long timeout;
1994 bool was_enabled;
1995
1996 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1997 & WM8994_AIF1CLK_ENA;
1998
1999 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
2000 & WM8994_AIF2CLK_ENA;
2001
2002 switch (id) {
2003 case WM8994_FLL1:
2004 reg_offset = 0;
2005 id = 0;
2006 break;
2007 case WM8994_FLL2:
2008 reg_offset = 0x20;
2009 id = 1;
2010 break;
2011 default:
2012 return -EINVAL;
2013 }
2014
2015 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2016 was_enabled = reg & WM8994_FLL1_ENA;
2017
2018 switch (src) {
2019 case 0:
2020 /* Allow no source specification when stopping */
2021 if (freq_out)
2022 return -EINVAL;
2023 src = wm8994->fll[id].src;
2024 break;
2025 case WM8994_FLL_SRC_MCLK1:
2026 case WM8994_FLL_SRC_MCLK2:
2027 case WM8994_FLL_SRC_LRCLK:
2028 case WM8994_FLL_SRC_BCLK:
2029 break;
2030 default:
2031 return -EINVAL;
2032 }
2033
2034 /* Are we changing anything? */
2035 if (wm8994->fll[id].src == src &&
2036 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2037 return 0;
2038
2039 /* If we're stopping the FLL redo the old config - no
2040 * registers will actually be written but we avoid GCC flow
2041 * analysis bugs spewing warnings.
2042 */
2043 if (freq_out)
2044 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2045 else
2046 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2047 wm8994->fll[id].out);
2048 if (ret < 0)
2049 return ret;
2050
2051 /* Gate the AIF clocks while we reclock */
2052 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2053 WM8994_AIF1CLK_ENA, 0);
2054 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2055 WM8994_AIF2CLK_ENA, 0);
2056
2057 /* We always need to disable the FLL while reconfiguring */
2058 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2059 WM8994_FLL1_ENA, 0);
2060
2061 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2062 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2063 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2064 WM8994_FLL1_OUTDIV_MASK |
2065 WM8994_FLL1_FRATIO_MASK, reg);
2066
2067 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
2068
2069 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2070 WM8994_FLL1_N_MASK,
2071 fll.n << WM8994_FLL1_N_SHIFT);
2072
2073 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2074 WM8994_FLL1_REFCLK_DIV_MASK |
2075 WM8994_FLL1_REFCLK_SRC_MASK,
2076 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2077 (src - 1));
2078
2079 /* Clear any pending completion from a previous failure */
2080 try_wait_for_completion(&wm8994->fll_locked[id]);
2081
2082 /* Enable (with fractional mode if required) */
2083 if (freq_out) {
2084 /* Enable VMID if we need it */
2085 if (!was_enabled) {
2086 active_reference(codec);
2087
2088 switch (control->type) {
2089 case WM8994:
2090 vmid_reference(codec);
2091 break;
2092 case WM8958:
2093 if (wm8994->revision < 1)
2094 vmid_reference(codec);
2095 break;
2096 default:
2097 break;
2098 }
2099 }
2100
2101 if (fll.k)
2102 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2103 else
2104 reg = WM8994_FLL1_ENA;
2105 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2106 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2107 reg);
2108
2109 if (wm8994->fll_locked_irq) {
2110 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2111 msecs_to_jiffies(10));
2112 if (timeout == 0)
2113 dev_warn(codec->dev,
2114 "Timed out waiting for FLL lock\n");
2115 } else {
2116 msleep(5);
2117 }
2118 } else {
2119 if (was_enabled) {
2120 switch (control->type) {
2121 case WM8994:
2122 vmid_dereference(codec);
2123 break;
2124 case WM8958:
2125 if (wm8994->revision < 1)
2126 vmid_dereference(codec);
2127 break;
2128 default:
2129 break;
2130 }
2131
2132 active_dereference(codec);
2133 }
2134 }
2135
2136 wm8994->fll[id].in = freq_in;
2137 wm8994->fll[id].out = freq_out;
2138 wm8994->fll[id].src = src;
2139
2140 /* Enable any gated AIF clocks */
2141 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2142 WM8994_AIF1CLK_ENA, aif1);
2143 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2144 WM8994_AIF2CLK_ENA, aif2);
2145
2146 configure_clock(codec);
2147
2148 return 0;
2149 }
2150
2151 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2152 {
2153 struct completion *completion = data;
2154
2155 complete(completion);
2156
2157 return IRQ_HANDLED;
2158 }
2159
2160 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2161
2162 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2163 unsigned int freq_in, unsigned int freq_out)
2164 {
2165 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2166 }
2167
2168 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2169 int clk_id, unsigned int freq, int dir)
2170 {
2171 struct snd_soc_codec *codec = dai->codec;
2172 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2173 int i;
2174
2175 switch (dai->id) {
2176 case 1:
2177 case 2:
2178 break;
2179
2180 default:
2181 /* AIF3 shares clocking with AIF1/2 */
2182 return -EINVAL;
2183 }
2184
2185 switch (clk_id) {
2186 case WM8994_SYSCLK_MCLK1:
2187 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2188 wm8994->mclk[0] = freq;
2189 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2190 dai->id, freq);
2191 break;
2192
2193 case WM8994_SYSCLK_MCLK2:
2194 /* TODO: Set GPIO AF */
2195 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2196 wm8994->mclk[1] = freq;
2197 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2198 dai->id, freq);
2199 break;
2200
2201 case WM8994_SYSCLK_FLL1:
2202 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2203 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2204 break;
2205
2206 case WM8994_SYSCLK_FLL2:
2207 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2208 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2209 break;
2210
2211 case WM8994_SYSCLK_OPCLK:
2212 /* Special case - a division (times 10) is given and
2213 * no effect on main clocking.
2214 */
2215 if (freq) {
2216 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2217 if (opclk_divs[i] == freq)
2218 break;
2219 if (i == ARRAY_SIZE(opclk_divs))
2220 return -EINVAL;
2221 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2222 WM8994_OPCLK_DIV_MASK, i);
2223 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2224 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2225 } else {
2226 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2227 WM8994_OPCLK_ENA, 0);
2228 }
2229
2230 default:
2231 return -EINVAL;
2232 }
2233
2234 configure_clock(codec);
2235
2236 return 0;
2237 }
2238
2239 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2240 enum snd_soc_bias_level level)
2241 {
2242 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2243 struct wm8994 *control = wm8994->wm8994;
2244
2245 switch (level) {
2246 case SND_SOC_BIAS_ON:
2247 break;
2248
2249 case SND_SOC_BIAS_PREPARE:
2250 /* MICBIAS into regulating mode */
2251 switch (control->type) {
2252 case WM8958:
2253 case WM1811:
2254 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2255 WM8958_MICB1_MODE, 0);
2256 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2257 WM8958_MICB2_MODE, 0);
2258 break;
2259 default:
2260 break;
2261 }
2262
2263 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2264 active_reference(codec);
2265 break;
2266
2267 case SND_SOC_BIAS_STANDBY:
2268 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2269 switch (control->type) {
2270 case WM8994:
2271 if (wm8994->revision < 4) {
2272 /* Tweak DC servo and DSP
2273 * configuration for improved
2274 * performance. */
2275 snd_soc_write(codec, 0x102, 0x3);
2276 snd_soc_write(codec, 0x56, 0x3);
2277 snd_soc_write(codec, 0x817, 0);
2278 snd_soc_write(codec, 0x102, 0);
2279 }
2280 break;
2281
2282 case WM8958:
2283 if (wm8994->revision == 0) {
2284 /* Optimise performance for rev A */
2285 snd_soc_write(codec, 0x102, 0x3);
2286 snd_soc_write(codec, 0xcb, 0x81);
2287 snd_soc_write(codec, 0x817, 0);
2288 snd_soc_write(codec, 0x102, 0);
2289
2290 snd_soc_update_bits(codec,
2291 WM8958_CHARGE_PUMP_2,
2292 WM8958_CP_DISCH,
2293 WM8958_CP_DISCH);
2294 }
2295 break;
2296
2297 case WM1811:
2298 if (wm8994->revision < 2) {
2299 snd_soc_write(codec, 0x102, 0x3);
2300 snd_soc_write(codec, 0x5d, 0x7e);
2301 snd_soc_write(codec, 0x5e, 0x0);
2302 snd_soc_write(codec, 0x102, 0x0);
2303 }
2304 break;
2305 }
2306
2307 /* Discharge LINEOUT1 & 2 */
2308 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2309 WM8994_LINEOUT1_DISCH |
2310 WM8994_LINEOUT2_DISCH,
2311 WM8994_LINEOUT1_DISCH |
2312 WM8994_LINEOUT2_DISCH);
2313 }
2314
2315 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2316 active_dereference(codec);
2317
2318 /* MICBIAS into bypass mode on newer devices */
2319 switch (control->type) {
2320 case WM8958:
2321 case WM1811:
2322 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2323 WM8958_MICB1_MODE,
2324 WM8958_MICB1_MODE);
2325 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2326 WM8958_MICB2_MODE,
2327 WM8958_MICB2_MODE);
2328 break;
2329 default:
2330 break;
2331 }
2332 break;
2333
2334 case SND_SOC_BIAS_OFF:
2335 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2336 wm8994->cur_fw = NULL;
2337 break;
2338 }
2339 codec->dapm.bias_level = level;
2340
2341 return 0;
2342 }
2343
2344 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2345 {
2346 struct snd_soc_codec *codec = dai->codec;
2347 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2348 struct wm8994 *control = wm8994->wm8994;
2349 int ms_reg;
2350 int aif1_reg;
2351 int ms = 0;
2352 int aif1 = 0;
2353
2354 switch (dai->id) {
2355 case 1:
2356 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2357 aif1_reg = WM8994_AIF1_CONTROL_1;
2358 break;
2359 case 2:
2360 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2361 aif1_reg = WM8994_AIF2_CONTROL_1;
2362 break;
2363 default:
2364 return -EINVAL;
2365 }
2366
2367 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2368 case SND_SOC_DAIFMT_CBS_CFS:
2369 break;
2370 case SND_SOC_DAIFMT_CBM_CFM:
2371 ms = WM8994_AIF1_MSTR;
2372 break;
2373 default:
2374 return -EINVAL;
2375 }
2376
2377 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2378 case SND_SOC_DAIFMT_DSP_B:
2379 aif1 |= WM8994_AIF1_LRCLK_INV;
2380 case SND_SOC_DAIFMT_DSP_A:
2381 aif1 |= 0x18;
2382 break;
2383 case SND_SOC_DAIFMT_I2S:
2384 aif1 |= 0x10;
2385 break;
2386 case SND_SOC_DAIFMT_RIGHT_J:
2387 break;
2388 case SND_SOC_DAIFMT_LEFT_J:
2389 aif1 |= 0x8;
2390 break;
2391 default:
2392 return -EINVAL;
2393 }
2394
2395 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2396 case SND_SOC_DAIFMT_DSP_A:
2397 case SND_SOC_DAIFMT_DSP_B:
2398 /* frame inversion not valid for DSP modes */
2399 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2400 case SND_SOC_DAIFMT_NB_NF:
2401 break;
2402 case SND_SOC_DAIFMT_IB_NF:
2403 aif1 |= WM8994_AIF1_BCLK_INV;
2404 break;
2405 default:
2406 return -EINVAL;
2407 }
2408 break;
2409
2410 case SND_SOC_DAIFMT_I2S:
2411 case SND_SOC_DAIFMT_RIGHT_J:
2412 case SND_SOC_DAIFMT_LEFT_J:
2413 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2414 case SND_SOC_DAIFMT_NB_NF:
2415 break;
2416 case SND_SOC_DAIFMT_IB_IF:
2417 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2418 break;
2419 case SND_SOC_DAIFMT_IB_NF:
2420 aif1 |= WM8994_AIF1_BCLK_INV;
2421 break;
2422 case SND_SOC_DAIFMT_NB_IF:
2423 aif1 |= WM8994_AIF1_LRCLK_INV;
2424 break;
2425 default:
2426 return -EINVAL;
2427 }
2428 break;
2429 default:
2430 return -EINVAL;
2431 }
2432
2433 /* The AIF2 format configuration needs to be mirrored to AIF3
2434 * on WM8958 if it's in use so just do it all the time. */
2435 switch (control->type) {
2436 case WM1811:
2437 case WM8958:
2438 if (dai->id == 2)
2439 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2440 WM8994_AIF1_LRCLK_INV |
2441 WM8958_AIF3_FMT_MASK, aif1);
2442 break;
2443
2444 default:
2445 break;
2446 }
2447
2448 snd_soc_update_bits(codec, aif1_reg,
2449 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2450 WM8994_AIF1_FMT_MASK,
2451 aif1);
2452 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2453 ms);
2454
2455 return 0;
2456 }
2457
2458 static struct {
2459 int val, rate;
2460 } srs[] = {
2461 { 0, 8000 },
2462 { 1, 11025 },
2463 { 2, 12000 },
2464 { 3, 16000 },
2465 { 4, 22050 },
2466 { 5, 24000 },
2467 { 6, 32000 },
2468 { 7, 44100 },
2469 { 8, 48000 },
2470 { 9, 88200 },
2471 { 10, 96000 },
2472 };
2473
2474 static int fs_ratios[] = {
2475 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2476 };
2477
2478 static int bclk_divs[] = {
2479 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2480 640, 880, 960, 1280, 1760, 1920
2481 };
2482
2483 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2484 struct snd_pcm_hw_params *params,
2485 struct snd_soc_dai *dai)
2486 {
2487 struct snd_soc_codec *codec = dai->codec;
2488 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2489 int aif1_reg;
2490 int aif2_reg;
2491 int bclk_reg;
2492 int lrclk_reg;
2493 int rate_reg;
2494 int aif1 = 0;
2495 int aif2 = 0;
2496 int bclk = 0;
2497 int lrclk = 0;
2498 int rate_val = 0;
2499 int id = dai->id - 1;
2500
2501 int i, cur_val, best_val, bclk_rate, best;
2502
2503 switch (dai->id) {
2504 case 1:
2505 aif1_reg = WM8994_AIF1_CONTROL_1;
2506 aif2_reg = WM8994_AIF1_CONTROL_2;
2507 bclk_reg = WM8994_AIF1_BCLK;
2508 rate_reg = WM8994_AIF1_RATE;
2509 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2510 wm8994->lrclk_shared[0]) {
2511 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2512 } else {
2513 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2514 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2515 }
2516 break;
2517 case 2:
2518 aif1_reg = WM8994_AIF2_CONTROL_1;
2519 aif2_reg = WM8994_AIF2_CONTROL_2;
2520 bclk_reg = WM8994_AIF2_BCLK;
2521 rate_reg = WM8994_AIF2_RATE;
2522 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2523 wm8994->lrclk_shared[1]) {
2524 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2525 } else {
2526 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2527 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2528 }
2529 break;
2530 default:
2531 return -EINVAL;
2532 }
2533
2534 bclk_rate = params_rate(params) * 2;
2535 switch (params_format(params)) {
2536 case SNDRV_PCM_FORMAT_S16_LE:
2537 bclk_rate *= 16;
2538 break;
2539 case SNDRV_PCM_FORMAT_S20_3LE:
2540 bclk_rate *= 20;
2541 aif1 |= 0x20;
2542 break;
2543 case SNDRV_PCM_FORMAT_S24_LE:
2544 bclk_rate *= 24;
2545 aif1 |= 0x40;
2546 break;
2547 case SNDRV_PCM_FORMAT_S32_LE:
2548 bclk_rate *= 32;
2549 aif1 |= 0x60;
2550 break;
2551 default:
2552 return -EINVAL;
2553 }
2554
2555 /* Try to find an appropriate sample rate; look for an exact match. */
2556 for (i = 0; i < ARRAY_SIZE(srs); i++)
2557 if (srs[i].rate == params_rate(params))
2558 break;
2559 if (i == ARRAY_SIZE(srs))
2560 return -EINVAL;
2561 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2562
2563 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2564 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2565 dai->id, wm8994->aifclk[id], bclk_rate);
2566
2567 if (params_channels(params) == 1 &&
2568 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2569 aif2 |= WM8994_AIF1_MONO;
2570
2571 if (wm8994->aifclk[id] == 0) {
2572 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2573 return -EINVAL;
2574 }
2575
2576 /* AIFCLK/fs ratio; look for a close match in either direction */
2577 best = 0;
2578 best_val = abs((fs_ratios[0] * params_rate(params))
2579 - wm8994->aifclk[id]);
2580 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2581 cur_val = abs((fs_ratios[i] * params_rate(params))
2582 - wm8994->aifclk[id]);
2583 if (cur_val >= best_val)
2584 continue;
2585 best = i;
2586 best_val = cur_val;
2587 }
2588 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2589 dai->id, fs_ratios[best]);
2590 rate_val |= best;
2591
2592 /* We may not get quite the right frequency if using
2593 * approximate clocks so look for the closest match that is
2594 * higher than the target (we need to ensure that there enough
2595 * BCLKs to clock out the samples).
2596 */
2597 best = 0;
2598 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2599 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2600 if (cur_val < 0) /* BCLK table is sorted */
2601 break;
2602 best = i;
2603 }
2604 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2605 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2606 bclk_divs[best], bclk_rate);
2607 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2608
2609 lrclk = bclk_rate / params_rate(params);
2610 if (!lrclk) {
2611 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2612 bclk_rate);
2613 return -EINVAL;
2614 }
2615 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2616 lrclk, bclk_rate / lrclk);
2617
2618 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2619 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2620 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2621 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2622 lrclk);
2623 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2624 WM8994_AIF1CLK_RATE_MASK, rate_val);
2625
2626 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2627 switch (dai->id) {
2628 case 1:
2629 wm8994->dac_rates[0] = params_rate(params);
2630 wm8994_set_retune_mobile(codec, 0);
2631 wm8994_set_retune_mobile(codec, 1);
2632 break;
2633 case 2:
2634 wm8994->dac_rates[1] = params_rate(params);
2635 wm8994_set_retune_mobile(codec, 2);
2636 break;
2637 }
2638 }
2639
2640 return 0;
2641 }
2642
2643 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2644 struct snd_pcm_hw_params *params,
2645 struct snd_soc_dai *dai)
2646 {
2647 struct snd_soc_codec *codec = dai->codec;
2648 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2649 struct wm8994 *control = wm8994->wm8994;
2650 int aif1_reg;
2651 int aif1 = 0;
2652
2653 switch (dai->id) {
2654 case 3:
2655 switch (control->type) {
2656 case WM1811:
2657 case WM8958:
2658 aif1_reg = WM8958_AIF3_CONTROL_1;
2659 break;
2660 default:
2661 return 0;
2662 }
2663 default:
2664 return 0;
2665 }
2666
2667 switch (params_format(params)) {
2668 case SNDRV_PCM_FORMAT_S16_LE:
2669 break;
2670 case SNDRV_PCM_FORMAT_S20_3LE:
2671 aif1 |= 0x20;
2672 break;
2673 case SNDRV_PCM_FORMAT_S24_LE:
2674 aif1 |= 0x40;
2675 break;
2676 case SNDRV_PCM_FORMAT_S32_LE:
2677 aif1 |= 0x60;
2678 break;
2679 default:
2680 return -EINVAL;
2681 }
2682
2683 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2684 }
2685
2686 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2687 struct snd_soc_dai *dai)
2688 {
2689 struct snd_soc_codec *codec = dai->codec;
2690 int rate_reg = 0;
2691
2692 switch (dai->id) {
2693 case 1:
2694 rate_reg = WM8994_AIF1_RATE;
2695 break;
2696 case 2:
2697 rate_reg = WM8994_AIF2_RATE;
2698 break;
2699 default:
2700 break;
2701 }
2702
2703 /* If the DAI is idle then configure the divider tree for the
2704 * lowest output rate to save a little power if the clock is
2705 * still active (eg, because it is system clock).
2706 */
2707 if (rate_reg && !dai->playback_active && !dai->capture_active)
2708 snd_soc_update_bits(codec, rate_reg,
2709 WM8994_AIF1_SR_MASK |
2710 WM8994_AIF1CLK_RATE_MASK, 0x9);
2711 }
2712
2713 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2714 {
2715 struct snd_soc_codec *codec = codec_dai->codec;
2716 int mute_reg;
2717 int reg;
2718
2719 switch (codec_dai->id) {
2720 case 1:
2721 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2722 break;
2723 case 2:
2724 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2725 break;
2726 default:
2727 return -EINVAL;
2728 }
2729
2730 if (mute)
2731 reg = WM8994_AIF1DAC1_MUTE;
2732 else
2733 reg = 0;
2734
2735 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2736
2737 return 0;
2738 }
2739
2740 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2741 {
2742 struct snd_soc_codec *codec = codec_dai->codec;
2743 int reg, val, mask;
2744
2745 switch (codec_dai->id) {
2746 case 1:
2747 reg = WM8994_AIF1_MASTER_SLAVE;
2748 mask = WM8994_AIF1_TRI;
2749 break;
2750 case 2:
2751 reg = WM8994_AIF2_MASTER_SLAVE;
2752 mask = WM8994_AIF2_TRI;
2753 break;
2754 case 3:
2755 reg = WM8994_POWER_MANAGEMENT_6;
2756 mask = WM8994_AIF3_TRI;
2757 break;
2758 default:
2759 return -EINVAL;
2760 }
2761
2762 if (tristate)
2763 val = mask;
2764 else
2765 val = 0;
2766
2767 return snd_soc_update_bits(codec, reg, mask, val);
2768 }
2769
2770 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2771 {
2772 struct snd_soc_codec *codec = dai->codec;
2773
2774 /* Disable the pulls on the AIF if we're using it to save power. */
2775 snd_soc_update_bits(codec, WM8994_GPIO_3,
2776 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2777 snd_soc_update_bits(codec, WM8994_GPIO_4,
2778 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2779 snd_soc_update_bits(codec, WM8994_GPIO_5,
2780 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2781
2782 return 0;
2783 }
2784
2785 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2786
2787 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2788 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2789
2790 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2791 .set_sysclk = wm8994_set_dai_sysclk,
2792 .set_fmt = wm8994_set_dai_fmt,
2793 .hw_params = wm8994_hw_params,
2794 .shutdown = wm8994_aif_shutdown,
2795 .digital_mute = wm8994_aif_mute,
2796 .set_pll = wm8994_set_fll,
2797 .set_tristate = wm8994_set_tristate,
2798 };
2799
2800 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2801 .set_sysclk = wm8994_set_dai_sysclk,
2802 .set_fmt = wm8994_set_dai_fmt,
2803 .hw_params = wm8994_hw_params,
2804 .shutdown = wm8994_aif_shutdown,
2805 .digital_mute = wm8994_aif_mute,
2806 .set_pll = wm8994_set_fll,
2807 .set_tristate = wm8994_set_tristate,
2808 };
2809
2810 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2811 .hw_params = wm8994_aif3_hw_params,
2812 .set_tristate = wm8994_set_tristate,
2813 };
2814
2815 static struct snd_soc_dai_driver wm8994_dai[] = {
2816 {
2817 .name = "wm8994-aif1",
2818 .id = 1,
2819 .playback = {
2820 .stream_name = "AIF1 Playback",
2821 .channels_min = 1,
2822 .channels_max = 2,
2823 .rates = WM8994_RATES,
2824 .formats = WM8994_FORMATS,
2825 },
2826 .capture = {
2827 .stream_name = "AIF1 Capture",
2828 .channels_min = 1,
2829 .channels_max = 2,
2830 .rates = WM8994_RATES,
2831 .formats = WM8994_FORMATS,
2832 },
2833 .ops = &wm8994_aif1_dai_ops,
2834 },
2835 {
2836 .name = "wm8994-aif2",
2837 .id = 2,
2838 .playback = {
2839 .stream_name = "AIF2 Playback",
2840 .channels_min = 1,
2841 .channels_max = 2,
2842 .rates = WM8994_RATES,
2843 .formats = WM8994_FORMATS,
2844 },
2845 .capture = {
2846 .stream_name = "AIF2 Capture",
2847 .channels_min = 1,
2848 .channels_max = 2,
2849 .rates = WM8994_RATES,
2850 .formats = WM8994_FORMATS,
2851 },
2852 .probe = wm8994_aif2_probe,
2853 .ops = &wm8994_aif2_dai_ops,
2854 },
2855 {
2856 .name = "wm8994-aif3",
2857 .id = 3,
2858 .playback = {
2859 .stream_name = "AIF3 Playback",
2860 .channels_min = 1,
2861 .channels_max = 2,
2862 .rates = WM8994_RATES,
2863 .formats = WM8994_FORMATS,
2864 },
2865 .capture = {
2866 .stream_name = "AIF3 Capture",
2867 .channels_min = 1,
2868 .channels_max = 2,
2869 .rates = WM8994_RATES,
2870 .formats = WM8994_FORMATS,
2871 },
2872 .ops = &wm8994_aif3_dai_ops,
2873 }
2874 };
2875
2876 #ifdef CONFIG_PM
2877 static int wm8994_suspend(struct snd_soc_codec *codec)
2878 {
2879 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2880 struct wm8994 *control = wm8994->wm8994;
2881 int i, ret;
2882
2883 switch (control->type) {
2884 case WM8994:
2885 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2886 break;
2887 case WM1811:
2888 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2889 WM1811_JACKDET_MODE_MASK, 0);
2890 /* Fall through */
2891 case WM8958:
2892 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2893 WM8958_MICD_ENA, 0);
2894 break;
2895 }
2896
2897 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2898 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2899 sizeof(struct wm8994_fll_config));
2900 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2901 if (ret < 0)
2902 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2903 i + 1, ret);
2904 }
2905
2906 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2907
2908 return 0;
2909 }
2910
2911 static int wm8994_resume(struct snd_soc_codec *codec)
2912 {
2913 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2914 struct wm8994 *control = wm8994->wm8994;
2915 int i, ret;
2916 unsigned int val, mask;
2917
2918 if (wm8994->revision < 4) {
2919 /* force a HW read */
2920 ret = regmap_read(control->regmap,
2921 WM8994_POWER_MANAGEMENT_5, &val);
2922
2923 /* modify the cache only */
2924 codec->cache_only = 1;
2925 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2926 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2927 val &= mask;
2928 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2929 mask, val);
2930 codec->cache_only = 0;
2931 }
2932
2933 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2934
2935 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2936 if (!wm8994->fll_suspend[i].out)
2937 continue;
2938
2939 ret = _wm8994_set_fll(codec, i + 1,
2940 wm8994->fll_suspend[i].src,
2941 wm8994->fll_suspend[i].in,
2942 wm8994->fll_suspend[i].out);
2943 if (ret < 0)
2944 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2945 i + 1, ret);
2946 }
2947
2948 switch (control->type) {
2949 case WM8994:
2950 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2951 snd_soc_update_bits(codec, WM8994_MICBIAS,
2952 WM8994_MICD_ENA, WM8994_MICD_ENA);
2953 break;
2954 case WM1811:
2955 if (wm8994->jackdet && wm8994->jack_cb) {
2956 /* Restart from idle */
2957 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2958 WM1811_JACKDET_MODE_MASK,
2959 WM1811_JACKDET_MODE_JACK);
2960 break;
2961 }
2962 case WM8958:
2963 if (wm8994->jack_cb)
2964 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2965 WM8958_MICD_ENA, WM8958_MICD_ENA);
2966 break;
2967 }
2968
2969 return 0;
2970 }
2971 #else
2972 #define wm8994_suspend NULL
2973 #define wm8994_resume NULL
2974 #endif
2975
2976 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2977 {
2978 struct snd_soc_codec *codec = wm8994->codec;
2979 struct wm8994_pdata *pdata = wm8994->pdata;
2980 struct snd_kcontrol_new controls[] = {
2981 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2982 wm8994->retune_mobile_enum,
2983 wm8994_get_retune_mobile_enum,
2984 wm8994_put_retune_mobile_enum),
2985 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2986 wm8994->retune_mobile_enum,
2987 wm8994_get_retune_mobile_enum,
2988 wm8994_put_retune_mobile_enum),
2989 SOC_ENUM_EXT("AIF2 EQ Mode",
2990 wm8994->retune_mobile_enum,
2991 wm8994_get_retune_mobile_enum,
2992 wm8994_put_retune_mobile_enum),
2993 };
2994 int ret, i, j;
2995 const char **t;
2996
2997 /* We need an array of texts for the enum API but the number
2998 * of texts is likely to be less than the number of
2999 * configurations due to the sample rate dependency of the
3000 * configurations. */
3001 wm8994->num_retune_mobile_texts = 0;
3002 wm8994->retune_mobile_texts = NULL;
3003 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3004 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3005 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3006 wm8994->retune_mobile_texts[j]) == 0)
3007 break;
3008 }
3009
3010 if (j != wm8994->num_retune_mobile_texts)
3011 continue;
3012
3013 /* Expand the array... */
3014 t = krealloc(wm8994->retune_mobile_texts,
3015 sizeof(char *) *
3016 (wm8994->num_retune_mobile_texts + 1),
3017 GFP_KERNEL);
3018 if (t == NULL)
3019 continue;
3020
3021 /* ...store the new entry... */
3022 t[wm8994->num_retune_mobile_texts] =
3023 pdata->retune_mobile_cfgs[i].name;
3024
3025 /* ...and remember the new version. */
3026 wm8994->num_retune_mobile_texts++;
3027 wm8994->retune_mobile_texts = t;
3028 }
3029
3030 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3031 wm8994->num_retune_mobile_texts);
3032
3033 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3034 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3035
3036 ret = snd_soc_add_controls(wm8994->codec, controls,
3037 ARRAY_SIZE(controls));
3038 if (ret != 0)
3039 dev_err(wm8994->codec->dev,
3040 "Failed to add ReTune Mobile controls: %d\n", ret);
3041 }
3042
3043 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3044 {
3045 struct snd_soc_codec *codec = wm8994->codec;
3046 struct wm8994_pdata *pdata = wm8994->pdata;
3047 int ret, i;
3048
3049 if (!pdata)
3050 return;
3051
3052 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3053 pdata->lineout2_diff,
3054 pdata->lineout1fb,
3055 pdata->lineout2fb,
3056 pdata->jd_scthr,
3057 pdata->jd_thr,
3058 pdata->micbias1_lvl,
3059 pdata->micbias2_lvl);
3060
3061 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3062
3063 if (pdata->num_drc_cfgs) {
3064 struct snd_kcontrol_new controls[] = {
3065 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3066 wm8994_get_drc_enum, wm8994_put_drc_enum),
3067 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3068 wm8994_get_drc_enum, wm8994_put_drc_enum),
3069 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3070 wm8994_get_drc_enum, wm8994_put_drc_enum),
3071 };
3072
3073 /* We need an array of texts for the enum API */
3074 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3075 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3076 if (!wm8994->drc_texts) {
3077 dev_err(wm8994->codec->dev,
3078 "Failed to allocate %d DRC config texts\n",
3079 pdata->num_drc_cfgs);
3080 return;
3081 }
3082
3083 for (i = 0; i < pdata->num_drc_cfgs; i++)
3084 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3085
3086 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3087 wm8994->drc_enum.texts = wm8994->drc_texts;
3088
3089 ret = snd_soc_add_controls(wm8994->codec, controls,
3090 ARRAY_SIZE(controls));
3091 if (ret != 0)
3092 dev_err(wm8994->codec->dev,
3093 "Failed to add DRC mode controls: %d\n", ret);
3094
3095 for (i = 0; i < WM8994_NUM_DRC; i++)
3096 wm8994_set_drc(codec, i);
3097 }
3098
3099 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3100 pdata->num_retune_mobile_cfgs);
3101
3102 if (pdata->num_retune_mobile_cfgs)
3103 wm8994_handle_retune_mobile_pdata(wm8994);
3104 else
3105 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
3106 ARRAY_SIZE(wm8994_eq_controls));
3107
3108 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3109 if (pdata->micbias[i]) {
3110 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3111 pdata->micbias[i] & 0xffff);
3112 }
3113 }
3114 }
3115
3116 /**
3117 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3118 *
3119 * @codec: WM8994 codec
3120 * @jack: jack to report detection events on
3121 * @micbias: microphone bias to detect on
3122 * @det: value to report for presence detection
3123 * @shrt: value to report for short detection
3124 *
3125 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3126 * being used to bring out signals to the processor then only platform
3127 * data configuration is needed for WM8994 and processor GPIOs should
3128 * be configured using snd_soc_jack_add_gpios() instead.
3129 *
3130 * Configuration of detection levels is available via the micbias1_lvl
3131 * and micbias2_lvl platform data members.
3132 */
3133 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3134 int micbias, int det, int shrt)
3135 {
3136 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3137 struct wm8994_micdet *micdet;
3138 struct wm8994 *control = wm8994->wm8994;
3139 int reg;
3140
3141 if (control->type != WM8994)
3142 return -EINVAL;
3143
3144 switch (micbias) {
3145 case 1:
3146 micdet = &wm8994->micdet[0];
3147 break;
3148 case 2:
3149 micdet = &wm8994->micdet[1];
3150 break;
3151 default:
3152 return -EINVAL;
3153 }
3154
3155 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
3156 micbias, det, shrt);
3157
3158 /* Store the configuration */
3159 micdet->jack = jack;
3160 micdet->det = det;
3161 micdet->shrt = shrt;
3162
3163 /* If either of the jacks is set up then enable detection */
3164 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3165 reg = WM8994_MICD_ENA;
3166 else
3167 reg = 0;
3168
3169 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3170
3171 return 0;
3172 }
3173 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3174
3175 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3176 {
3177 struct wm8994_priv *priv = data;
3178 struct snd_soc_codec *codec = priv->codec;
3179 int reg;
3180 int report;
3181
3182 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3183 trace_snd_soc_jack_irq(dev_name(codec->dev));
3184 #endif
3185
3186 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3187 if (reg < 0) {
3188 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3189 reg);
3190 return IRQ_HANDLED;
3191 }
3192
3193 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3194
3195 report = 0;
3196 if (reg & WM8994_MIC1_DET_STS)
3197 report |= priv->micdet[0].det;
3198 if (reg & WM8994_MIC1_SHRT_STS)
3199 report |= priv->micdet[0].shrt;
3200 snd_soc_jack_report(priv->micdet[0].jack, report,
3201 priv->micdet[0].det | priv->micdet[0].shrt);
3202
3203 report = 0;
3204 if (reg & WM8994_MIC2_DET_STS)
3205 report |= priv->micdet[1].det;
3206 if (reg & WM8994_MIC2_SHRT_STS)
3207 report |= priv->micdet[1].shrt;
3208 snd_soc_jack_report(priv->micdet[1].jack, report,
3209 priv->micdet[1].det | priv->micdet[1].shrt);
3210
3211 return IRQ_HANDLED;
3212 }
3213
3214 /* Default microphone detection handler for WM8958 - the user can
3215 * override this if they wish.
3216 */
3217 static void wm8958_default_micdet(u16 status, void *data)
3218 {
3219 struct snd_soc_codec *codec = data;
3220 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3221 int report;
3222
3223 dev_dbg(codec->dev, "MICDET %x\n", status);
3224
3225 /* Either nothing present or just starting detection */
3226 if (!(status & WM8958_MICD_STS)) {
3227 if (!wm8994->jackdet) {
3228 /* If nothing present then clear our statuses */
3229 dev_dbg(codec->dev, "Detected open circuit\n");
3230 wm8994->jack_mic = false;
3231 wm8994->mic_detecting = true;
3232
3233 wm8958_micd_set_rate(codec);
3234
3235 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3236 wm8994->btn_mask |
3237 SND_JACK_HEADSET);
3238 }
3239 return;
3240 }
3241
3242 /* If the measurement is showing a high impedence we've got a
3243 * microphone.
3244 */
3245 if (wm8994->mic_detecting && (status & 0x600)) {
3246 dev_dbg(codec->dev, "Detected microphone\n");
3247
3248 wm8994->mic_detecting = false;
3249 wm8994->jack_mic = true;
3250
3251 wm8958_micd_set_rate(codec);
3252
3253 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3254 SND_JACK_HEADSET);
3255 }
3256
3257
3258 if (wm8994->mic_detecting && status & 0x4) {
3259 dev_dbg(codec->dev, "Detected headphone\n");
3260 wm8994->mic_detecting = false;
3261
3262 wm8958_micd_set_rate(codec);
3263
3264 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3265 SND_JACK_HEADSET);
3266
3267 /* If we have jackdet that will detect removal */
3268 if (wm8994->jackdet) {
3269 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3270 WM8958_MICD_ENA, 0);
3271
3272 wm1811_jackdet_set_mode(codec,
3273 WM1811_JACKDET_MODE_JACK);
3274 }
3275 }
3276
3277 /* Report short circuit as a button */
3278 if (wm8994->jack_mic) {
3279 report = 0;
3280 if (status & 0x4)
3281 report |= SND_JACK_BTN_0;
3282
3283 if (status & 0x8)
3284 report |= SND_JACK_BTN_1;
3285
3286 if (status & 0x10)
3287 report |= SND_JACK_BTN_2;
3288
3289 if (status & 0x20)
3290 report |= SND_JACK_BTN_3;
3291
3292 if (status & 0x40)
3293 report |= SND_JACK_BTN_4;
3294
3295 if (status & 0x80)
3296 report |= SND_JACK_BTN_5;
3297
3298 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3299 wm8994->btn_mask);
3300 }
3301 }
3302
3303 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3304 {
3305 struct wm8994_priv *wm8994 = data;
3306 struct snd_soc_codec *codec = wm8994->codec;
3307 int reg;
3308
3309 mutex_lock(&wm8994->accdet_lock);
3310
3311 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3312 if (reg < 0) {
3313 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3314 mutex_unlock(&wm8994->accdet_lock);
3315 return IRQ_NONE;
3316 }
3317
3318 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3319
3320 if (reg & WM1811_JACKDET_LVL) {
3321 dev_dbg(codec->dev, "Jack detected\n");
3322
3323 snd_soc_jack_report(wm8994->micdet[0].jack,
3324 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3325
3326 /*
3327 * Start off measument of microphone impedence to find
3328 * out what's actually there.
3329 */
3330 wm8994->mic_detecting = true;
3331 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3332 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3333 WM8958_MICD_ENA, WM8958_MICD_ENA);
3334 } else {
3335 dev_dbg(codec->dev, "Jack not detected\n");
3336
3337 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3338 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3339 wm8994->btn_mask);
3340
3341 wm8994->mic_detecting = false;
3342 wm8994->jack_mic = false;
3343 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3344 WM8958_MICD_ENA, 0);
3345 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3346 }
3347
3348 mutex_unlock(&wm8994->accdet_lock);
3349
3350 return IRQ_HANDLED;
3351 }
3352
3353 /**
3354 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3355 *
3356 * @codec: WM8958 codec
3357 * @jack: jack to report detection events on
3358 *
3359 * Enable microphone detection functionality for the WM8958. By
3360 * default simple detection which supports the detection of up to 6
3361 * buttons plus video and microphone functionality is supported.
3362 *
3363 * The WM8958 has an advanced jack detection facility which is able to
3364 * support complex accessory detection, especially when used in
3365 * conjunction with external circuitry. In order to provide maximum
3366 * flexiblity a callback is provided which allows a completely custom
3367 * detection algorithm.
3368 */
3369 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3370 wm8958_micdet_cb cb, void *cb_data)
3371 {
3372 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3373 struct wm8994 *control = wm8994->wm8994;
3374 u16 micd_lvl_sel;
3375
3376 switch (control->type) {
3377 case WM1811:
3378 case WM8958:
3379 break;
3380 default:
3381 return -EINVAL;
3382 }
3383
3384 if (jack) {
3385 if (!cb) {
3386 dev_dbg(codec->dev, "Using default micdet callback\n");
3387 cb = wm8958_default_micdet;
3388 cb_data = codec;
3389 }
3390
3391 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3392
3393 wm8994->micdet[0].jack = jack;
3394 wm8994->jack_cb = cb;
3395 wm8994->jack_cb_data = cb_data;
3396
3397 wm8994->mic_detecting = true;
3398 wm8994->jack_mic = false;
3399
3400 wm8958_micd_set_rate(codec);
3401
3402 /* Detect microphones and short circuits by default */
3403 if (wm8994->pdata->micd_lvl_sel)
3404 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3405 else
3406 micd_lvl_sel = 0x41;
3407
3408 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3409 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3410 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3411
3412 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3413 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3414
3415 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3416
3417 /*
3418 * If we can use jack detection start off with that,
3419 * otherwise jump straight to microphone detection.
3420 */
3421 if (wm8994->jackdet) {
3422 snd_soc_update_bits(codec, WM8994_LDO_1,
3423 WM8994_LDO1_DISCH, 0);
3424 wm1811_jackdet_set_mode(codec,
3425 WM1811_JACKDET_MODE_JACK);
3426 } else {
3427 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3428 WM8958_MICD_ENA, WM8958_MICD_ENA);
3429 }
3430
3431 } else {
3432 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3433 WM8958_MICD_ENA, 0);
3434 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3435 }
3436
3437 return 0;
3438 }
3439 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3440
3441 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3442 {
3443 struct wm8994_priv *wm8994 = data;
3444 struct snd_soc_codec *codec = wm8994->codec;
3445 int reg, count;
3446
3447 mutex_lock(&wm8994->accdet_lock);
3448
3449 /*
3450 * Jack detection may have detected a removal simulataneously
3451 * with an update of the MICDET status; if so it will have
3452 * stopped detection and we can ignore this interrupt.
3453 */
3454 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3455 mutex_unlock(&wm8994->accdet_lock);
3456 return IRQ_HANDLED;
3457 }
3458
3459 /* We may occasionally read a detection without an impedence
3460 * range being provided - if that happens loop again.
3461 */
3462 count = 10;
3463 do {
3464 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3465 if (reg < 0) {
3466 mutex_unlock(&wm8994->accdet_lock);
3467 dev_err(codec->dev,
3468 "Failed to read mic detect status: %d\n",
3469 reg);
3470 return IRQ_NONE;
3471 }
3472
3473 if (!(reg & WM8958_MICD_VALID)) {
3474 dev_dbg(codec->dev, "Mic detect data not valid\n");
3475 goto out;
3476 }
3477
3478 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3479 break;
3480
3481 msleep(1);
3482 } while (count--);
3483
3484 if (count == 0)
3485 dev_warn(codec->dev, "No impedence range reported for jack\n");
3486
3487 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3488 trace_snd_soc_jack_irq(dev_name(codec->dev));
3489 #endif
3490
3491 if (wm8994->jack_cb)
3492 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3493 else
3494 dev_warn(codec->dev, "Accessory detection with no callback\n");
3495
3496 out:
3497 mutex_unlock(&wm8994->accdet_lock);
3498
3499 return IRQ_HANDLED;
3500 }
3501
3502 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3503 {
3504 struct snd_soc_codec *codec = data;
3505
3506 dev_err(codec->dev, "FIFO error\n");
3507
3508 return IRQ_HANDLED;
3509 }
3510
3511 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3512 {
3513 struct snd_soc_codec *codec = data;
3514
3515 dev_err(codec->dev, "Thermal warning\n");
3516
3517 return IRQ_HANDLED;
3518 }
3519
3520 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3521 {
3522 struct snd_soc_codec *codec = data;
3523
3524 dev_crit(codec->dev, "Thermal shutdown\n");
3525
3526 return IRQ_HANDLED;
3527 }
3528
3529 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3530 {
3531 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3532 struct wm8994_priv *wm8994;
3533 struct snd_soc_dapm_context *dapm = &codec->dapm;
3534 unsigned int reg;
3535 int ret, i;
3536
3537 codec->control_data = control->regmap;
3538
3539 wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3540 GFP_KERNEL);
3541 if (wm8994 == NULL)
3542 return -ENOMEM;
3543 snd_soc_codec_set_drvdata(codec, wm8994);
3544
3545 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3546
3547 wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
3548 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3549 wm8994->codec = codec;
3550
3551 mutex_init(&wm8994->accdet_lock);
3552
3553 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3554 init_completion(&wm8994->fll_locked[i]);
3555
3556 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3557 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3558 else if (wm8994->pdata && wm8994->pdata->irq_base)
3559 wm8994->micdet_irq = wm8994->pdata->irq_base +
3560 WM8994_IRQ_MIC1_DET;
3561
3562 pm_runtime_enable(codec->dev);
3563 pm_runtime_resume(codec->dev);
3564
3565 /* Set revision-specific configuration */
3566 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3567 switch (control->type) {
3568 case WM8994:
3569 switch (wm8994->revision) {
3570 case 2:
3571 case 3:
3572 wm8994->hubs.dcs_codes_l = -5;
3573 wm8994->hubs.dcs_codes_r = -5;
3574 wm8994->hubs.hp_startup_mode = 1;
3575 wm8994->hubs.dcs_readback_mode = 1;
3576 wm8994->hubs.series_startup = 1;
3577 break;
3578 default:
3579 wm8994->hubs.dcs_readback_mode = 2;
3580 break;
3581 }
3582 break;
3583
3584 case WM8958:
3585 wm8994->hubs.dcs_readback_mode = 1;
3586 break;
3587
3588 case WM1811:
3589 wm8994->hubs.dcs_readback_mode = 2;
3590 wm8994->hubs.no_series_update = 1;
3591
3592 switch (wm8994->revision) {
3593 case 0:
3594 case 1:
3595 case 2:
3596 case 3:
3597 wm8994->hubs.dcs_codes_l = -9;
3598 wm8994->hubs.dcs_codes_r = -7;
3599 break;
3600 default:
3601 break;
3602 }
3603
3604 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3605 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3606 break;
3607
3608 default:
3609 break;
3610 }
3611
3612 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3613 wm8994_fifo_error, "FIFO error", codec);
3614 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3615 wm8994_temp_warn, "Thermal warning", codec);
3616 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3617 wm8994_temp_shut, "Thermal shutdown", codec);
3618
3619 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3620 wm_hubs_dcs_done, "DC servo done",
3621 &wm8994->hubs);
3622 if (ret == 0)
3623 wm8994->hubs.dcs_done_irq = true;
3624
3625 switch (control->type) {
3626 case WM8994:
3627 if (wm8994->micdet_irq) {
3628 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3629 wm8994_mic_irq,
3630 IRQF_TRIGGER_RISING,
3631 "Mic1 detect",
3632 wm8994);
3633 if (ret != 0)
3634 dev_warn(codec->dev,
3635 "Failed to request Mic1 detect IRQ: %d\n",
3636 ret);
3637 }
3638
3639 ret = wm8994_request_irq(wm8994->wm8994,
3640 WM8994_IRQ_MIC1_SHRT,
3641 wm8994_mic_irq, "Mic 1 short",
3642 wm8994);
3643 if (ret != 0)
3644 dev_warn(codec->dev,
3645 "Failed to request Mic1 short IRQ: %d\n",
3646 ret);
3647
3648 ret = wm8994_request_irq(wm8994->wm8994,
3649 WM8994_IRQ_MIC2_DET,
3650 wm8994_mic_irq, "Mic 2 detect",
3651 wm8994);
3652 if (ret != 0)
3653 dev_warn(codec->dev,
3654 "Failed to request Mic2 detect IRQ: %d\n",
3655 ret);
3656
3657 ret = wm8994_request_irq(wm8994->wm8994,
3658 WM8994_IRQ_MIC2_SHRT,
3659 wm8994_mic_irq, "Mic 2 short",
3660 wm8994);
3661 if (ret != 0)
3662 dev_warn(codec->dev,
3663 "Failed to request Mic2 short IRQ: %d\n",
3664 ret);
3665 break;
3666
3667 case WM8958:
3668 case WM1811:
3669 if (wm8994->micdet_irq) {
3670 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3671 wm8958_mic_irq,
3672 IRQF_TRIGGER_RISING,
3673 "Mic detect",
3674 wm8994);
3675 if (ret != 0)
3676 dev_warn(codec->dev,
3677 "Failed to request Mic detect IRQ: %d\n",
3678 ret);
3679 }
3680 }
3681
3682 switch (control->type) {
3683 case WM1811:
3684 if (wm8994->revision > 1) {
3685 ret = wm8994_request_irq(wm8994->wm8994,
3686 WM8994_IRQ_GPIO(6),
3687 wm1811_jackdet_irq, "JACKDET",
3688 wm8994);
3689 if (ret == 0)
3690 wm8994->jackdet = true;
3691 }
3692 break;
3693 default:
3694 break;
3695 }
3696
3697 wm8994->fll_locked_irq = true;
3698 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3699 ret = wm8994_request_irq(wm8994->wm8994,
3700 WM8994_IRQ_FLL1_LOCK + i,
3701 wm8994_fll_locked_irq, "FLL lock",
3702 &wm8994->fll_locked[i]);
3703 if (ret != 0)
3704 wm8994->fll_locked_irq = false;
3705 }
3706
3707 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3708 * configured on init - if a system wants to do this dynamically
3709 * at runtime we can deal with that then.
3710 */
3711 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3712 if (ret < 0) {
3713 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3714 goto err_irq;
3715 }
3716 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3717 wm8994->lrclk_shared[0] = 1;
3718 wm8994_dai[0].symmetric_rates = 1;
3719 } else {
3720 wm8994->lrclk_shared[0] = 0;
3721 }
3722
3723 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3724 if (ret < 0) {
3725 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3726 goto err_irq;
3727 }
3728 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3729 wm8994->lrclk_shared[1] = 1;
3730 wm8994_dai[1].symmetric_rates = 1;
3731 } else {
3732 wm8994->lrclk_shared[1] = 0;
3733 }
3734
3735 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3736
3737 /* Latch volume updates (right only; we always do left then right). */
3738 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3739 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3740 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3741 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3742 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3743 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3744 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3745 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3746 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3747 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3748 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3749 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3750 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3751 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3752 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3753 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3754 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3755 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3756 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3757 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3758 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3759 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3760 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3761 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3762 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3763 WM8994_DAC1_VU, WM8994_DAC1_VU);
3764 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3765 WM8994_DAC1_VU, WM8994_DAC1_VU);
3766 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3767 WM8994_DAC2_VU, WM8994_DAC2_VU);
3768 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3769 WM8994_DAC2_VU, WM8994_DAC2_VU);
3770
3771 /* Set the low bit of the 3D stereo depth so TLV matches */
3772 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3773 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3774 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3775 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3776 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3777 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3778 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3779 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3780 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3781
3782 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3783 * use this; it only affects behaviour on idle TDM clock
3784 * cycles. */
3785 switch (control->type) {
3786 case WM8994:
3787 case WM8958:
3788 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3789 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3790 break;
3791 default:
3792 break;
3793 }
3794
3795 /* Put MICBIAS into bypass mode by default on newer devices */
3796 switch (control->type) {
3797 case WM8958:
3798 case WM1811:
3799 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3800 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3801 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3802 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3803 break;
3804 default:
3805 break;
3806 }
3807
3808 wm8994_update_class_w(codec);
3809
3810 wm8994_handle_pdata(wm8994);
3811
3812 wm_hubs_add_analogue_controls(codec);
3813 snd_soc_add_controls(codec, wm8994_snd_controls,
3814 ARRAY_SIZE(wm8994_snd_controls));
3815 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3816 ARRAY_SIZE(wm8994_dapm_widgets));
3817
3818 switch (control->type) {
3819 case WM8994:
3820 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3821 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3822 if (wm8994->revision < 4) {
3823 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3824 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3825 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3826 ARRAY_SIZE(wm8994_adc_revd_widgets));
3827 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3828 ARRAY_SIZE(wm8994_dac_revd_widgets));
3829 } else {
3830 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3831 ARRAY_SIZE(wm8994_lateclk_widgets));
3832 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3833 ARRAY_SIZE(wm8994_adc_widgets));
3834 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3835 ARRAY_SIZE(wm8994_dac_widgets));
3836 }
3837 break;
3838 case WM8958:
3839 snd_soc_add_controls(codec, wm8958_snd_controls,
3840 ARRAY_SIZE(wm8958_snd_controls));
3841 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3842 ARRAY_SIZE(wm8958_dapm_widgets));
3843 if (wm8994->revision < 1) {
3844 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3845 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3846 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3847 ARRAY_SIZE(wm8994_adc_revd_widgets));
3848 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3849 ARRAY_SIZE(wm8994_dac_revd_widgets));
3850 } else {
3851 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3852 ARRAY_SIZE(wm8994_lateclk_widgets));
3853 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3854 ARRAY_SIZE(wm8994_adc_widgets));
3855 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3856 ARRAY_SIZE(wm8994_dac_widgets));
3857 }
3858 break;
3859
3860 case WM1811:
3861 snd_soc_add_controls(codec, wm8958_snd_controls,
3862 ARRAY_SIZE(wm8958_snd_controls));
3863 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3864 ARRAY_SIZE(wm8958_dapm_widgets));
3865 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3866 ARRAY_SIZE(wm8994_lateclk_widgets));
3867 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3868 ARRAY_SIZE(wm8994_adc_widgets));
3869 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3870 ARRAY_SIZE(wm8994_dac_widgets));
3871 break;
3872 }
3873
3874
3875 wm_hubs_add_analogue_routes(codec, 0, 0);
3876 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3877
3878 switch (control->type) {
3879 case WM8994:
3880 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3881 ARRAY_SIZE(wm8994_intercon));
3882
3883 if (wm8994->revision < 4) {
3884 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3885 ARRAY_SIZE(wm8994_revd_intercon));
3886 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3887 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3888 } else {
3889 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3890 ARRAY_SIZE(wm8994_lateclk_intercon));
3891 }
3892 break;
3893 case WM8958:
3894 if (wm8994->revision < 1) {
3895 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3896 ARRAY_SIZE(wm8994_revd_intercon));
3897 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3898 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3899 } else {
3900 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3901 ARRAY_SIZE(wm8994_lateclk_intercon));
3902 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3903 ARRAY_SIZE(wm8958_intercon));
3904 }
3905
3906 wm8958_dsp2_init(codec);
3907 break;
3908 case WM1811:
3909 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3910 ARRAY_SIZE(wm8994_lateclk_intercon));
3911 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3912 ARRAY_SIZE(wm8958_intercon));
3913 break;
3914 }
3915
3916 return 0;
3917
3918 err_irq:
3919 if (wm8994->jackdet)
3920 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3921 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3922 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3923 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3924 if (wm8994->micdet_irq)
3925 free_irq(wm8994->micdet_irq, wm8994);
3926 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3927 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3928 &wm8994->fll_locked[i]);
3929 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3930 &wm8994->hubs);
3931 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3932 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3933 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3934
3935 return ret;
3936 }
3937
3938 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3939 {
3940 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3941 struct wm8994 *control = wm8994->wm8994;
3942 int i;
3943
3944 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3945
3946 pm_runtime_disable(codec->dev);
3947
3948 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3949 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3950 &wm8994->fll_locked[i]);
3951
3952 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3953 &wm8994->hubs);
3954 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3955 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3956 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3957
3958 if (wm8994->jackdet)
3959 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3960
3961 switch (control->type) {
3962 case WM8994:
3963 if (wm8994->micdet_irq)
3964 free_irq(wm8994->micdet_irq, wm8994);
3965 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3966 wm8994);
3967 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3968 wm8994);
3969 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3970 wm8994);
3971 break;
3972
3973 case WM1811:
3974 case WM8958:
3975 if (wm8994->micdet_irq)
3976 free_irq(wm8994->micdet_irq, wm8994);
3977 break;
3978 }
3979 if (wm8994->mbc)
3980 release_firmware(wm8994->mbc);
3981 if (wm8994->mbc_vss)
3982 release_firmware(wm8994->mbc_vss);
3983 if (wm8994->enh_eq)
3984 release_firmware(wm8994->enh_eq);
3985 kfree(wm8994->retune_mobile_texts);
3986
3987 return 0;
3988 }
3989
3990 static int wm8994_soc_volatile(struct snd_soc_codec *codec,
3991 unsigned int reg)
3992 {
3993 return true;
3994 }
3995
3996 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3997 .probe = wm8994_codec_probe,
3998 .remove = wm8994_codec_remove,
3999 .suspend = wm8994_suspend,
4000 .resume = wm8994_resume,
4001 .set_bias_level = wm8994_set_bias_level,
4002 .reg_cache_size = WM8994_MAX_REGISTER,
4003 .volatile_register = wm8994_soc_volatile,
4004 };
4005
4006 static int __devinit wm8994_probe(struct platform_device *pdev)
4007 {
4008 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4009 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4010 }
4011
4012 static int __devexit wm8994_remove(struct platform_device *pdev)
4013 {
4014 snd_soc_unregister_codec(&pdev->dev);
4015 return 0;
4016 }
4017
4018 static struct platform_driver wm8994_codec_driver = {
4019 .driver = {
4020 .name = "wm8994-codec",
4021 .owner = THIS_MODULE,
4022 },
4023 .probe = wm8994_probe,
4024 .remove = __devexit_p(wm8994_remove),
4025 };
4026
4027 module_platform_driver(wm8994_codec_driver);
4028
4029 MODULE_DESCRIPTION("ASoC WM8994 driver");
4030 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4031 MODULE_LICENSE("GPL");
4032 MODULE_ALIAS("platform:wm8994-codec");