include/linux/mmc/dw_mmc.h

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #ifndef LINUX_MMC_DW_MMC_H
  15 #define LINUX_MMC_DW_MMC_H
  16
  17 #define MAX_MCI_SLOTS   2
  18
  19 enum dw_mci_state {
  20         STATE_IDLE = 0,
  21         STATE_SENDING_CMD,
  22         STATE_SENDING_DATA,
  23         STATE_DATA_BUSY,
  24         STATE_SENDING_STOP,
  25         STATE_DATA_ERROR,
  26 };
  27
  28 enum {
  29         EVENT_CMD_COMPLETE = 0,
  30         EVENT_XFER_COMPLETE,
  31         EVENT_DATA_COMPLETE,
  32         EVENT_DATA_ERROR,
  33         EVENT_XFER_ERROR
  34 };
  35
  36 struct mmc_data;
  37
  38 /**
  39  * struct dw_mci - MMC controller state shared between all slots
  40  * @lock: Spinlock protecting the queue and associated data.
  41  * @regs: Pointer to MMIO registers.
  42  * @sg: Scatterlist entry currently being processed by PIO code, if any.
  43  * @pio_offset: Offset into the current scatterlist entry.
  44  * @cur_slot: The slot which is currently using the controller.
  45  * @mrq: The request currently being processed on @cur_slot,
  46  *      or NULL if the controller is idle.
  47  * @cmd: The command currently being sent to the card, or NULL.
  48  * @data: The data currently being transferred, or NULL if no data
  49  *      transfer is in progress.
  50  * @use_dma: Whether DMA channel is initialized or not.
  51  * @using_dma: Whether DMA is in use for the current transfer.
  52  * @sg_dma: Bus address of DMA buffer.
  53  * @sg_cpu: Virtual address of DMA buffer.
  54  * @dma_ops: Pointer to platform-specific DMA callbacks.
  55  * @cmd_status: Snapshot of SR taken upon completion of the current
  56  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
  57  * @data_status: Snapshot of SR taken upon completion of the current
  58  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
  59  *      EVENT_DATA_ERROR is pending.
  60  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
  61  *      to be sent.
  62  * @dir_status: Direction of current transfer.
  63  * @tasklet: Tasklet running the request state machine.
  64  * @card_tasklet: Tasklet handling card detect.
  65  * @pending_events: Bitmask of events flagged by the interrupt handler
  66  *      to be processed by the tasklet.
  67  * @completed_events: Bitmask of events which the state machine has
  68  *      processed.
  69  * @state: Tasklet state.
  70  * @queue: List of slots waiting for access to the controller.
  71  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
  72  *      rate and timeout calculations.
  73  * @current_speed: Configured rate of the controller.
  74  * @num_slots: Number of slots available.
  75  * @pdev: Platform device associated with the MMC controller.
  76  * @pdata: Platform data associated with the MMC controller.
  77  * @slot: Slots sharing this MMC controller.
  78  * @fifo_depth: depth of FIFO.
  79  * @data_shift: log2 of FIFO item size.
  80  * @part_buf_start: Start index in part_buf.
  81  * @part_buf_count: Bytes of partial data in part_buf.
  82  * @part_buf: Simple buffer for partial fifo reads/writes.
  83  * @push_data: Pointer to FIFO push function.
  84  * @pull_data: Pointer to FIFO pull function.
  85  * @quirks: Set of quirks that apply to specific versions of the IP.
  86  *
  87  * Locking
  88  * =======
  89  *
  90  * @lock is a softirq-safe spinlock protecting @queue as well as
  91  * @cur_slot, @mrq and @state. These must always be updated
  92  * at the same time while holding @lock.
  93  *
  94  * The @mrq field of struct dw_mci_slot is also protected by @lock,
  95  * and must always be written at the same time as the slot is added to
  96  * @queue.
  97  *
  98  * @pending_events and @completed_events are accessed using atomic bit
  99  * operations, so they don't need any locking.
 100  *
 101  * None of the fields touched by the interrupt handler need any
 102  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 103  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 104  * interrupts must be disabled and @data_status updated with a
 105  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 106  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 107  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 108  * bytes_xfered field of @data must be written. This is ensured by
 109  * using barriers.
 110  */
 111 struct dw_mci {
 112         spinlock_t              lock;
 113         void __iomem            *regs;
 114
 115         struct scatterlist      *sg;
 116         unsigned int            pio_offset;
 117
 118         struct dw_mci_slot      *cur_slot;
 119         struct mmc_request      *mrq;
 120         struct mmc_command      *cmd;
 121         struct mmc_data         *data;
 122
 123         /* DMA interface members*/
 124         int                     use_dma;
 125         int                     using_dma;
 126
 127         dma_addr_t              sg_dma;
 128         void                    *sg_cpu;
 129         struct dw_mci_dma_ops   *dma_ops;
 130 #ifdef CONFIG_MMC_DW_IDMAC
 131         unsigned int            ring_size;
 132 #else
 133         struct dw_mci_dma_data  *dma_data;
 134 #endif
 135         u32                     cmd_status;
 136         u32                     data_status;
 137         u32                     stop_cmdr;
 138         u32                     dir_status;
 139         struct tasklet_struct   tasklet;
 140         struct work_struct      card_work;
 141         unsigned long           pending_events;
 142         unsigned long           completed_events;
 143         enum dw_mci_state       state;
 144         struct list_head        queue;
 145
 146         u32                     bus_hz;
 147         u32                     current_speed;
 148         u32                     num_slots;
 149         u32                     fifoth_val;
 150         struct platform_device  *pdev;
 151         struct dw_mci_board     *pdata;
 152         struct dw_mci_slot      *slot[MAX_MCI_SLOTS];
 153
 154         /* FIFO push and pull */
 155         int                     fifo_depth;
 156         int                     data_shift;
 157         u8                      part_buf_start;
 158         u8                      part_buf_count;
 159         union {
 160                 u16             part_buf16;
 161                 u32             part_buf32;
 162                 u64             part_buf;
 163         };
 164         void (*push_data)(struct dw_mci *host, void *buf, int cnt);
 165         void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
 166
 167         /* Workaround flags */
 168         u32                     quirks;
 169
 170         struct regulator        *vmmc;  /* Power regulator */
 171 };
 172
 173 /* DMA ops for Internal/External DMAC interface */
 174 struct dw_mci_dma_ops {
 175         /* DMA Ops */
 176         int (*init)(struct dw_mci *host);
 177         void (*start)(struct dw_mci *host, unsigned int sg_len);
 178         void (*complete)(struct dw_mci *host);
 179         void (*stop)(struct dw_mci *host);
 180         void (*cleanup)(struct dw_mci *host);
 181         void (*exit)(struct dw_mci *host);
 182 };
 183
 184 /* IP Quirks/flags. */
 185 /* DTO fix for command transmission with IDMAC configured */
 186 #define DW_MCI_QUIRK_IDMAC_DTO                  BIT(0)
 187 /* delay needed between retries on some 2.11a implementations */
 188 #define DW_MCI_QUIRK_RETRY_DELAY                BIT(1)
 189 /* High Speed Capable - Supports HS cards (up to 50MHz) */
 190 #define DW_MCI_QUIRK_HIGHSPEED                  BIT(2)
 191 /* Unreliable card detection */
 192 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION      BIT(3)
 193
 194
 195 struct dma_pdata;
 196
 197 struct block_settings {
 198         unsigned short  max_segs;       /* see blk_queue_max_segments */
 199         unsigned int    max_blk_size;   /* maximum size of one mmc block */
 200         unsigned int    max_blk_count;  /* maximum number of blocks in one req*/
 201         unsigned int    max_req_size;   /* maximum number of bytes in one req*/
 202         unsigned int    max_seg_size;   /* see blk_queue_max_segment_size */
 203 };
 204
 205 /* Board platform data */
 206 struct dw_mci_board {
 207         u32 num_slots;
 208
 209         u32 quirks; /* Workaround / Quirk flags */
 210         unsigned int bus_hz; /* Bus speed */
 211
 212         unsigned int caps;      /* Capabilities */
 213         /*
 214          * Override fifo depth. If 0, autodetect it from the FIFOTH register,
 215          * but note that this may not be reliable after a bootloader has used
 216          * it.
 217          */
 218         unsigned int fifo_depth;
 219
 220         /* delay in mS before detecting cards after interrupt */
 221         u32 detect_delay_ms;
 222
 223         int (*init)(u32 slot_id, irq_handler_t , void *);
 224         int (*get_ro)(u32 slot_id);
 225         int (*get_cd)(u32 slot_id);
 226         int (*get_ocr)(u32 slot_id);
 227         int (*get_bus_wd)(u32 slot_id);
 228         /*
 229          * Enable power to selected slot and set voltage to desired level.
 230          * Voltage levels are specified using MMC_VDD_xxx defines defined
 231          * in linux/mmc/host.h file.
 232          */
 233         void (*setpower)(u32 slot_id, u32 volt);
 234         void (*exit)(u32 slot_id);
 235         void (*select_slot)(u32 slot_id);
 236
 237         struct dw_mci_dma_ops *dma_ops;
 238         struct dma_pdata *data;
 239         struct block_settings *blk_settings;
 240 };
 241
 242 #endif /* LINUX_MMC_DW_MMC_H */