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QE/FHCI: fixed the CONTROL bug
[zen-stable.git] / drivers / pci / setup-bus.c
blob784da9d3602985606d850d9d07f51b65f21e3f05
1 /*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12 /*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
28 #include "pci.h"
29
30 struct resource_list_x {
31 struct resource_list_x *next;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
36 resource_size_t add_size;
37 resource_size_t min_align;
38 unsigned long flags;
39 };
40
41 #define free_list(type, head) do { \
42 struct type *list, *tmp; \
43 for (list = (head)->next; list;) { \
44 tmp = list; \
45 list = list->next; \
46 kfree(tmp); \
47 } \
48 (head)->next = NULL; \
49 } while (0)
50
51 int pci_realloc_enable = 0;
52 #define pci_realloc_enabled() pci_realloc_enable
53 void pci_realloc(void)
54 {
55 pci_realloc_enable = 1;
56 }
57
58 /**
59 * add_to_list() - add a new resource tracker to the list
60 * @head: Head of the list
61 * @dev: device corresponding to which the resource
62 * belongs
63 * @res: The resource to be tracked
64 * @add_size: additional size to be optionally added
65 * to the resource
66 */
67 static void add_to_list(struct resource_list_x *head,
68 struct pci_dev *dev, struct resource *res,
69 resource_size_t add_size, resource_size_t min_align)
70 {
71 struct resource_list_x *list = head;
72 struct resource_list_x *ln = list->next;
73 struct resource_list_x *tmp;
74
75 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
76 if (!tmp) {
77 pr_warning("add_to_list: kmalloc() failed!\n");
78 return;
79 }
80
81 tmp->next = ln;
82 tmp->res = res;
83 tmp->dev = dev;
84 tmp->start = res->start;
85 tmp->end = res->end;
86 tmp->flags = res->flags;
87 tmp->add_size = add_size;
88 tmp->min_align = min_align;
89 list->next = tmp;
90 }
91
92 static void add_to_failed_list(struct resource_list_x *head,
93 struct pci_dev *dev, struct resource *res)
94 {
95 add_to_list(head, dev, res,
96 0 /* dont care */,
97 0 /* dont care */);
98 }
99
100 static void __dev_sort_resources(struct pci_dev *dev,
101 struct resource_list *head)
102 {
103 u16 class = dev->class >> 8;
104
105 /* Don't touch classless devices or host bridges or ioapics. */
106 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
107 return;
108
109 /* Don't touch ioapic devices already enabled by firmware */
110 if (class == PCI_CLASS_SYSTEM_PIC) {
111 u16 command;
112 pci_read_config_word(dev, PCI_COMMAND, &command);
113 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
114 return;
115 }
116
117 pdev_sort_resources(dev, head);
118 }
119
120 static inline void reset_resource(struct resource *res)
121 {
122 res->start = 0;
123 res->end = 0;
124 res->flags = 0;
125 }
126
127 /**
128 * reassign_resources_sorted() - satisfy any additional resource requests
129 *
130 * @realloc_head : head of the list tracking requests requiring additional
131 * resources
132 * @head : head of the list tracking requests with allocated
133 * resources
134 *
135 * Walk through each element of the realloc_head and try to procure
136 * additional resources for the element, provided the element
137 * is in the head list.
138 */
139 static void reassign_resources_sorted(struct resource_list_x *realloc_head,
140 struct resource_list *head)
141 {
142 struct resource *res;
143 struct resource_list_x *list, *tmp, *prev;
144 struct resource_list *hlist;
145 resource_size_t add_size;
146 int idx;
147
148 prev = realloc_head;
149 for (list = realloc_head->next; list;) {
150 res = list->res;
151 /* skip resource that has been reset */
152 if (!res->flags)
153 goto out;
154
155 /* skip this resource if not found in head list */
156 for (hlist = head->next; hlist && hlist->res != res;
157 hlist = hlist->next);
158 if (!hlist) { /* just skip */
159 prev = list;
160 list = list->next;
161 continue;
162 }
163
164 idx = res - &list->dev->resource[0];
165 add_size=list->add_size;
166 if (!resource_size(res)) {
167 res->start = list->start;
168 res->end = res->start + add_size - 1;
169 if(pci_assign_resource(list->dev, idx))
170 reset_resource(res);
171 } else {
172 resource_size_t align = list->min_align;
173 res->flags |= list->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
174 if (pci_reassign_resource(list->dev, idx, add_size, align))
175 dev_printk(KERN_DEBUG, &list->dev->dev, "failed to add optional resources res=%pR\n",
176 res);
177 }
178 out:
179 tmp = list;
180 prev->next = list = list->next;
181 kfree(tmp);
182 }
183 }
184
185 /**
186 * assign_requested_resources_sorted() - satisfy resource requests
187 *
188 * @head : head of the list tracking requests for resources
189 * @failed_list : head of the list tracking requests that could
190 * not be allocated
191 *
192 * Satisfy resource requests of each element in the list. Add
193 * requests that could not satisfied to the failed_list.
194 */
195 static void assign_requested_resources_sorted(struct resource_list *head,
196 struct resource_list_x *fail_head)
197 {
198 struct resource *res;
199 struct resource_list *list;
200 int idx;
201
202 for (list = head->next; list; list = list->next) {
203 res = list->res;
204 idx = res - &list->dev->resource[0];
205 if (resource_size(res) && pci_assign_resource(list->dev, idx)) {
206 if (fail_head && !pci_is_root_bus(list->dev->bus)) {
207 /*
208 * if the failed res is for ROM BAR, and it will
209 * be enabled later, don't add it to the list
210 */
211 if (!((idx == PCI_ROM_RESOURCE) &&
212 (!(res->flags & IORESOURCE_ROM_ENABLE))))
213 add_to_failed_list(fail_head, list->dev, res);
214 }
215 reset_resource(res);
216 }
217 }
218 }
219
220 static void __assign_resources_sorted(struct resource_list *head,
221 struct resource_list_x *realloc_head,
222 struct resource_list_x *fail_head)
223 {
224 /* Satisfy the must-have resource requests */
225 assign_requested_resources_sorted(head, fail_head);
226
227 /* Try to satisfy any additional optional resource
228 requests */
229 if (realloc_head)
230 reassign_resources_sorted(realloc_head, head);
231 free_list(resource_list, head);
232 }
233
234 static void pdev_assign_resources_sorted(struct pci_dev *dev,
235 struct resource_list_x *fail_head)
236 {
237 struct resource_list head;
238
239 head.next = NULL;
240 __dev_sort_resources(dev, &head);
241 __assign_resources_sorted(&head, NULL, fail_head);
242
243 }
244
245 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
246 struct resource_list_x *realloc_head,
247 struct resource_list_x *fail_head)
248 {
249 struct pci_dev *dev;
250 struct resource_list head;
251
252 head.next = NULL;
253 list_for_each_entry(dev, &bus->devices, bus_list)
254 __dev_sort_resources(dev, &head);
255
256 __assign_resources_sorted(&head, realloc_head, fail_head);
257 }
258
259 void pci_setup_cardbus(struct pci_bus *bus)
260 {
261 struct pci_dev *bridge = bus->self;
262 struct resource *res;
263 struct pci_bus_region region;
264
265 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
266 bus->secondary, bus->subordinate);
267
268 res = bus->resource[0];
269 pcibios_resource_to_bus(bridge, &region, res);
270 if (res->flags & IORESOURCE_IO) {
271 /*
272 * The IO resource is allocated a range twice as large as it
273 * would normally need. This allows us to set both IO regs.
274 */
275 dev_info(&bridge->dev, " bridge window %pR\n", res);
276 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
277 region.start);
278 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
279 region.end);
280 }
281
282 res = bus->resource[1];
283 pcibios_resource_to_bus(bridge, &region, res);
284 if (res->flags & IORESOURCE_IO) {
285 dev_info(&bridge->dev, " bridge window %pR\n", res);
286 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
287 region.start);
288 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
289 region.end);
290 }
291
292 res = bus->resource[2];
293 pcibios_resource_to_bus(bridge, &region, res);
294 if (res->flags & IORESOURCE_MEM) {
295 dev_info(&bridge->dev, " bridge window %pR\n", res);
296 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
297 region.start);
298 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
299 region.end);
300 }
301
302 res = bus->resource[3];
303 pcibios_resource_to_bus(bridge, &region, res);
304 if (res->flags & IORESOURCE_MEM) {
305 dev_info(&bridge->dev, " bridge window %pR\n", res);
306 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
307 region.start);
308 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
309 region.end);
310 }
311 }
312 EXPORT_SYMBOL(pci_setup_cardbus);
313
314 /* Initialize bridges with base/limit values we have collected.
315 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
316 requires that if there is no I/O ports or memory behind the
317 bridge, corresponding range must be turned off by writing base
318 value greater than limit to the bridge's base/limit registers.
319
320 Note: care must be taken when updating I/O base/limit registers
321 of bridges which support 32-bit I/O. This update requires two
322 config space writes, so it's quite possible that an I/O window of
323 the bridge will have some undesirable address (e.g. 0) after the
324 first write. Ditto 64-bit prefetchable MMIO. */
325 static void pci_setup_bridge_io(struct pci_bus *bus)
326 {
327 struct pci_dev *bridge = bus->self;
328 struct resource *res;
329 struct pci_bus_region region;
330 u32 l, io_upper16;
331
332 /* Set up the top and bottom of the PCI I/O segment for this bus. */
333 res = bus->resource[0];
334 pcibios_resource_to_bus(bridge, &region, res);
335 if (res->flags & IORESOURCE_IO) {
336 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
337 l &= 0xffff0000;
338 l |= (region.start >> 8) & 0x00f0;
339 l |= region.end & 0xf000;
340 /* Set up upper 16 bits of I/O base/limit. */
341 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
342 dev_info(&bridge->dev, " bridge window %pR\n", res);
343 } else {
344 /* Clear upper 16 bits of I/O base/limit. */
345 io_upper16 = 0;
346 l = 0x00f0;
347 }
348 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
349 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
350 /* Update lower 16 bits of I/O base/limit. */
351 pci_write_config_dword(bridge, PCI_IO_BASE, l);
352 /* Update upper 16 bits of I/O base/limit. */
353 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
354 }
355
356 static void pci_setup_bridge_mmio(struct pci_bus *bus)
357 {
358 struct pci_dev *bridge = bus->self;
359 struct resource *res;
360 struct pci_bus_region region;
361 u32 l;
362
363 /* Set up the top and bottom of the PCI Memory segment for this bus. */
364 res = bus->resource[1];
365 pcibios_resource_to_bus(bridge, &region, res);
366 if (res->flags & IORESOURCE_MEM) {
367 l = (region.start >> 16) & 0xfff0;
368 l |= region.end & 0xfff00000;
369 dev_info(&bridge->dev, " bridge window %pR\n", res);
370 } else {
371 l = 0x0000fff0;
372 }
373 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
374 }
375
376 static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
377 {
378 struct pci_dev *bridge = bus->self;
379 struct resource *res;
380 struct pci_bus_region region;
381 u32 l, bu, lu;
382
383 /* Clear out the upper 32 bits of PREF limit.
384 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
385 disables PREF range, which is ok. */
386 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
387
388 /* Set up PREF base/limit. */
389 bu = lu = 0;
390 res = bus->resource[2];
391 pcibios_resource_to_bus(bridge, &region, res);
392 if (res->flags & IORESOURCE_PREFETCH) {
393 l = (region.start >> 16) & 0xfff0;
394 l |= region.end & 0xfff00000;
395 if (res->flags & IORESOURCE_MEM_64) {
396 bu = upper_32_bits(region.start);
397 lu = upper_32_bits(region.end);
398 }
399 dev_info(&bridge->dev, " bridge window %pR\n", res);
400 } else {
401 l = 0x0000fff0;
402 }
403 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
404
405 /* Set the upper 32 bits of PREF base & limit. */
406 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
407 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
408 }
409
410 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
411 {
412 struct pci_dev *bridge = bus->self;
413
414 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
415 bus->secondary, bus->subordinate);
416
417 if (type & IORESOURCE_IO)
418 pci_setup_bridge_io(bus);
419
420 if (type & IORESOURCE_MEM)
421 pci_setup_bridge_mmio(bus);
422
423 if (type & IORESOURCE_PREFETCH)
424 pci_setup_bridge_mmio_pref(bus);
425
426 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
427 }
428
429 static void pci_setup_bridge(struct pci_bus *bus)
430 {
431 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
432 IORESOURCE_PREFETCH;
433
434 __pci_setup_bridge(bus, type);
435 }
436
437 /* Check whether the bridge supports optional I/O and
438 prefetchable memory ranges. If not, the respective
439 base/limit registers must be read-only and read as 0. */
440 static void pci_bridge_check_ranges(struct pci_bus *bus)
441 {
442 u16 io;
443 u32 pmem;
444 struct pci_dev *bridge = bus->self;
445 struct resource *b_res;
446
447 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
448 b_res[1].flags |= IORESOURCE_MEM;
449
450 pci_read_config_word(bridge, PCI_IO_BASE, &io);
451 if (!io) {
452 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
453 pci_read_config_word(bridge, PCI_IO_BASE, &io);
454 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
455 }
456 if (io)
457 b_res[0].flags |= IORESOURCE_IO;
458 /* DECchip 21050 pass 2 errata: the bridge may miss an address
459 disconnect boundary by one PCI data phase.
460 Workaround: do not use prefetching on this device. */
461 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
462 return;
463 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
464 if (!pmem) {
465 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
466 0xfff0fff0);
467 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
468 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
469 }
470 if (pmem) {
471 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
472 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
473 PCI_PREF_RANGE_TYPE_64) {
474 b_res[2].flags |= IORESOURCE_MEM_64;
475 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
476 }
477 }
478
479 /* double check if bridge does support 64 bit pref */
480 if (b_res[2].flags & IORESOURCE_MEM_64) {
481 u32 mem_base_hi, tmp;
482 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
483 &mem_base_hi);
484 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
485 0xffffffff);
486 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
487 if (!tmp)
488 b_res[2].flags &= ~IORESOURCE_MEM_64;
489 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
490 mem_base_hi);
491 }
492 }
493
494 /* Helper function for sizing routines: find first available
495 bus resource of a given type. Note: we intentionally skip
496 the bus resources which have already been assigned (that is,
497 have non-NULL parent resource). */
498 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
499 {
500 int i;
501 struct resource *r;
502 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
503 IORESOURCE_PREFETCH;
504
505 pci_bus_for_each_resource(bus, r, i) {
506 if (r == &ioport_resource || r == &iomem_resource)
507 continue;
508 if (r && (r->flags & type_mask) == type && !r->parent)
509 return r;
510 }
511 return NULL;
512 }
513
514 static resource_size_t calculate_iosize(resource_size_t size,
515 resource_size_t min_size,
516 resource_size_t size1,
517 resource_size_t old_size,
518 resource_size_t align)
519 {
520 if (size < min_size)
521 size = min_size;
522 if (old_size == 1 )
523 old_size = 0;
524 /* To be fixed in 2.5: we should have sort of HAVE_ISA
525 flag in the struct pci_bus. */
526 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
527 size = (size & 0xff) + ((size & ~0xffUL) << 2);
528 #endif
529 size = ALIGN(size + size1, align);
530 if (size < old_size)
531 size = old_size;
532 return size;
533 }
534
535 static resource_size_t calculate_memsize(resource_size_t size,
536 resource_size_t min_size,
537 resource_size_t size1,
538 resource_size_t old_size,
539 resource_size_t align)
540 {
541 if (size < min_size)
542 size = min_size;
543 if (old_size == 1 )
544 old_size = 0;
545 if (size < old_size)
546 size = old_size;
547 size = ALIGN(size + size1, align);
548 return size;
549 }
550
551 static resource_size_t get_res_add_size(struct resource_list_x *realloc_head,
552 struct resource *res)
553 {
554 struct resource_list_x *list;
555
556 /* check if it is in realloc_head list */
557 for (list = realloc_head->next; list && list->res != res;
558 list = list->next);
559 if (list)
560 return list->add_size;
561
562 return 0;
563 }
564
565 /**
566 * pbus_size_io() - size the io window of a given bus
567 *
568 * @bus : the bus
569 * @min_size : the minimum io window that must to be allocated
570 * @add_size : additional optional io window
571 * @realloc_head : track the additional io window on this list
572 *
573 * Sizing the IO windows of the PCI-PCI bridge is trivial,
574 * since these windows have 4K granularity and the IO ranges
575 * of non-bridge PCI devices are limited to 256 bytes.
576 * We must be careful with the ISA aliasing though.
577 */
578 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
579 resource_size_t add_size, struct resource_list_x *realloc_head)
580 {
581 struct pci_dev *dev;
582 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
583 unsigned long size = 0, size0 = 0, size1 = 0;
584 resource_size_t children_add_size = 0;
585
586 if (!b_res)
587 return;
588
589 list_for_each_entry(dev, &bus->devices, bus_list) {
590 int i;
591
592 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
593 struct resource *r = &dev->resource[i];
594 unsigned long r_size;
595
596 if (r->parent || !(r->flags & IORESOURCE_IO))
597 continue;
598 r_size = resource_size(r);
599
600 if (r_size < 0x400)
601 /* Might be re-aligned for ISA */
602 size += r_size;
603 else
604 size1 += r_size;
605
606 if (realloc_head)
607 children_add_size += get_res_add_size(realloc_head, r);
608 }
609 }
610 size0 = calculate_iosize(size, min_size, size1,
611 resource_size(b_res), 4096);
612 if (children_add_size > add_size)
613 add_size = children_add_size;
614 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
615 calculate_iosize(size, min_size+add_size, size1,
616 resource_size(b_res), 4096);
617 if (!size0 && !size1) {
618 if (b_res->start || b_res->end)
619 dev_info(&bus->self->dev, "disabling bridge window "
620 "%pR to [bus %02x-%02x] (unused)\n", b_res,
621 bus->secondary, bus->subordinate);
622 b_res->flags = 0;
623 return;
624 }
625 /* Alignment of the IO window is always 4K */
626 b_res->start = 4096;
627 b_res->end = b_res->start + size0 - 1;
628 b_res->flags |= IORESOURCE_STARTALIGN;
629 if (size1 > size0 && realloc_head)
630 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
631 }
632
633 /**
634 * pbus_size_mem() - size the memory window of a given bus
635 *
636 * @bus : the bus
637 * @min_size : the minimum memory window that must to be allocated
638 * @add_size : additional optional memory window
639 * @realloc_head : track the additional memory window on this list
640 *
641 * Calculate the size of the bus and minimal alignment which
642 * guarantees that all child resources fit in this size.
643 */
644 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
645 unsigned long type, resource_size_t min_size,
646 resource_size_t add_size,
647 struct resource_list_x *realloc_head)
648 {
649 struct pci_dev *dev;
650 resource_size_t min_align, align, size, size0, size1;
651 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
652 int order, max_order;
653 struct resource *b_res = find_free_bus_resource(bus, type);
654 unsigned int mem64_mask = 0;
655 resource_size_t children_add_size = 0;
656
657 if (!b_res)
658 return 0;
659
660 memset(aligns, 0, sizeof(aligns));
661 max_order = 0;
662 size = 0;
663
664 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
665 b_res->flags &= ~IORESOURCE_MEM_64;
666
667 list_for_each_entry(dev, &bus->devices, bus_list) {
668 int i;
669
670 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
671 struct resource *r = &dev->resource[i];
672 resource_size_t r_size;
673
674 if (r->parent || (r->flags & mask) != type)
675 continue;
676 r_size = resource_size(r);
677 #ifdef CONFIG_PCI_IOV
678 /* put SRIOV requested res to the optional list */
679 if (realloc_head && i >= PCI_IOV_RESOURCES &&
680 i <= PCI_IOV_RESOURCE_END) {
681 r->end = r->start - 1;
682 add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
683 children_add_size += r_size;
684 continue;
685 }
686 #endif
687 /* For bridges size != alignment */
688 align = pci_resource_alignment(dev, r);
689 order = __ffs(align) - 20;
690 if (order > 11) {
691 dev_warn(&dev->dev, "disabling BAR %d: %pR "
692 "(bad alignment %#llx)\n", i, r,
693 (unsigned long long) align);
694 r->flags = 0;
695 continue;
696 }
697 size += r_size;
698 if (order < 0)
699 order = 0;
700 /* Exclude ranges with size > align from
701 calculation of the alignment. */
702 if (r_size == align)
703 aligns[order] += align;
704 if (order > max_order)
705 max_order = order;
706 mem64_mask &= r->flags & IORESOURCE_MEM_64;
707
708 if (realloc_head)
709 children_add_size += get_res_add_size(realloc_head, r);
710 }
711 }
712 align = 0;
713 min_align = 0;
714 for (order = 0; order <= max_order; order++) {
715 resource_size_t align1 = 1;
716
717 align1 <<= (order + 20);
718
719 if (!align)
720 min_align = align1;
721 else if (ALIGN(align + min_align, min_align) < align1)
722 min_align = align1 >> 1;
723 align += aligns[order];
724 }
725 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
726 if (children_add_size > add_size)
727 add_size = children_add_size;
728 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
729 calculate_memsize(size, min_size+add_size, 0,
730 resource_size(b_res), min_align);
731 if (!size0 && !size1) {
732 if (b_res->start || b_res->end)
733 dev_info(&bus->self->dev, "disabling bridge window "
734 "%pR to [bus %02x-%02x] (unused)\n", b_res,
735 bus->secondary, bus->subordinate);
736 b_res->flags = 0;
737 return 1;
738 }
739 b_res->start = min_align;
740 b_res->end = size0 + min_align - 1;
741 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
742 if (size1 > size0 && realloc_head)
743 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
744 return 1;
745 }
746
747 unsigned long pci_cardbus_resource_alignment(struct resource *res)
748 {
749 if (res->flags & IORESOURCE_IO)
750 return pci_cardbus_io_size;
751 if (res->flags & IORESOURCE_MEM)
752 return pci_cardbus_mem_size;
753 return 0;
754 }
755
756 static void pci_bus_size_cardbus(struct pci_bus *bus,
757 struct resource_list_x *realloc_head)
758 {
759 struct pci_dev *bridge = bus->self;
760 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
761 u16 ctrl;
762
763 /*
764 * Reserve some resources for CardBus. We reserve
765 * a fixed amount of bus space for CardBus bridges.
766 */
767 b_res[0].start = 0;
768 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
769 if (realloc_head)
770 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */);
771
772 b_res[1].start = 0;
773 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
774 if (realloc_head)
775 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */);
776
777 /*
778 * Check whether prefetchable memory is supported
779 * by this bridge.
780 */
781 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
782 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
783 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
784 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
785 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
786 }
787
788 /*
789 * If we have prefetchable memory support, allocate
790 * two regions. Otherwise, allocate one region of
791 * twice the size.
792 */
793 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
794 b_res[2].start = 0;
795 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
796 if (realloc_head)
797 add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */);
798
799 b_res[3].start = 0;
800 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
801 if (realloc_head)
802 add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */);
803 } else {
804 b_res[3].start = 0;
805 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
806 if (realloc_head)
807 add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */);
808 }
809
810 /* set the size of the resource to zero, so that the resource does not
811 * get assigned during required-resource allocation cycle but gets assigned
812 * during the optional-resource allocation cycle.
813 */
814 b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1;
815 b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0;
816 }
817
818 void __ref __pci_bus_size_bridges(struct pci_bus *bus,
819 struct resource_list_x *realloc_head)
820 {
821 struct pci_dev *dev;
822 unsigned long mask, prefmask;
823 resource_size_t additional_mem_size = 0, additional_io_size = 0;
824
825 list_for_each_entry(dev, &bus->devices, bus_list) {
826 struct pci_bus *b = dev->subordinate;
827 if (!b)
828 continue;
829
830 switch (dev->class >> 8) {
831 case PCI_CLASS_BRIDGE_CARDBUS:
832 pci_bus_size_cardbus(b, realloc_head);
833 break;
834
835 case PCI_CLASS_BRIDGE_PCI:
836 default:
837 __pci_bus_size_bridges(b, realloc_head);
838 break;
839 }
840 }
841
842 /* The root bus? */
843 if (!bus->self)
844 return;
845
846 switch (bus->self->class >> 8) {
847 case PCI_CLASS_BRIDGE_CARDBUS:
848 /* don't size cardbuses yet. */
849 break;
850
851 case PCI_CLASS_BRIDGE_PCI:
852 pci_bridge_check_ranges(bus);
853 if (bus->self->is_hotplug_bridge) {
854 additional_io_size = pci_hotplug_io_size;
855 additional_mem_size = pci_hotplug_mem_size;
856 }
857 /*
858 * Follow thru
859 */
860 default:
861 pbus_size_io(bus, 0, additional_io_size, realloc_head);
862 /* If the bridge supports prefetchable range, size it
863 separately. If it doesn't, or its prefetchable window
864 has already been allocated by arch code, try
865 non-prefetchable range for both types of PCI memory
866 resources. */
867 mask = IORESOURCE_MEM;
868 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
869 if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, realloc_head))
870 mask = prefmask; /* Success, size non-prefetch only. */
871 else
872 additional_mem_size += additional_mem_size;
873 pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, realloc_head);
874 break;
875 }
876 }
877
878 void __ref pci_bus_size_bridges(struct pci_bus *bus)
879 {
880 __pci_bus_size_bridges(bus, NULL);
881 }
882 EXPORT_SYMBOL(pci_bus_size_bridges);
883
884 static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
885 struct resource_list_x *realloc_head,
886 struct resource_list_x *fail_head)
887 {
888 struct pci_bus *b;
889 struct pci_dev *dev;
890
891 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
892
893 list_for_each_entry(dev, &bus->devices, bus_list) {
894 b = dev->subordinate;
895 if (!b)
896 continue;
897
898 __pci_bus_assign_resources(b, realloc_head, fail_head);
899
900 switch (dev->class >> 8) {
901 case PCI_CLASS_BRIDGE_PCI:
902 if (!pci_is_enabled(dev))
903 pci_setup_bridge(b);
904 break;
905
906 case PCI_CLASS_BRIDGE_CARDBUS:
907 pci_setup_cardbus(b);
908 break;
909
910 default:
911 dev_info(&dev->dev, "not setting up bridge for bus "
912 "%04x:%02x\n", pci_domain_nr(b), b->number);
913 break;
914 }
915 }
916 }
917
918 void __ref pci_bus_assign_resources(const struct pci_bus *bus)
919 {
920 __pci_bus_assign_resources(bus, NULL, NULL);
921 }
922 EXPORT_SYMBOL(pci_bus_assign_resources);
923
924 static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
925 struct resource_list_x *fail_head)
926 {
927 struct pci_bus *b;
928
929 pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
930
931 b = bridge->subordinate;
932 if (!b)
933 return;
934
935 __pci_bus_assign_resources(b, NULL, fail_head);
936
937 switch (bridge->class >> 8) {
938 case PCI_CLASS_BRIDGE_PCI:
939 pci_setup_bridge(b);
940 break;
941
942 case PCI_CLASS_BRIDGE_CARDBUS:
943 pci_setup_cardbus(b);
944 break;
945
946 default:
947 dev_info(&bridge->dev, "not setting up bridge for bus "
948 "%04x:%02x\n", pci_domain_nr(b), b->number);
949 break;
950 }
951 }
952 static void pci_bridge_release_resources(struct pci_bus *bus,
953 unsigned long type)
954 {
955 int idx;
956 bool changed = false;
957 struct pci_dev *dev;
958 struct resource *r;
959 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
960 IORESOURCE_PREFETCH;
961
962 dev = bus->self;
963 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
964 idx++) {
965 r = &dev->resource[idx];
966 if ((r->flags & type_mask) != type)
967 continue;
968 if (!r->parent)
969 continue;
970 /*
971 * if there are children under that, we should release them
972 * all
973 */
974 release_child_resources(r);
975 if (!release_resource(r)) {
976 dev_printk(KERN_DEBUG, &dev->dev,
977 "resource %d %pR released\n", idx, r);
978 /* keep the old size */
979 r->end = resource_size(r) - 1;
980 r->start = 0;
981 r->flags = 0;
982 changed = true;
983 }
984 }
985
986 if (changed) {
987 /* avoiding touch the one without PREF */
988 if (type & IORESOURCE_PREFETCH)
989 type = IORESOURCE_PREFETCH;
990 __pci_setup_bridge(bus, type);
991 }
992 }
993
994 enum release_type {
995 leaf_only,
996 whole_subtree,
997 };
998 /*
999 * try to release pci bridge resources that is from leaf bridge,
1000 * so we can allocate big new one later
1001 */
1002 static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1003 unsigned long type,
1004 enum release_type rel_type)
1005 {
1006 struct pci_dev *dev;
1007 bool is_leaf_bridge = true;
1008
1009 list_for_each_entry(dev, &bus->devices, bus_list) {
1010 struct pci_bus *b = dev->subordinate;
1011 if (!b)
1012 continue;
1013
1014 is_leaf_bridge = false;
1015
1016 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1017 continue;
1018
1019 if (rel_type == whole_subtree)
1020 pci_bus_release_bridge_resources(b, type,
1021 whole_subtree);
1022 }
1023
1024 if (pci_is_root_bus(bus))
1025 return;
1026
1027 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1028 return;
1029
1030 if ((rel_type == whole_subtree) || is_leaf_bridge)
1031 pci_bridge_release_resources(bus, type);
1032 }
1033
1034 static void pci_bus_dump_res(struct pci_bus *bus)
1035 {
1036 struct resource *res;
1037 int i;
1038
1039 pci_bus_for_each_resource(bus, res, i) {
1040 if (!res || !res->end || !res->flags)
1041 continue;
1042
1043 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1044 }
1045 }
1046
1047 static void pci_bus_dump_resources(struct pci_bus *bus)
1048 {
1049 struct pci_bus *b;
1050 struct pci_dev *dev;
1051
1052
1053 pci_bus_dump_res(bus);
1054
1055 list_for_each_entry(dev, &bus->devices, bus_list) {
1056 b = dev->subordinate;
1057 if (!b)
1058 continue;
1059
1060 pci_bus_dump_resources(b);
1061 }
1062 }
1063
1064 static int __init pci_bus_get_depth(struct pci_bus *bus)
1065 {
1066 int depth = 0;
1067 struct pci_dev *dev;
1068
1069 list_for_each_entry(dev, &bus->devices, bus_list) {
1070 int ret;
1071 struct pci_bus *b = dev->subordinate;
1072 if (!b)
1073 continue;
1074
1075 ret = pci_bus_get_depth(b);
1076 if (ret + 1 > depth)
1077 depth = ret + 1;
1078 }
1079
1080 return depth;
1081 }
1082 static int __init pci_get_max_depth(void)
1083 {
1084 int depth = 0;
1085 struct pci_bus *bus;
1086
1087 list_for_each_entry(bus, &pci_root_buses, node) {
1088 int ret;
1089
1090 ret = pci_bus_get_depth(bus);
1091 if (ret > depth)
1092 depth = ret;
1093 }
1094
1095 return depth;
1096 }
1097
1098
1099 /*
1100 * first try will not touch pci bridge res
1101 * second and later try will clear small leaf bridge res
1102 * will stop till to the max deepth if can not find good one
1103 */
1104 void __init
1105 pci_assign_unassigned_resources(void)
1106 {
1107 struct pci_bus *bus;
1108 struct resource_list_x realloc_list; /* list of resources that
1109 want additional resources */
1110 int tried_times = 0;
1111 enum release_type rel_type = leaf_only;
1112 struct resource_list_x head, *list;
1113 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1114 IORESOURCE_PREFETCH;
1115 unsigned long failed_type;
1116 int max_depth = pci_get_max_depth();
1117 int pci_try_num;
1118
1119
1120 head.next = NULL;
1121 realloc_list.next = NULL;
1122
1123 pci_try_num = max_depth + 1;
1124 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1125 max_depth, pci_try_num);
1126
1127 again:
1128 /* Depth first, calculate sizes and alignments of all
1129 subordinate buses. */
1130 list_for_each_entry(bus, &pci_root_buses, node)
1131 __pci_bus_size_bridges(bus, &realloc_list);
1132
1133 /* Depth last, allocate resources and update the hardware. */
1134 list_for_each_entry(bus, &pci_root_buses, node)
1135 __pci_bus_assign_resources(bus, &realloc_list, &head);
1136 BUG_ON(realloc_list.next);
1137 tried_times++;
1138
1139 /* any device complain? */
1140 if (!head.next)
1141 goto enable_and_dump;
1142
1143 /* don't realloc if asked to do so */
1144 if (!pci_realloc_enabled()) {
1145 free_list(resource_list_x, &head);
1146 goto enable_and_dump;
1147 }
1148
1149 failed_type = 0;
1150 for (list = head.next; list;) {
1151 failed_type |= list->flags;
1152 list = list->next;
1153 }
1154 /*
1155 * io port are tight, don't try extra
1156 * or if reach the limit, don't want to try more
1157 */
1158 failed_type &= type_mask;
1159 if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
1160 free_list(resource_list_x, &head);
1161 goto enable_and_dump;
1162 }
1163
1164 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1165 tried_times + 1);
1166
1167 /* third times and later will not check if it is leaf */
1168 if ((tried_times + 1) > 2)
1169 rel_type = whole_subtree;
1170
1171 /*
1172 * Try to release leaf bridge's resources that doesn't fit resource of
1173 * child device under that bridge
1174 */
1175 for (list = head.next; list;) {
1176 bus = list->dev->bus;
1177 pci_bus_release_bridge_resources(bus, list->flags & type_mask,
1178 rel_type);
1179 list = list->next;
1180 }
1181 /* restore size and flags */
1182 for (list = head.next; list;) {
1183 struct resource *res = list->res;
1184
1185 res->start = list->start;
1186 res->end = list->end;
1187 res->flags = list->flags;
1188 if (list->dev->subordinate)
1189 res->flags = 0;
1190
1191 list = list->next;
1192 }
1193 free_list(resource_list_x, &head);
1194
1195 goto again;
1196
1197 enable_and_dump:
1198 /* Depth last, update the hardware. */
1199 list_for_each_entry(bus, &pci_root_buses, node)
1200 pci_enable_bridges(bus);
1201
1202 /* dump the resource on buses */
1203 list_for_each_entry(bus, &pci_root_buses, node)
1204 pci_bus_dump_resources(bus);
1205 }
1206
1207 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1208 {
1209 struct pci_bus *parent = bridge->subordinate;
1210 int tried_times = 0;
1211 struct resource_list_x head, *list;
1212 int retval;
1213 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1214 IORESOURCE_PREFETCH;
1215
1216 head.next = NULL;
1217
1218 again:
1219 pci_bus_size_bridges(parent);
1220 __pci_bridge_assign_resources(bridge, &head);
1221
1222 tried_times++;
1223
1224 if (!head.next)
1225 goto enable_all;
1226
1227 if (tried_times >= 2) {
1228 /* still fail, don't need to try more */
1229 free_list(resource_list_x, &head);
1230 goto enable_all;
1231 }
1232
1233 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1234 tried_times + 1);
1235
1236 /*
1237 * Try to release leaf bridge's resources that doesn't fit resource of
1238 * child device under that bridge
1239 */
1240 for (list = head.next; list;) {
1241 struct pci_bus *bus = list->dev->bus;
1242 unsigned long flags = list->flags;
1243
1244 pci_bus_release_bridge_resources(bus, flags & type_mask,
1245 whole_subtree);
1246 list = list->next;
1247 }
1248 /* restore size and flags */
1249 for (list = head.next; list;) {
1250 struct resource *res = list->res;
1251
1252 res->start = list->start;
1253 res->end = list->end;
1254 res->flags = list->flags;
1255 if (list->dev->subordinate)
1256 res->flags = 0;
1257
1258 list = list->next;
1259 }
1260 free_list(resource_list_x, &head);
1261
1262 goto again;
1263
1264 enable_all:
1265 retval = pci_reenable_device(bridge);
1266 pci_set_master(bridge);
1267 pci_enable_bridges(parent);
1268 }
1269 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);