drivers/scsi/mpt2sas/mpi/mpi2.h

   1 /*
   2  *  Copyright (c) 2000-2010 LSI Corporation.
   3  *
   4  *
   5  *           Name:  mpi2.h
   6  *          Title:  MPI Message independent structures and definitions
   7  *                  including System Interface Register Set and
   8  *                  scatter/gather formats.
   9  *  Creation Date:  June 21, 2006
  10  *
  11  *  mpi2.h Version:  02.00.17
  12  *
  13  *  Version History
  14  *  ---------------
  15  *
  16  *  Date      Version   Description
  17  *  --------  --------  ------------------------------------------------------
  18  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  19  *  06-04-07  02.00.01  Bumped MPI2_HEADER_VERSION_UNIT.
  20  *  06-26-07  02.00.02  Bumped MPI2_HEADER_VERSION_UNIT.
  21  *  08-31-07  02.00.03  Bumped MPI2_HEADER_VERSION_UNIT.
  22  *                      Moved ReplyPostHostIndex register to offset 0x6C of the
  23  *                      MPI2_SYSTEM_INTERFACE_REGS and modified the define for
  24  *                      MPI2_REPLY_POST_HOST_INDEX_OFFSET.
  25  *                      Added union of request descriptors.
  26  *                      Added union of reply descriptors.
  27  *  10-31-07  02.00.04  Bumped MPI2_HEADER_VERSION_UNIT.
  28  *                      Added define for MPI2_VERSION_02_00.
  29  *                      Fixed the size of the FunctionDependent5 field in the
  30  *                      MPI2_DEFAULT_REPLY structure.
  31  *  12-18-07  02.00.05  Bumped MPI2_HEADER_VERSION_UNIT.
  32  *                      Removed the MPI-defined Fault Codes and extended the
  33  *                      product specific codes up to 0xEFFF.
  34  *                      Added a sixth key value for the WriteSequence register
  35  *                      and changed the flush value to 0x0.
  36  *                      Added message function codes for Diagnostic Buffer Post
  37  *                      and Diagnsotic Release.
  38  *                      New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
  39  *                      Moved MPI2_VERSION_UNION from mpi2_ioc.h.
  40  *  02-29-08  02.00.06  Bumped MPI2_HEADER_VERSION_UNIT.
  41  *  03-03-08  02.00.07  Bumped MPI2_HEADER_VERSION_UNIT.
  42  *  05-21-08  02.00.08  Bumped MPI2_HEADER_VERSION_UNIT.
  43  *                      Added #defines for marking a reply descriptor as unused.
  44  *  06-27-08  02.00.09  Bumped MPI2_HEADER_VERSION_UNIT.
  45  *  10-02-08  02.00.10  Bumped MPI2_HEADER_VERSION_UNIT.
  46  *                      Moved LUN field defines from mpi2_init.h.
  47  *  01-19-09  02.00.11  Bumped MPI2_HEADER_VERSION_UNIT.
  48  *  05-06-09  02.00.12  Bumped MPI2_HEADER_VERSION_UNIT.
  49  *                      In all request and reply descriptors, replaced VF_ID
  50  *                      field with MSIxIndex field.
  51  *                      Removed DevHandle field from
  52  *                      MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
  53  *                      bytes reserved.
  54  *                      Added RAID Accelerator functionality.
  55  *  07-30-09  02.00.13  Bumped MPI2_HEADER_VERSION_UNIT.
  56  *  10-28-09  02.00.14  Bumped MPI2_HEADER_VERSION_UNIT.
  57  *                      Added MSI-x index mask and shift for Reply Post Host
  58  *                      Index register.
  59  *                      Added function code for Host Based Discovery Action.
  60  *  02-10-10  02.00.15  Bumped MPI2_HEADER_VERSION_UNIT.
  61  *                      Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
  62  *                      Added defines for product-specific range of message
  63  *                      function codes, 0xF0 to 0xFF.
  64  *  05-12-10  02.00.16  Bumped MPI2_HEADER_VERSION_UNIT.
  65  *                      Added alternative defines for the SGE Direction bit.
  66  *  08-11-10  02.00.17  Bumped MPI2_HEADER_VERSION_UNIT.
  67  *  --------------------------------------------------------------------------
  68  */
  69
  70 #ifndef MPI2_H
  71 #define MPI2_H
  72
  73
  74 /*****************************************************************************
  75 *
  76 *        MPI Version Definitions
  77 *
  78 *****************************************************************************/
  79
  80 #define MPI2_VERSION_MAJOR                  (0x02)
  81 #define MPI2_VERSION_MINOR                  (0x00)
  82 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
  83 #define MPI2_VERSION_MAJOR_SHIFT            (8)
  84 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
  85 #define MPI2_VERSION_MINOR_SHIFT            (0)
  86 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) |   \
  87                                       MPI2_VERSION_MINOR)
  88
  89 #define MPI2_VERSION_02_00                  (0x0200)
  90
  91 /* versioning for this MPI header set */
  92 #define MPI2_HEADER_VERSION_UNIT            (0x11)
  93 #define MPI2_HEADER_VERSION_DEV             (0x00)
  94 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
  95 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
  96 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
  97 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
  98 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
  99
 100
 101 /*****************************************************************************
 102 *
 103 *        IOC State Definitions
 104 *
 105 *****************************************************************************/
 106
 107 #define MPI2_IOC_STATE_RESET               (0x00000000)
 108 #define MPI2_IOC_STATE_READY               (0x10000000)
 109 #define MPI2_IOC_STATE_OPERATIONAL         (0x20000000)
 110 #define MPI2_IOC_STATE_FAULT               (0x40000000)
 111
 112 #define MPI2_IOC_STATE_MASK                (0xF0000000)
 113 #define MPI2_IOC_STATE_SHIFT               (28)
 114
 115 /* Fault state range for prodcut specific codes */
 116 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN                 (0x0000)
 117 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX                 (0xEFFF)
 118
 119
 120 /*****************************************************************************
 121 *
 122 *        System Interface Register Definitions
 123 *
 124 *****************************************************************************/
 125
 126 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
 127 {
 128     U32         Doorbell;                   /* 0x00 */
 129     U32         WriteSequence;              /* 0x04 */
 130     U32         HostDiagnostic;             /* 0x08 */
 131     U32         Reserved1;                  /* 0x0C */
 132     U32         DiagRWData;                 /* 0x10 */
 133     U32         DiagRWAddressLow;           /* 0x14 */
 134     U32         DiagRWAddressHigh;          /* 0x18 */
 135     U32         Reserved2[5];               /* 0x1C */
 136     U32         HostInterruptStatus;        /* 0x30 */
 137     U32         HostInterruptMask;          /* 0x34 */
 138     U32         DCRData;                    /* 0x38 */
 139     U32         DCRAddress;                 /* 0x3C */
 140     U32         Reserved3[2];               /* 0x40 */
 141     U32         ReplyFreeHostIndex;         /* 0x48 */
 142     U32         Reserved4[8];               /* 0x4C */
 143     U32         ReplyPostHostIndex;         /* 0x6C */
 144     U32         Reserved5;                  /* 0x70 */
 145     U32         HCBSize;                    /* 0x74 */
 146     U32         HCBAddressLow;              /* 0x78 */
 147     U32         HCBAddressHigh;             /* 0x7C */
 148     U32         Reserved6[16];              /* 0x80 */
 149     U32         RequestDescriptorPostLow;   /* 0xC0 */
 150     U32         RequestDescriptorPostHigh;  /* 0xC4 */
 151     U32         Reserved7[14];              /* 0xC8 */
 152 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
 153   Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
 154
 155 /*
 156  * Defines for working with the Doorbell register.
 157  */
 158 #define MPI2_DOORBELL_OFFSET                    (0x00000000)
 159
 160 /* IOC --> System values */
 161 #define MPI2_DOORBELL_USED                      (0x08000000)
 162 #define MPI2_DOORBELL_WHO_INIT_MASK             (0x07000000)
 163 #define MPI2_DOORBELL_WHO_INIT_SHIFT            (24)
 164 #define MPI2_DOORBELL_FAULT_CODE_MASK           (0x0000FFFF)
 165 #define MPI2_DOORBELL_DATA_MASK                 (0x0000FFFF)
 166
 167 /* System --> IOC values */
 168 #define MPI2_DOORBELL_FUNCTION_MASK             (0xFF000000)
 169 #define MPI2_DOORBELL_FUNCTION_SHIFT            (24)
 170 #define MPI2_DOORBELL_ADD_DWORDS_MASK           (0x00FF0000)
 171 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT          (16)
 172
 173
 174 /*
 175  * Defines for the WriteSequence register
 176  */
 177 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 178 #define MPI2_WRSEQ_KEY_VALUE_MASK               (0x0000000F)
 179 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 180 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 181 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 182 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 183 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 184 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 185 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 186
 187 /*
 188  * Defines for the HostDiagnostic register
 189  */
 190 #define MPI2_HOST_DIAGNOSTIC_OFFSET             (0x00000008)
 191
 192 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK       (0x00001800)
 193 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT    (0x00000000)
 194 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW       (0x00000800)
 195
 196 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG           (0x00000400)
 197 #define MPI2_DIAG_FORCE_HCB_ON_RESET            (0x00000200)
 198 #define MPI2_DIAG_HCB_MODE                      (0x00000100)
 199 #define MPI2_DIAG_DIAG_WRITE_ENABLE             (0x00000080)
 200 #define MPI2_DIAG_FLASH_BAD_SIG                 (0x00000040)
 201 #define MPI2_DIAG_RESET_HISTORY                 (0x00000020)
 202 #define MPI2_DIAG_DIAG_RW_ENABLE                (0x00000010)
 203 #define MPI2_DIAG_RESET_ADAPTER                 (0x00000004)
 204 #define MPI2_DIAG_HOLD_IOC_RESET                (0x00000002)
 205
 206 /*
 207  * Offsets for DiagRWData and address
 208  */
 209 #define MPI2_DIAG_RW_DATA_OFFSET                (0x00000010)
 210 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET         (0x00000014)
 211 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET        (0x00000018)
 212
 213 /*
 214  * Defines for the HostInterruptStatus register
 215  */
 216 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET       (0x00000030)
 217 #define MPI2_HIS_SYS2IOC_DB_STATUS              (0x80000000)
 218 #define MPI2_HIS_IOP_DOORBELL_STATUS            MPI2_HIS_SYS2IOC_DB_STATUS
 219 #define MPI2_HIS_RESET_IRQ_STATUS               (0x40000000)
 220 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT     (0x00000008)
 221 #define MPI2_HIS_IOC2SYS_DB_STATUS              (0x00000001)
 222 #define MPI2_HIS_DOORBELL_INTERRUPT             MPI2_HIS_IOC2SYS_DB_STATUS
 223
 224 /*
 225  * Defines for the HostInterruptMask register
 226  */
 227 #define MPI2_HOST_INTERRUPT_MASK_OFFSET         (0x00000034)
 228 #define MPI2_HIM_RESET_IRQ_MASK                 (0x40000000)
 229 #define MPI2_HIM_REPLY_INT_MASK                 (0x00000008)
 230 #define MPI2_HIM_RIM                            MPI2_HIM_REPLY_INT_MASK
 231 #define MPI2_HIM_IOC2SYS_DB_MASK                (0x00000001)
 232 #define MPI2_HIM_DIM                            MPI2_HIM_IOC2SYS_DB_MASK
 233
 234 /*
 235  * Offsets for DCRData and address
 236  */
 237 #define MPI2_DCR_DATA_OFFSET                    (0x00000038)
 238 #define MPI2_DCR_ADDRESS_OFFSET                 (0x0000003C)
 239
 240 /*
 241  * Offset for the Reply Free Queue
 242  */
 243 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET       (0x00000048)
 244
 245 /*
 246  * Defines for the Reply Descriptor Post Queue
 247  */
 248 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
 249 #define MPI2_REPLY_POST_HOST_INDEX_MASK         (0x00FFFFFF)
 250 #define MPI2_RPHI_MSIX_INDEX_MASK               (0xFF000000)
 251 #define MPI2_RPHI_MSIX_INDEX_SHIFT              (24)
 252
 253 /*
 254  * Defines for the HCBSize and address
 255  */
 256 #define MPI2_HCB_SIZE_OFFSET                    (0x00000074)
 257 #define MPI2_HCB_SIZE_SIZE_MASK                 (0xFFFFF000)
 258 #define MPI2_HCB_SIZE_HCB_ENABLE                (0x00000001)
 259
 260 #define MPI2_HCB_ADDRESS_LOW_OFFSET             (0x00000078)
 261 #define MPI2_HCB_ADDRESS_HIGH_OFFSET            (0x0000007C)
 262
 263 /*
 264  * Offsets for the Request Queue
 265  */
 266 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET     (0x000000C0)
 267 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET    (0x000000C4)
 268
 269
 270 /*****************************************************************************
 271 *
 272 *        Message Descriptors
 273 *
 274 *****************************************************************************/
 275
 276 /* Request Descriptors */
 277
 278 /* Default Request Descriptor */
 279 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
 280 {
 281     U8              RequestFlags;               /* 0x00 */
 282     U8              MSIxIndex;                  /* 0x01 */
 283     U16             SMID;                       /* 0x02 */
 284     U16             LMID;                       /* 0x04 */
 285     U16             DescriptorTypeDependent;    /* 0x06 */
 286 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 287   MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 288   Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
 289
 290 /* defines for the RequestFlags field */
 291 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 292 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 293 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET             (0x02)
 294 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
 295 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE            (0x08)
 296 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR        (0x0A)
 297
 298 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
 299
 300
 301 /* High Priority Request Descriptor */
 302 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
 303 {
 304     U8              RequestFlags;               /* 0x00 */
 305     U8              MSIxIndex;                  /* 0x01 */
 306     U16             SMID;                       /* 0x02 */
 307     U16             LMID;                       /* 0x04 */
 308     U16             Reserved1;                  /* 0x06 */
 309 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 310   MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 311   Mpi2HighPriorityRequestDescriptor_t,
 312   MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
 313
 314
 315 /* SCSI IO Request Descriptor */
 316 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
 317 {
 318     U8              RequestFlags;               /* 0x00 */
 319     U8              MSIxIndex;                  /* 0x01 */
 320     U16             SMID;                       /* 0x02 */
 321     U16             LMID;                       /* 0x04 */
 322     U16             DevHandle;                  /* 0x06 */
 323 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 324   MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 325   Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
 326
 327
 328 /* SCSI Target Request Descriptor */
 329 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
 330 {
 331     U8              RequestFlags;               /* 0x00 */
 332     U8              MSIxIndex;                  /* 0x01 */
 333     U16             SMID;                       /* 0x02 */
 334     U16             LMID;                       /* 0x04 */
 335     U16             IoIndex;                    /* 0x06 */
 336 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 337   MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 338   Mpi2SCSITargetRequestDescriptor_t,
 339   MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
 340
 341
 342 /* RAID Accelerator Request Descriptor */
 343 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 344     U8              RequestFlags;               /* 0x00 */
 345     U8              MSIxIndex;                  /* 0x01 */
 346     U16             SMID;                       /* 0x02 */
 347     U16             LMID;                       /* 0x04 */
 348     U16             Reserved;                   /* 0x06 */
 349 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 350   MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 351   Mpi2RAIDAcceleratorRequestDescriptor_t,
 352   MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
 353
 354
 355 /* union of Request Descriptors */
 356 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
 357 {
 358     MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
 359     MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
 360     MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
 361     MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
 362     MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
 363     U64                                         Words;
 364 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
 365   Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
 366
 367
 368 /* Reply Descriptors */
 369
 370 /* Default Reply Descriptor */
 371 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
 372 {
 373     U8              ReplyFlags;                 /* 0x00 */
 374     U8              MSIxIndex;                  /* 0x01 */
 375     U16             DescriptorTypeDependent1;   /* 0x02 */
 376     U32             DescriptorTypeDependent2;   /* 0x04 */
 377 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
 378   Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
 379
 380 /* defines for the ReplyFlags field */
 381 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK                   (0x0F)
 382 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS             (0x00)
 383 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY               (0x01)
 384 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS        (0x02)
 385 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER       (0x03)
 386 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS    (0x05)
 387 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                      (0x0F)
 388
 389 /* values for marking a reply descriptor as unused */
 390 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK             (0xFFFFFFFF)
 391 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK             (0xFFFFFFFF)
 392
 393 /* Address Reply Descriptor */
 394 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
 395 {
 396     U8              ReplyFlags;                 /* 0x00 */
 397     U8              MSIxIndex;                  /* 0x01 */
 398     U16             SMID;                       /* 0x02 */
 399     U32             ReplyFrameAddress;          /* 0x04 */
 400 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
 401   Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
 402
 403 #define MPI2_ADDRESS_REPLY_SMID_INVALID                 (0x00)
 404
 405
 406 /* SCSI IO Success Reply Descriptor */
 407 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
 408 {
 409     U8              ReplyFlags;                 /* 0x00 */
 410     U8              MSIxIndex;                  /* 0x01 */
 411     U16             SMID;                       /* 0x02 */
 412     U16             TaskTag;                    /* 0x04 */
 413     U16             Reserved1;                  /* 0x06 */
 414 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 415   MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 416   Mpi2SCSIIOSuccessReplyDescriptor_t,
 417   MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
 418
 419
 420 /* TargetAssist Success Reply Descriptor */
 421 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
 422 {
 423     U8              ReplyFlags;                 /* 0x00 */
 424     U8              MSIxIndex;                  /* 0x01 */
 425     U16             SMID;                       /* 0x02 */
 426     U8              SequenceNumber;             /* 0x04 */
 427     U8              Reserved1;                  /* 0x05 */
 428     U16             IoIndex;                    /* 0x06 */
 429 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 430   MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 431   Mpi2TargetAssistSuccessReplyDescriptor_t,
 432   MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
 433
 434
 435 /* Target Command Buffer Reply Descriptor */
 436 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
 437 {
 438     U8              ReplyFlags;                 /* 0x00 */
 439     U8              MSIxIndex;                  /* 0x01 */
 440     U8              VP_ID;                      /* 0x02 */
 441     U8              Flags;                      /* 0x03 */
 442     U16             InitiatorDevHandle;         /* 0x04 */
 443     U16             IoIndex;                    /* 0x06 */
 444 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 445   MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 446   Mpi2TargetCommandBufferReplyDescriptor_t,
 447   MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
 448
 449 /* defines for Flags field */
 450 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK     (0x3F)
 451
 452
 453 /* RAID Accelerator Success Reply Descriptor */
 454 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 455     U8              ReplyFlags;                 /* 0x00 */
 456     U8              MSIxIndex;                  /* 0x01 */
 457     U16             SMID;                       /* 0x02 */
 458     U32             Reserved;                   /* 0x04 */
 459 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 460   MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 461   Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
 462   MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
 463
 464
 465 /* union of Reply Descriptors */
 466 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
 467 {
 468     MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
 469     MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
 470     MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
 471     MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR      TargetAssistSuccess;
 472     MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR     TargetCommandBuffer;
 473     MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR  RAIDAcceleratorSuccess;
 474     U64                                             Words;
 475 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
 476   Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
 477
 478
 479
 480 /*****************************************************************************
 481 *
 482 *        Message Functions
 483 *
 484 *****************************************************************************/
 485
 486 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
 487 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01) /* SCSI Task Management */
 488 #define MPI2_FUNCTION_IOC_INIT                      (0x02) /* IOC Init */
 489 #define MPI2_FUNCTION_IOC_FACTS                     (0x03) /* IOC Facts */
 490 #define MPI2_FUNCTION_CONFIG                        (0x04) /* Configuration */
 491 #define MPI2_FUNCTION_PORT_FACTS                    (0x05) /* Port Facts */
 492 #define MPI2_FUNCTION_PORT_ENABLE                   (0x06) /* Port Enable */
 493 #define MPI2_FUNCTION_EVENT_NOTIFICATION            (0x07) /* Event Notification */
 494 #define MPI2_FUNCTION_EVENT_ACK                     (0x08) /* Event Acknowledge */
 495 #define MPI2_FUNCTION_FW_DOWNLOAD                   (0x09) /* FW Download */
 496 #define MPI2_FUNCTION_TARGET_ASSIST                 (0x0B) /* Target Assist */
 497 #define MPI2_FUNCTION_TARGET_STATUS_SEND            (0x0C) /* Target Status Send */
 498 #define MPI2_FUNCTION_TARGET_MODE_ABORT             (0x0D) /* Target Mode Abort */
 499 #define MPI2_FUNCTION_FW_UPLOAD                     (0x12) /* FW Upload */
 500 #define MPI2_FUNCTION_RAID_ACTION                   (0x15) /* RAID Action */
 501 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH      (0x16) /* SCSI IO RAID Passthrough */
 502 #define MPI2_FUNCTION_TOOLBOX                       (0x17) /* Toolbox */
 503 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR      (0x18) /* SCSI Enclosure Processor */
 504 #define MPI2_FUNCTION_SMP_PASSTHROUGH               (0x1A) /* SMP Passthrough */
 505 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL           (0x1B) /* SAS IO Unit Control */
 506 #define MPI2_FUNCTION_SATA_PASSTHROUGH              (0x1C) /* SATA Passthrough */
 507 #define MPI2_FUNCTION_DIAG_BUFFER_POST              (0x1D) /* Diagnostic Buffer Post */
 508 #define MPI2_FUNCTION_DIAG_RELEASE                  (0x1E) /* Diagnostic Release */
 509 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST      (0x24) /* Target Command Buffer Post Base */
 510 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST      (0x25) /* Target Command Buffer Post List */
 511 #define MPI2_FUNCTION_RAID_ACCELERATOR              (0x2C) /* RAID Accelerator*/
 512 /* Host Based Discovery Action */
 513 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION   (0x2F)
 514 /* Power Management Control */
 515 #define MPI2_FUNCTION_PWR_MGMT_CONTROL              (0x30)
 516 /* beginning of product-specific range */
 517 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC          (0xF0)
 518 /* end of product-specific range */
 519 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC          (0xFF)
 520
 521
 522
 523
 524 /* Doorbell functions */
 525 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET        (0x40)
 526 #define MPI2_FUNCTION_HANDSHAKE                     (0x42)
 527
 528
 529 /*****************************************************************************
 530 *
 531 *        IOC Status Values
 532 *
 533 *****************************************************************************/
 534
 535 /* mask for IOCStatus status value */
 536 #define MPI2_IOCSTATUS_MASK                     (0x7FFF)
 537
 538 /****************************************************************************
 539 *  Common IOCStatus values for all replies
 540 ****************************************************************************/
 541
 542 #define MPI2_IOCSTATUS_SUCCESS                      (0x0000)
 543 #define MPI2_IOCSTATUS_INVALID_FUNCTION             (0x0001)
 544 #define MPI2_IOCSTATUS_BUSY                         (0x0002)
 545 #define MPI2_IOCSTATUS_INVALID_SGL                  (0x0003)
 546 #define MPI2_IOCSTATUS_INTERNAL_ERROR               (0x0004)
 547 #define MPI2_IOCSTATUS_INVALID_VPID                 (0x0005)
 548 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES       (0x0006)
 549 #define MPI2_IOCSTATUS_INVALID_FIELD                (0x0007)
 550 #define MPI2_IOCSTATUS_INVALID_STATE                (0x0008)
 551 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED       (0x0009)
 552
 553 /****************************************************************************
 554 *  Config IOCStatus values
 555 ****************************************************************************/
 556
 557 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION        (0x0020)
 558 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE          (0x0021)
 559 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE          (0x0022)
 560 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA          (0x0023)
 561 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS           (0x0024)
 562 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT           (0x0025)
 563
 564 /****************************************************************************
 565 *  SCSI IO Reply
 566 ****************************************************************************/
 567
 568 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR         (0x0040)
 569 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE       (0x0042)
 570 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE        (0x0043)
 571 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN            (0x0044)
 572 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN           (0x0045)
 573 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR           (0x0046)
 574 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR          (0x0047)
 575 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED         (0x0048)
 576 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH       (0x0049)
 577 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED        (0x004A)
 578 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED          (0x004B)
 579 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED          (0x004C)
 580
 581 /****************************************************************************
 582 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
 583 ****************************************************************************/
 584
 585 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR             (0x004D)
 586 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR           (0x004E)
 587 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR           (0x004F)
 588
 589 /****************************************************************************
 590 *  SCSI Target values
 591 ****************************************************************************/
 592
 593 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX      (0x0062)
 594 #define MPI2_IOCSTATUS_TARGET_ABORTED               (0x0063)
 595 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE     (0x0064)
 596 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION         (0x0065)
 597 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH   (0x006A)
 598 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR     (0x006D)
 599 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA   (0x006E)
 600 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT          (0x006F)
 601 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT       (0x0070)
 602 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED          (0x0071)
 603
 604 /****************************************************************************
 605 *  Serial Attached SCSI values
 606 ****************************************************************************/
 607
 608 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED       (0x0090)
 609 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN         (0x0091)
 610
 611 /****************************************************************************
 612 *  Diagnostic Buffer Post / Diagnostic Release values
 613 ****************************************************************************/
 614
 615 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED          (0x00A0)
 616
 617 /****************************************************************************
 618 *  RAID Accelerator values
 619 ****************************************************************************/
 620
 621 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR             (0x00B0)
 622
 623 /****************************************************************************
 624 *  IOCStatus flag to indicate that log info is available
 625 ****************************************************************************/
 626
 627 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE      (0x8000)
 628
 629 /****************************************************************************
 630 *  IOCLogInfo Types
 631 ****************************************************************************/
 632
 633 #define MPI2_IOCLOGINFO_TYPE_MASK               (0xF0000000)
 634 #define MPI2_IOCLOGINFO_TYPE_SHIFT              (28)
 635 #define MPI2_IOCLOGINFO_TYPE_NONE               (0x0)
 636 #define MPI2_IOCLOGINFO_TYPE_SCSI               (0x1)
 637 #define MPI2_IOCLOGINFO_TYPE_FC                 (0x2)
 638 #define MPI2_IOCLOGINFO_TYPE_SAS                (0x3)
 639 #define MPI2_IOCLOGINFO_TYPE_ISCSI              (0x4)
 640 #define MPI2_IOCLOGINFO_LOG_DATA_MASK           (0x0FFFFFFF)
 641
 642
 643 /*****************************************************************************
 644 *
 645 *        Standard Message Structures
 646 *
 647 *****************************************************************************/
 648
 649 /****************************************************************************
 650 * Request Message Header for all request messages
 651 ****************************************************************************/
 652
 653 typedef struct _MPI2_REQUEST_HEADER
 654 {
 655     U16             FunctionDependent1;         /* 0x00 */
 656     U8              ChainOffset;                /* 0x02 */
 657     U8              Function;                   /* 0x03 */
 658     U16             FunctionDependent2;         /* 0x04 */
 659     U8              FunctionDependent3;         /* 0x06 */
 660     U8              MsgFlags;                   /* 0x07 */
 661     U8              VP_ID;                      /* 0x08 */
 662     U8              VF_ID;                      /* 0x09 */
 663     U16             Reserved1;                  /* 0x0A */
 664 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
 665   MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
 666
 667
 668 /****************************************************************************
 669 *  Default Reply
 670 ****************************************************************************/
 671
 672 typedef struct _MPI2_DEFAULT_REPLY
 673 {
 674     U16             FunctionDependent1;         /* 0x00 */
 675     U8              MsgLength;                  /* 0x02 */
 676     U8              Function;                   /* 0x03 */
 677     U16             FunctionDependent2;         /* 0x04 */
 678     U8              FunctionDependent3;         /* 0x06 */
 679     U8              MsgFlags;                   /* 0x07 */
 680     U8              VP_ID;                      /* 0x08 */
 681     U8              VF_ID;                      /* 0x09 */
 682     U16             Reserved1;                  /* 0x0A */
 683     U16             FunctionDependent5;         /* 0x0C */
 684     U16             IOCStatus;                  /* 0x0E */
 685     U32             IOCLogInfo;                 /* 0x10 */
 686 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
 687   MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
 688
 689
 690 /* common version structure/union used in messages and configuration pages */
 691
 692 typedef struct _MPI2_VERSION_STRUCT
 693 {
 694     U8                      Dev;                        /* 0x00 */
 695     U8                      Unit;                       /* 0x01 */
 696     U8                      Minor;                      /* 0x02 */
 697     U8                      Major;                      /* 0x03 */
 698 } MPI2_VERSION_STRUCT;
 699
 700 typedef union _MPI2_VERSION_UNION
 701 {
 702     MPI2_VERSION_STRUCT     Struct;
 703     U32                     Word;
 704 } MPI2_VERSION_UNION;
 705
 706
 707 /* LUN field defines, common to many structures */
 708 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING             (0x0000FFFF)
 709 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING            (0xFFFF0000)
 710 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING             (0x0000FFFF)
 711 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING            (0xFFFF0000)
 712 #define MPI2_LUN_LEVEL_1_WORD                       (0xFF00)
 713 #define MPI2_LUN_LEVEL_1_DWORD                      (0x0000FF00)
 714
 715
 716 /*****************************************************************************
 717 *
 718 *        Fusion-MPT MPI Scatter Gather Elements
 719 *
 720 *****************************************************************************/
 721
 722 /****************************************************************************
 723 *  MPI Simple Element structures
 724 ****************************************************************************/
 725
 726 typedef struct _MPI2_SGE_SIMPLE32
 727 {
 728     U32                     FlagsLength;
 729     U32                     Address;
 730 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
 731   Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
 732
 733 typedef struct _MPI2_SGE_SIMPLE64
 734 {
 735     U32                     FlagsLength;
 736     U64                     Address;
 737 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
 738   Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
 739
 740 typedef struct _MPI2_SGE_SIMPLE_UNION
 741 {
 742     U32                     FlagsLength;
 743     union
 744     {
 745         U32                 Address32;
 746         U64                 Address64;
 747     } u;
 748 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
 749   Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
 750
 751
 752 /****************************************************************************
 753 *  MPI Chain Element structures
 754 ****************************************************************************/
 755
 756 typedef struct _MPI2_SGE_CHAIN32
 757 {
 758     U16                     Length;
 759     U8                      NextChainOffset;
 760     U8                      Flags;
 761     U32                     Address;
 762 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
 763   Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
 764
 765 typedef struct _MPI2_SGE_CHAIN64
 766 {
 767     U16                     Length;
 768     U8                      NextChainOffset;
 769     U8                      Flags;
 770     U64                     Address;
 771 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
 772   Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
 773
 774 typedef struct _MPI2_SGE_CHAIN_UNION
 775 {
 776     U16                     Length;
 777     U8                      NextChainOffset;
 778     U8                      Flags;
 779     union
 780     {
 781         U32                 Address32;
 782         U64                 Address64;
 783     } u;
 784 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
 785   Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
 786
 787
 788 /****************************************************************************
 789 *  MPI Transaction Context Element structures
 790 ****************************************************************************/
 791
 792 typedef struct _MPI2_SGE_TRANSACTION32
 793 {
 794     U8                      Reserved;
 795     U8                      ContextSize;
 796     U8                      DetailsLength;
 797     U8                      Flags;
 798     U32                     TransactionContext[1];
 799     U32                     TransactionDetails[1];
 800 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
 801   Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
 802
 803 typedef struct _MPI2_SGE_TRANSACTION64
 804 {
 805     U8                      Reserved;
 806     U8                      ContextSize;
 807     U8                      DetailsLength;
 808     U8                      Flags;
 809     U32                     TransactionContext[2];
 810     U32                     TransactionDetails[1];
 811 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
 812   Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
 813
 814 typedef struct _MPI2_SGE_TRANSACTION96
 815 {
 816     U8                      Reserved;
 817     U8                      ContextSize;
 818     U8                      DetailsLength;
 819     U8                      Flags;
 820     U32                     TransactionContext[3];
 821     U32                     TransactionDetails[1];
 822 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
 823   Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
 824
 825 typedef struct _MPI2_SGE_TRANSACTION128
 826 {
 827     U8                      Reserved;
 828     U8                      ContextSize;
 829     U8                      DetailsLength;
 830     U8                      Flags;
 831     U32                     TransactionContext[4];
 832     U32                     TransactionDetails[1];
 833 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
 834   Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
 835
 836 typedef struct _MPI2_SGE_TRANSACTION_UNION
 837 {
 838     U8                      Reserved;
 839     U8                      ContextSize;
 840     U8                      DetailsLength;
 841     U8                      Flags;
 842     union
 843     {
 844         U32                 TransactionContext32[1];
 845         U32                 TransactionContext64[2];
 846         U32                 TransactionContext96[3];
 847         U32                 TransactionContext128[4];
 848     } u;
 849     U32                     TransactionDetails[1];
 850 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
 851   Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
 852
 853
 854 /****************************************************************************
 855 *  MPI SGE union for IO SGL's
 856 ****************************************************************************/
 857
 858 typedef struct _MPI2_MPI_SGE_IO_UNION
 859 {
 860     union
 861     {
 862         MPI2_SGE_SIMPLE_UNION   Simple;
 863         MPI2_SGE_CHAIN_UNION    Chain;
 864     } u;
 865 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
 866   Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
 867
 868
 869 /****************************************************************************
 870 *  MPI SGE union for SGL's with Simple and Transaction elements
 871 ****************************************************************************/
 872
 873 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
 874 {
 875     union
 876     {
 877         MPI2_SGE_SIMPLE_UNION       Simple;
 878         MPI2_SGE_TRANSACTION_UNION  Transaction;
 879     } u;
 880 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
 881   Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
 882
 883
 884 /****************************************************************************
 885 *  All MPI SGE types union
 886 ****************************************************************************/
 887
 888 typedef struct _MPI2_MPI_SGE_UNION
 889 {
 890     union
 891     {
 892         MPI2_SGE_SIMPLE_UNION       Simple;
 893         MPI2_SGE_CHAIN_UNION        Chain;
 894         MPI2_SGE_TRANSACTION_UNION  Transaction;
 895     } u;
 896 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
 897   Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
 898
 899
 900 /****************************************************************************
 901 *  MPI SGE field definition and masks
 902 ****************************************************************************/
 903
 904 /* Flags field bit definitions */
 905
 906 #define MPI2_SGE_FLAGS_LAST_ELEMENT             (0x80)
 907 #define MPI2_SGE_FLAGS_END_OF_BUFFER            (0x40)
 908 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK        (0x30)
 909 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS            (0x08)
 910 #define MPI2_SGE_FLAGS_DIRECTION                (0x04)
 911 #define MPI2_SGE_FLAGS_ADDRESS_SIZE             (0x02)
 912 #define MPI2_SGE_FLAGS_END_OF_LIST              (0x01)
 913
 914 #define MPI2_SGE_FLAGS_SHIFT                    (24)
 915
 916 #define MPI2_SGE_LENGTH_MASK                    (0x00FFFFFF)
 917 #define MPI2_SGE_CHAIN_LENGTH_MASK              (0x0000FFFF)
 918
 919 /* Element Type */
 920
 921 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT      (0x00)
 922 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT           (0x10)
 923 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT            (0x30)
 924 #define MPI2_SGE_FLAGS_ELEMENT_MASK             (0x30)
 925
 926 /* Address location */
 927
 928 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS           (0x00)
 929
 930 /* Direction */
 931
 932 #define MPI2_SGE_FLAGS_IOC_TO_HOST              (0x00)
 933 #define MPI2_SGE_FLAGS_HOST_TO_IOC              (0x04)
 934
 935 #define MPI2_SGE_FLAGS_DEST                     (MPI2_SGE_FLAGS_IOC_TO_HOST)
 936 #define MPI2_SGE_FLAGS_SOURCE                   (MPI2_SGE_FLAGS_HOST_TO_IOC)
 937
 938 /* Address Size */
 939
 940 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING        (0x00)
 941 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 942
 943 /* Context Size */
 944
 945 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT           (0x00)
 946 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT           (0x02)
 947 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT           (0x04)
 948 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT          (0x06)
 949
 950 #define MPI2_SGE_CHAIN_OFFSET_MASK              (0x00FF0000)
 951 #define MPI2_SGE_CHAIN_OFFSET_SHIFT             (16)
 952
 953 /****************************************************************************
 954 *  MPI SGE operation Macros
 955 ****************************************************************************/
 956
 957 /* SIMPLE FlagsLength manipulations... */
 958 #define MPI2_SGE_SET_FLAGS(f)          ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
 959 #define MPI2_SGE_GET_FLAGS(f)          (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
 960 #define MPI2_SGE_LENGTH(f)             ((f) & MPI2_SGE_LENGTH_MASK)
 961 #define MPI2_SGE_CHAIN_LENGTH(f)       ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
 962
 963 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
 964
 965 #define MPI2_pSGE_GET_FLAGS(psg)            MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
 966 #define MPI2_pSGE_GET_LENGTH(psg)           MPI2_SGE_LENGTH((psg)->FlagsLength)
 967 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
 968
 969 /* CAUTION - The following are READ-MODIFY-WRITE! */
 970 #define MPI2_pSGE_SET_FLAGS(psg,f)      (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
 971 #define MPI2_pSGE_SET_LENGTH(psg,l)     (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
 972
 973 #define MPI2_GET_CHAIN_OFFSET(x)    ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
 974
 975
 976 /*****************************************************************************
 977 *
 978 *        Fusion-MPT IEEE Scatter Gather Elements
 979 *
 980 *****************************************************************************/
 981
 982 /****************************************************************************
 983 *  IEEE Simple Element structures
 984 ****************************************************************************/
 985
 986 typedef struct _MPI2_IEEE_SGE_SIMPLE32
 987 {
 988     U32                     Address;
 989     U32                     FlagsLength;
 990 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
 991   Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
 992
 993 typedef struct _MPI2_IEEE_SGE_SIMPLE64
 994 {
 995     U64                     Address;
 996     U32                     Length;
 997     U16                     Reserved1;
 998     U8                      Reserved2;
 999     U8                      Flags;
1000 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1001   Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1002
1003 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1004 {
1005     MPI2_IEEE_SGE_SIMPLE32  Simple32;
1006     MPI2_IEEE_SGE_SIMPLE64  Simple64;
1007 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1008   Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1009
1010
1011 /****************************************************************************
1012 *  IEEE Chain Element structures
1013 ****************************************************************************/
1014
1015 typedef MPI2_IEEE_SGE_SIMPLE32  MPI2_IEEE_SGE_CHAIN32;
1016
1017 typedef MPI2_IEEE_SGE_SIMPLE64  MPI2_IEEE_SGE_CHAIN64;
1018
1019 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1020 {
1021     MPI2_IEEE_SGE_CHAIN32   Chain32;
1022     MPI2_IEEE_SGE_CHAIN64   Chain64;
1023 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1024   Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1025
1026
1027 /****************************************************************************
1028 *  All IEEE SGE types union
1029 ****************************************************************************/
1030
1031 typedef struct _MPI2_IEEE_SGE_UNION
1032 {
1033     union
1034     {
1035         MPI2_IEEE_SGE_SIMPLE_UNION  Simple;
1036         MPI2_IEEE_SGE_CHAIN_UNION   Chain;
1037     } u;
1038 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1039   Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1040
1041
1042 /****************************************************************************
1043 *  IEEE SGE field definitions and masks
1044 ****************************************************************************/
1045
1046 /* Flags field bit definitions */
1047
1048 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK   (0x80)
1049
1050 #define MPI2_IEEE32_SGE_FLAGS_SHIFT             (24)
1051
1052 #define MPI2_IEEE32_SGE_LENGTH_MASK             (0x00FFFFFF)
1053
1054 /* Element Type */
1055
1056 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT      (0x00)
1057 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT       (0x80)
1058
1059 /* Data Location Address Space */
1060
1061 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK           (0x03)
1062 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR         (0x00)
1063 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR         (0x01)
1064 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR         (0x02)
1065 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
1066
1067
1068 /****************************************************************************
1069 *  IEEE SGE operation Macros
1070 ****************************************************************************/
1071
1072 /* SIMPLE FlagsLength manipulations... */
1073 #define MPI2_IEEE32_SGE_SET_FLAGS(f)     ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1074 #define MPI2_IEEE32_SGE_GET_FLAGS(f)     (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1075 #define MPI2_IEEE32_SGE_LENGTH(f)        ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1076
1077 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)      (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1078
1079 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg)             MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1080 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg)            MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1081 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l)  (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1082
1083 /* CAUTION - The following are READ-MODIFY-WRITE! */
1084 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f)    (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1085 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l)   (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1086
1087
1088
1089
1090 /*****************************************************************************
1091 *
1092 *        Fusion-MPT MPI/IEEE Scatter Gather Unions
1093 *
1094 *****************************************************************************/
1095
1096 typedef union _MPI2_SIMPLE_SGE_UNION
1097 {
1098     MPI2_SGE_SIMPLE_UNION       MpiSimple;
1099     MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
1100 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1101   Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1102
1103
1104 typedef union _MPI2_SGE_IO_UNION
1105 {
1106     MPI2_SGE_SIMPLE_UNION       MpiSimple;
1107     MPI2_SGE_CHAIN_UNION        MpiChain;
1108     MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
1109     MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
1110 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1111   Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1112
1113
1114 /****************************************************************************
1115 *
1116 *  Values for SGLFlags field, used in many request messages with an SGL
1117 *
1118 ****************************************************************************/
1119
1120 /* values for MPI SGL Data Location Address Space subfield */
1121 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK            (0x0C)
1122 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE          (0x00)
1123 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE          (0x04)
1124 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE          (0x08)
1125 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE       (0x0C)
1126 /* values for SGL Type subfield */
1127 #define MPI2_SGLFLAGS_SGL_TYPE_MASK                 (0x03)
1128 #define MPI2_SGLFLAGS_SGL_TYPE_MPI                  (0x00)
1129 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32               (0x01)
1130 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64               (0x02)
1131
1132
1133 #endif
1134