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xHCI: refine td allocation
[zen-stable.git] / arch / arm / mach-iop13xx / pci.c
blob251c40897dad44085f23e9850bf29c23540c0a65
1 /*
2 * iop13xx PCI support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20 #include <linux/pci.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/jiffies.h>
24 #include <asm/irq.h>
25 #include <mach/hardware.h>
26 #include <asm/sizes.h>
27 #include <asm/signal.h>
28 #include <asm/mach/pci.h>
29 #include <mach/pci.h>
30
31 #define IOP13XX_PCI_DEBUG 0
32 #define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
33
34 u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
35 u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
36 static struct pci_bus *pci_bus_atux = 0;
37 static struct pci_bus *pci_bus_atue = 0;
38 u32 iop13xx_atue_mem_base;
39 u32 iop13xx_atux_mem_base;
40 size_t iop13xx_atue_mem_size;
41 size_t iop13xx_atux_mem_size;
42
43 EXPORT_SYMBOL(iop13xx_atue_mem_base);
44 EXPORT_SYMBOL(iop13xx_atux_mem_base);
45 EXPORT_SYMBOL(iop13xx_atue_mem_size);
46 EXPORT_SYMBOL(iop13xx_atux_mem_size);
47
48 int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
49 static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
50 access */
51
52 /* Scan the initialized busses and ioremap the requested memory range
53 */
54 void iop13xx_map_pci_memory(void)
55 {
56 int atu;
57 struct pci_bus *bus;
58 struct pci_dev *dev;
59 resource_size_t end = 0;
60
61 for (atu = 0; atu < 2; atu++) {
62 bus = atu ? pci_bus_atue : pci_bus_atux;
63 if (bus) {
64 list_for_each_entry(dev, &bus->devices, bus_list) {
65 int i;
66 int max = 7;
67
68 if (dev->subordinate)
69 max = DEVICE_COUNT_RESOURCE;
70
71 for (i = 0; i < max; i++) {
72 struct resource *res = &dev->resource[i];
73 if (res->flags & IORESOURCE_MEM)
74 end = max(res->end, end);
75 }
76 }
77
78 switch(atu) {
79 case 0:
80 iop13xx_atux_mem_size =
81 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
82
83 /* 16MB align the request */
84 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
85 iop13xx_atux_mem_size &= ~(SZ_16M - 1);
86 iop13xx_atux_mem_size += SZ_16M;
87 }
88
89 if (end) {
90 iop13xx_atux_mem_base =
91 (u32) __arm_ioremap_pfn(
92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
93 , 0, iop13xx_atux_mem_size, MT_DEVICE);
94 if (!iop13xx_atux_mem_base) {
95 printk("%s: atux allocation "
96 "failed\n", __func__);
97 BUG();
98 }
99 } else
100 iop13xx_atux_mem_size = 0;
101 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
102 __func__, atu, iop13xx_atux_mem_size,
103 iop13xx_atux_mem_base);
104 break;
105 case 1:
106 iop13xx_atue_mem_size =
107 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
108
109 /* 16MB align the request */
110 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
111 iop13xx_atue_mem_size &= ~(SZ_16M - 1);
112 iop13xx_atue_mem_size += SZ_16M;
113 }
114
115 if (end) {
116 iop13xx_atue_mem_base =
117 (u32) __arm_ioremap_pfn(
118 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
119 , 0, iop13xx_atue_mem_size, MT_DEVICE);
120 if (!iop13xx_atue_mem_base) {
121 printk("%s: atue allocation "
122 "failed\n", __func__);
123 BUG();
124 }
125 } else
126 iop13xx_atue_mem_size = 0;
127 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
128 __func__, atu, iop13xx_atue_mem_size,
129 iop13xx_atue_mem_base);
130 break;
131 }
132
133 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
134 atu ? "ATUE" : "ATUX",
135 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
136 SZ_1M,
137 atu ? IOP13XX_PCIE_LOWER_MEM_RA :
138 IOP13XX_PCIX_LOWER_MEM_RA,
139 atu ? iop13xx_atue_mem_base :
140 iop13xx_atux_mem_base);
141 end = 0;
142 }
143
144 }
145 }
146
147 static int iop13xx_atu_function(int atu)
148 {
149 int func = 0;
150 /* the function number depends on the value of the
151 * IOP13XX_INTERFACE_SEL_PCIX reset strap
152 * see C-Spec section 3.17
153 */
154 switch(atu) {
155 case IOP13XX_INIT_ATU_ATUX:
156 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
157 func = 5;
158 else
159 func = 0;
160 break;
161 case IOP13XX_INIT_ATU_ATUE:
162 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
163 func = 0;
164 else
165 func = 5;
166 break;
167 default:
168 BUG();
169 }
170
171 return func;
172 }
173
174 /* iop13xx_atux_cfg_address - format a configuration address for atux
175 * @bus: Target bus to access
176 * @devfn: Combined device number and function number
177 * @where: Desired register's address offset
178 *
179 * Convert the parameters to a configuration address formatted
180 * according the PCI-X 2.0 specification
181 */
182 static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
183 {
184 struct pci_sys_data *sys = bus->sysdata;
185 u32 addr;
186
187 if (sys->busnr == bus->number)
188 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
189 else
190 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
191
192 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
193 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
194
195 return addr;
196 }
197
198 /* iop13xx_atue_cfg_address - format a configuration address for atue
199 * @bus: Target bus to access
200 * @devfn: Combined device number and function number
201 * @where: Desired register's address offset
202 *
203 * Convert the parameters to an address usable by the ATUE_OCCAR
204 */
205 static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
206 {
207 struct pci_sys_data *sys = bus->sysdata;
208 u32 addr;
209
210 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
211 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
212 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
213 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
214 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
215 (where & ~0x3);
216
217 if (sys->busnr != bus->number)
218 addr |= 1; /* type 1 access */
219
220 return addr;
221 }
222
223 /* This routine checks the status of the last configuration cycle. If an error
224 * was detected it returns >0, else it returns a 0. The errors being checked
225 * are parity, master abort, target abort (master and target). These types of
226 * errors occur during a config cycle where there is no device, like during
227 * the discovery stage.
228 */
229 static int iop13xx_atux_pci_status(int clear)
230 {
231 unsigned int status;
232 int err = 0;
233
234 /*
235 * Check the status registers.
236 */
237 status = __raw_readw(IOP13XX_ATUX_ATUSR);
238 if (status & IOP_PCI_STATUS_ERROR)
239 {
240 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
241 if(clear)
242 __raw_writew(status & IOP_PCI_STATUS_ERROR,
243 IOP13XX_ATUX_ATUSR);
244 err = 1;
245 }
246 status = __raw_readl(IOP13XX_ATUX_ATUISR);
247 if (status & IOP13XX_ATUX_ATUISR_ERROR)
248 {
249 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
250 if(clear)
251 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
252 IOP13XX_ATUX_ATUISR);
253 err = 1;
254 }
255 return err;
256 }
257
258 /* Simply write the address register and read the configuration
259 * data. Note that the data dependency on %0 encourages an abort
260 * to be detected before we return.
261 */
262 static u32 iop13xx_atux_read(unsigned long addr)
263 {
264 u32 val;
265
266 __asm__ __volatile__(
267 "str %1, [%2]\n\t"
268 "ldr %0, [%3]\n\t"
269 "mov %0, %0\n\t"
270 : "=r" (val)
271 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
272
273 return val;
274 }
275
276 /* The read routines must check the error status of the last configuration
277 * cycle. If there was an error, the routine returns all hex f's.
278 */
279 static int
280 iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
281 int size, u32 *value)
282 {
283 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
284 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
285
286 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
287 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
288 IOP13XX_XBG_BECSR);
289 val = 0xffffffff;
290 }
291
292 *value = val;
293
294 return PCIBIOS_SUCCESSFUL;
295 }
296
297 static int
298 iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
299 int size, u32 value)
300 {
301 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
302 u32 val;
303
304 if (size != 4) {
305 val = iop13xx_atux_read(addr);
306 if (!iop13xx_atux_pci_status(1) == 0)
307 return PCIBIOS_SUCCESSFUL;
308
309 where = (where & 3) * 8;
310
311 if (size == 1)
312 val &= ~(0xff << where);
313 else
314 val &= ~(0xffff << where);
315
316 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
317 } else {
318 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
319 __raw_writel(value, IOP13XX_ATUX_OCCDR);
320 }
321
322 return PCIBIOS_SUCCESSFUL;
323 }
324
325 static struct pci_ops iop13xx_atux_ops = {
326 .read = iop13xx_atux_read_config,
327 .write = iop13xx_atux_write_config,
328 };
329
330 /* This routine checks the status of the last configuration cycle. If an error
331 * was detected it returns >0, else it returns a 0. The errors being checked
332 * are parity, master abort, target abort (master and target). These types of
333 * errors occur during a config cycle where there is no device, like during
334 * the discovery stage.
335 */
336 static int iop13xx_atue_pci_status(int clear)
337 {
338 unsigned int status;
339 int err = 0;
340
341 /*
342 * Check the status registers.
343 */
344
345 /* standard pci status register */
346 status = __raw_readw(IOP13XX_ATUE_ATUSR);
347 if (status & IOP_PCI_STATUS_ERROR) {
348 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
349 if(clear)
350 __raw_writew(status & IOP_PCI_STATUS_ERROR,
351 IOP13XX_ATUE_ATUSR);
352 err++;
353 }
354
355 /* check the normal status bits in the ATUISR */
356 status = __raw_readl(IOP13XX_ATUE_ATUISR);
357 if (status & IOP13XX_ATUE_ATUISR_ERROR) {
358 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
359 if (clear)
360 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
361 IOP13XX_ATUE_ATUISR);
362 err++;
363
364 /* check the PCI-E status if the ATUISR reports an interface error */
365 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
366 /* get the unmasked errors */
367 status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
368 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
369
370 if (status) {
371 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
372 __raw_readl(IOP13XX_ATUE_PIE_STS));
373 err++;
374 } else {
375 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
376 __raw_readl(IOP13XX_ATUE_PIE_STS));
377 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
378 __raw_readl(IOP13XX_ATUE_PIE_MSK));
379 BUG();
380 }
381
382 if(clear)
383 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
384 }
385 }
386
387 return err;
388 }
389
390 static int
391 iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
392 {
393 WARN_ON(idsel != 0);
394
395 switch (pin) {
396 case 1: return ATUE_INTA;
397 case 2: return ATUE_INTB;
398 case 3: return ATUE_INTC;
399 case 4: return ATUE_INTD;
400 default: return -1;
401 }
402 }
403
404 static u32 iop13xx_atue_read(unsigned long addr)
405 {
406 u32 val;
407
408 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
409 val = __raw_readl(IOP13XX_ATUE_OCCDR);
410
411 rmb();
412
413 return val;
414 }
415
416 /* The read routines must check the error status of the last configuration
417 * cycle. If there was an error, the routine returns all hex f's.
418 */
419 static int
420 iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
421 int size, u32 *value)
422 {
423 u32 val;
424 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
425
426 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
427 if (!PCI_SLOT(devfn) || (addr & 1)) {
428 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
429 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
430 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
431 IOP13XX_XBG_BECSR);
432 val = 0xffffffff;
433 }
434
435 PRINTK("addr=%#0lx, val=%#010x", addr, val);
436 } else
437 val = 0xffffffff;
438
439 *value = val;
440
441 return PCIBIOS_SUCCESSFUL;
442 }
443
444 static int
445 iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
446 int size, u32 value)
447 {
448 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
449 u32 val;
450
451 if (size != 4) {
452 val = iop13xx_atue_read(addr);
453 if (!iop13xx_atue_pci_status(1) == 0)
454 return PCIBIOS_SUCCESSFUL;
455
456 where = (where & 3) * 8;
457
458 if (size == 1)
459 val &= ~(0xff << where);
460 else
461 val &= ~(0xffff << where);
462
463 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
464 } else {
465 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
466 __raw_writel(value, IOP13XX_ATUE_OCCDR);
467 }
468
469 return PCIBIOS_SUCCESSFUL;
470 }
471
472 static struct pci_ops iop13xx_atue_ops = {
473 .read = iop13xx_atue_read_config,
474 .write = iop13xx_atue_write_config,
475 };
476
477 /* When a PCI device does not exist during config cycles, the XScale gets a
478 * bus error instead of returning 0xffffffff. We can't rely on the ATU status
479 * bits to tell us that it was indeed a configuration cycle that caused this
480 * error especially in the case when the ATUE link is down. Instead we rely
481 * on data from the south XSI bridge to validate the abort
482 */
483 int
484 iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
485 {
486 PRINTK("Data abort: address = 0x%08lx "
487 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
488 addr, fsr, regs->ARM_pc, regs->ARM_lr);
489
490 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
491 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
492 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
493
494 /* If it was an imprecise abort, then we need to correct the
495 * return address to be _after_ the instruction.
496 */
497 if (fsr & (1 << 10))
498 regs->ARM_pc += 4;
499
500 if (is_atue_occdr_error() || is_atux_occdr_error())
501 return 0;
502 else
503 return 1;
504 }
505
506 /* Scan an IOP13XX PCI bus. nr selects which ATU we use.
507 */
508 struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
509 {
510 int which_atu;
511 struct pci_bus *bus = NULL;
512
513 switch (init_atu) {
514 case IOP13XX_INIT_ATU_ATUX:
515 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
516 break;
517 case IOP13XX_INIT_ATU_ATUE:
518 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
519 break;
520 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
521 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
522 break;
523 default:
524 which_atu = 0;
525 }
526
527 if (!which_atu) {
528 BUG();
529 return NULL;
530 }
531
532 switch (which_atu) {
533 case IOP13XX_INIT_ATU_ATUX:
534 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
535 atux_trhfa_timeout)) /* ensure not wrap */
536 while(time_before(jiffies, atux_trhfa_timeout))
537 udelay(100);
538
539 bus = pci_bus_atux = pci_scan_bus(sys->busnr,
540 &iop13xx_atux_ops,
541 sys);
542 break;
543 case IOP13XX_INIT_ATU_ATUE:
544 bus = pci_bus_atue = pci_scan_bus(sys->busnr,
545 &iop13xx_atue_ops,
546 sys);
547 break;
548 }
549
550 return bus;
551 }
552
553 /* This function is called from iop13xx_pci_init() after assigning valid
554 * values to iop13xx_atue_pmmr_offset. This is the location for common
555 * setup of ATUE for all IOP13XX implementations.
556 */
557 void __init iop13xx_atue_setup(void)
558 {
559 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
560 u32 reg_val;
561
562 #ifdef CONFIG_PCI_MSI
563 /* BAR 0 (inbound msi window) */
564 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
565 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0);
566 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0);
567 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0);
568 #endif
569
570 /* BAR 1 (1:1 mapping with Physical RAM) */
571 /* Set limit and enable */
572 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
573 IOP13XX_ATUE_IALR1);
574 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
575
576 /* Set base at the top of the reserved address space */
577 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
578 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
579
580 /* 1:1 mapping with physical ram
581 * (leave big endian byte swap disabled)
582 */
583 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
584 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
585
586 /* Outbound window 1 (PCIX/PCIE memory window) */
587 /* 32 bit Address Space */
588 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
589 /* PA[35:32] */
590 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
591 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
592 IOP13XX_ATUE_OUMBAR1);
593
594 /* Setup the I/O Bar
595 * A[35-16] in 31-12
596 */
597 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
598 IOP13XX_ATUE_OIOBAR);
599 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
600
601 /* clear startup errors */
602 iop13xx_atue_pci_status(1);
603
604 /* OIOBAR function number
605 */
606 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
607 reg_val &= ~0x7;
608 reg_val |= func;
609 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
610
611 /* OUMBAR function numbers
612 */
613 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
614 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
615 IOP13XX_ATU_OUMBAR_FUNC_NUM);
616 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
617 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
618
619 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
620 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
621 IOP13XX_ATU_OUMBAR_FUNC_NUM);
622 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
623 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
624
625 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
626 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
627 IOP13XX_ATU_OUMBAR_FUNC_NUM);
628 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
629 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
630
631 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
632 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
633 IOP13XX_ATU_OUMBAR_FUNC_NUM);
634 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
635 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
636
637 /* Enable inbound and outbound cycles
638 */
639 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
640 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
641 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
642 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
643
644 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
645 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
646 IOP13XX_ATUE_ATUCR_IVM;
647 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
648 }
649
650 void __init iop13xx_atue_disable(void)
651 {
652 u32 reg_val;
653
654 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
655 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
656
657 /* wait for cycles to quiesce */
658 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
659 IOP13XX_ATUE_PCSR_IN_Q_BUSY |
660 IOP13XX_ATUE_PCSR_LLRB_BUSY))
661 cpu_relax();
662
663 /* BAR 0 ( Disabled ) */
664 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
665 __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
666 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
667 __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
668 __raw_writel(0x0, IOP13XX_ATUE_IALR0);
669 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
670 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
671 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
672
673 /* BAR 1 ( Disabled ) */
674 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
675 __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
676 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
677 __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
678 __raw_writel(0x0, IOP13XX_ATUE_IALR1);
679 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
680 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
681 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
682
683 /* BAR 2 ( Disabled ) */
684 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
685 __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
686 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
687 __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
688 __raw_writel(0x0, IOP13XX_ATUE_IALR2);
689 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
690 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
691 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
692
693 /* BAR 3 ( Disabled ) */
694 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
695 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
696 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
697
698 /* Setup the I/O Bar
699 * A[35-16] in 31-12
700 */
701 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
702 IOP13XX_ATUE_OIOBAR);
703 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
704 }
705
706 /* This function is called from iop13xx_pci_init() after assigning valid
707 * values to iop13xx_atux_pmmr_offset. This is the location for common
708 * setup of ATUX for all IOP13XX implementations.
709 */
710 void __init iop13xx_atux_setup(void)
711 {
712 u32 reg_val;
713 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
714
715 /* Take PCI-X bus out of reset if bootloader hasn't already.
716 * According to spec, we should wait for 2^25 PCI clocks to meet
717 * the PCI timing parameter Trhfa (RST# high to first access).
718 * This is rarely necessary and often ignored.
719 */
720 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
721 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
722 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
723 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
724 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
725 IOP13XX_ATUX_PCSR);
726 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
727 }
728 else
729 atux_trhfa_timeout = jiffies;
730
731 #ifdef CONFIG_PCI_MSI
732 /* BAR 0 (inbound msi window) */
733 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
734 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0);
735 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0);
736 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0);
737 #endif
738
739 /* BAR 1 (1:1 mapping with Physical RAM) */
740 /* Set limit and enable */
741 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
742 IOP13XX_ATUX_IALR1);
743 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
744
745 /* Set base at the top of the reserved address space */
746 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
747 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
748
749 /* 1:1 mapping with physical ram
750 * (leave big endian byte swap disabled)
751 */
752 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
753 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
754
755 /* Outbound window 1 (PCIX/PCIE memory window) */
756 /* 32 bit Address Space */
757 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
758 /* PA[35:32] */
759 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
760 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
761 IOP13XX_ATUX_OUMBAR1);
762
763 /* Setup the I/O Bar
764 * A[35-16] in 31-12
765 */
766 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
767 IOP13XX_ATUX_OIOBAR);
768 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
769
770 /* clear startup errors */
771 iop13xx_atux_pci_status(1);
772
773 /* OIOBAR function number
774 */
775 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
776 reg_val &= ~0x7;
777 reg_val |= func;
778 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
779
780 /* OUMBAR function numbers
781 */
782 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
783 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
784 IOP13XX_ATU_OUMBAR_FUNC_NUM);
785 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
786 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
787
788 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
789 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
790 IOP13XX_ATU_OUMBAR_FUNC_NUM);
791 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
792 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
793
794 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
795 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
796 IOP13XX_ATU_OUMBAR_FUNC_NUM);
797 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
798 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
799
800 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
801 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
802 IOP13XX_ATU_OUMBAR_FUNC_NUM);
803 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
804 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
805
806 /* Enable inbound and outbound cycles
807 */
808 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
809 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
810 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
811 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
812
813 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
814 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
815 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
816 }
817
818 void __init iop13xx_atux_disable(void)
819 {
820 u32 reg_val;
821
822 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
823 __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
824
825 /* wait for cycles to quiesce */
826 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
827 IOP13XX_ATUX_PCSR_IN_Q_BUSY))
828 cpu_relax();
829
830 /* BAR 0 ( Disabled ) */
831 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
832 __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
833 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
834 __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
835 __raw_writel(0x0, IOP13XX_ATUX_IALR0);
836 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
837 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
838 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
839
840 /* BAR 1 ( Disabled ) */
841 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
842 __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
843 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
844 __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
845 __raw_writel(0x0, IOP13XX_ATUX_IALR1);
846 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
847 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
848 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
849
850 /* BAR 2 ( Disabled ) */
851 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
852 __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
853 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
854 __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
855 __raw_writel(0x0, IOP13XX_ATUX_IALR2);
856 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
857 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
858 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
859
860 /* BAR 3 ( Disabled ) */
861 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
862 __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
863 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
864 __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
865 __raw_writel(0x0, IOP13XX_ATUX_IALR3);
866 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
867 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
868 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
869
870 /* Setup the I/O Bar
871 * A[35-16] in 31-12
872 */
873 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
874 IOP13XX_ATUX_OIOBAR);
875 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
876 }
877
878 void __init iop13xx_set_atu_mmr_bases(void)
879 {
880 /* Based on ESSR0, determine the ATU X/E offsets */
881 switch(__raw_readl(IOP13XX_ESSR0) &
882 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
883 /* both asserted */
884 case 0:
885 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
886 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
887 break;
888 /* IOP13XX_CONTROLLER_ONLY = deasserted
889 * IOP13XX_INTERFACE_SEL_PCIX = asserted
890 */
891 case IOP13XX_CONTROLLER_ONLY:
892 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
893 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
894 break;
895 /* IOP13XX_CONTROLLER_ONLY = asserted
896 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
897 */
898 case IOP13XX_INTERFACE_SEL_PCIX:
899 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
900 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
901 break;
902 /* both deasserted */
903 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
904 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
905 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
906 break;
907 default:
908 BUG();
909 }
910 }
911
912 void __init iop13xx_atu_select(struct hw_pci *plat_pci)
913 {
914 int i;
915
916 /* set system defaults
917 * note: if "iop13xx_init_atu=" is specified this autodetect
918 * sequence will be bypassed
919 */
920 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
921 /* check for single/dual interface */
922 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
923 /* ATUE must be present check the device id
924 * to see if ATUX is present.
925 */
926 init_atu |= IOP13XX_INIT_ATU_ATUE;
927 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
928 case 0x70:
929 case 0x80:
930 case 0xc0:
931 init_atu |= IOP13XX_INIT_ATU_ATUX;
932 break;
933 }
934 } else {
935 /* ATUX must be present check the device id
936 * to see if ATUE is present.
937 */
938 init_atu |= IOP13XX_INIT_ATU_ATUX;
939 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
940 case 0x70:
941 case 0x80:
942 case 0xc0:
943 init_atu |= IOP13XX_INIT_ATU_ATUE;
944 break;
945 }
946 }
947
948 /* check central resource and root complex capability */
949 if (init_atu & IOP13XX_INIT_ATU_ATUX)
950 if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
951 IOP13XX_ATUX_PCSR_CENTRAL_RES))
952 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
953
954 if (init_atu & IOP13XX_INIT_ATU_ATUE)
955 if (__raw_readl(IOP13XX_ATUE_PCSR) &
956 IOP13XX_ATUE_PCSR_END_POINT)
957 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
958 }
959
960 for (i = 0; i < 2; i++) {
961 if((init_atu & (1 << i)) == (1 << i))
962 plat_pci->nr_controllers++;
963 }
964 }
965
966 void __init iop13xx_pci_init(void)
967 {
968 /* clear pre-existing south bridge errors */
969 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
970
971 /* Setup the Min Address for PCI memory... */
972 pcibios_min_io = 0;
973 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
974
975 /* if Linux is given control of an ATU
976 * clear out its prior configuration,
977 * otherwise do not touch the registers
978 */
979 if (init_atu & IOP13XX_INIT_ATU_ATUE) {
980 iop13xx_atue_disable();
981 iop13xx_atue_setup();
982 }
983
984 if (init_atu & IOP13XX_INIT_ATU_ATUX) {
985 iop13xx_atux_disable();
986 iop13xx_atux_setup();
987 }
988
989 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
990 "imprecise external abort");
991 }
992
993 /* initialize the pci memory space. handle any combination of
994 * atue and atux enabled/disabled
995 */
996 int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
997 {
998 struct resource *res;
999 int which_atu;
1000 u32 pcixsr, pcsr;
1001
1002 if (nr > 1)
1003 return 0;
1004
1005 res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
1006 if (!res)
1007 panic("PCI: unable to alloc resources");
1008
1009
1010 /* 'nr' assumptions:
1011 * ATUX is always 0
1012 * ATUE is 1 when ATUX is also enabled
1013 * ATUE is 0 when ATUX is disabled
1014 */
1015 switch(init_atu) {
1016 case IOP13XX_INIT_ATU_ATUX:
1017 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1018 break;
1019 case IOP13XX_INIT_ATU_ATUE:
1020 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1021 break;
1022 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1023 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1024 break;
1025 default:
1026 which_atu = 0;
1027 }
1028
1029 if (!which_atu) {
1030 kfree(res);
1031 return 0;
1032 }
1033
1034 switch(which_atu) {
1035 case IOP13XX_INIT_ATU_ATUX:
1036 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1037 pcixsr &= ~0xffff;
1038 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1039 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1040 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1041 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1042 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1043
1044 res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
1045 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
1046 res[0].name = "IQ81340 ATUX PCI I/O Space";
1047 res[0].flags = IORESOURCE_IO;
1048
1049 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
1050 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA;
1051 res[1].name = "IQ81340 ATUX PCI Memory Space";
1052 res[1].flags = IORESOURCE_MEM;
1053 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1054 sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
1055 break;
1056 case IOP13XX_INIT_ATU_ATUE:
1057 /* Note: the function number field in the PCSR is ro */
1058 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1059 pcsr &= ~(0xfff8 << 16);
1060 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1061 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1062
1063 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1064
1065 res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
1066 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
1067 res[0].name = "IQ81340 ATUE PCI I/O Space";
1068 res[0].flags = IORESOURCE_IO;
1069
1070 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
1071 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA;
1072 res[1].name = "IQ81340 ATUE PCI Memory Space";
1073 res[1].flags = IORESOURCE_MEM;
1074 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1075 sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
1076 sys->map_irq = iop13xx_pcie_map_irq;
1077 break;
1078 default:
1079 kfree(res);
1080 return 0;
1081 }
1082
1083 request_resource(&ioport_resource, &res[0]);
1084 request_resource(&iomem_resource, &res[1]);
1085
1086 sys->resource[0] = &res[0];
1087 sys->resource[1] = &res[1];
1088 sys->resource[2] = NULL;
1089
1090 return 1;
1091 }
1092
1093 u16 iop13xx_dev_id(void)
1094 {
1095 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1096 return __raw_readw(IOP13XX_ATUE_DID);
1097 else
1098 return __raw_readw(IOP13XX_ATUX_DID);
1099 }
1100
1101 static int __init iop13xx_init_atu_setup(char *str)
1102 {
1103 init_atu = IOP13XX_INIT_ATU_NONE;
1104 if (str) {
1105 while (*str != '\0') {
1106 switch (*str) {
1107 case 'x':
1108 case 'X':
1109 init_atu |= IOP13XX_INIT_ATU_ATUX;
1110 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1111 break;
1112 case 'e':
1113 case 'E':
1114 init_atu |= IOP13XX_INIT_ATU_ATUE;
1115 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1116 break;
1117 case ',':
1118 case '=':
1119 break;
1120 default:
1121 PRINTK("\"iop13xx_init_atu\" malformed at "
1122 "character: \'%c\'", *str);
1123 *(str + 1) = '\0';
1124 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1125 }
1126 str++;
1127 }
1128 }
1129 return 1;
1130 }
1131
1132 __setup("iop13xx_init_atu", iop13xx_init_atu_setup);