drivers/usb/host/alchemy-common.c

   1 /*
   2  * USB block power/access management abstraction.
   3  *
   4  * Au1000+: The OHCI block control register is at the far end of the OHCI memory
   5  *          area. Au1550 has OHCI on different base address. No need to handle
   6  *          UDC here.
   7  * Au1200:  one register to control access and clocks to O/EHCI, UDC and OTG
   8  *          as well as the PHY for EHCI and UDC.
   9  *
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/syscore_ops.h>
  17 #include <asm/mach-au1x00/au1000.h>
  18
  19 /* control register offsets */
  20 #define AU1000_OHCICFG  0x7fffc
  21 #define AU1550_OHCICFG  0x07ffc
  22 #define AU1200_USBCFG   0x04
  23
  24 /* Au1000 USB block config bits */
  25 #define USBHEN_RD       (1 << 4)                /* OHCI reset-done indicator */
  26 #define USBHEN_CE       (1 << 3)                /* OHCI block clock enable */
  27 #define USBHEN_E        (1 << 2)                /* OHCI block enable */
  28 #define USBHEN_C        (1 << 1)                /* OHCI block coherency bit */
  29 #define USBHEN_BE       (1 << 0)                /* OHCI Big-Endian */
  30
  31 /* Au1200 USB config bits */
  32 #define USBCFG_PFEN     (1 << 31)               /* prefetch enable (undoc) */
  33 #define USBCFG_RDCOMB   (1 << 30)               /* read combining (undoc) */
  34 #define USBCFG_UNKNOWN  (5 << 20)               /* unknown, leave this way */
  35 #define USBCFG_SSD      (1 << 23)               /* serial short detect en */
  36 #define USBCFG_PPE      (1 << 19)               /* HS PHY PLL */
  37 #define USBCFG_UCE      (1 << 18)               /* UDC clock enable */
  38 #define USBCFG_ECE      (1 << 17)               /* EHCI clock enable */
  39 #define USBCFG_OCE      (1 << 16)               /* OHCI clock enable */
  40 #define USBCFG_FLA(x)   (((x) & 0x3f) << 8)
  41 #define USBCFG_UCAM     (1 << 7)                /* coherent access (undoc) */
  42 #define USBCFG_GME      (1 << 6)                /* OTG mem access */
  43 #define USBCFG_DBE      (1 << 5)                /* UDC busmaster enable */
  44 #define USBCFG_DME      (1 << 4)                /* UDC mem enable */
  45 #define USBCFG_EBE      (1 << 3)                /* EHCI busmaster enable */
  46 #define USBCFG_EME      (1 << 2)                /* EHCI mem enable */
  47 #define USBCFG_OBE      (1 << 1)                /* OHCI busmaster enable */
  48 #define USBCFG_OME      (1 << 0)                /* OHCI mem enable */
  49 #define USBCFG_INIT_AU1200      (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
  50                                  USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
  51                                  USBCFG_GME | USBCFG_DBE | USBCFG_DME |        \
  52                                  USBCFG_EBE | USBCFG_EME | USBCFG_OBE |        \
  53                                  USBCFG_OME)
  54
  55
  56 static DEFINE_SPINLOCK(alchemy_usb_lock);
  57
  58
  59 static inline void __au1200_ohci_control(void __iomem *base, int enable)
  60 {
  61         unsigned long r = __raw_readl(base + AU1200_USBCFG);
  62         if (enable) {
  63                 __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
  64                 wmb();
  65                 udelay(2000);
  66         } else {
  67                 __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
  68                 wmb();
  69                 udelay(1000);
  70         }
  71 }
  72
  73 static inline void __au1200_ehci_control(void __iomem *base, int enable)
  74 {
  75         unsigned long r = __raw_readl(base + AU1200_USBCFG);
  76         if (enable) {
  77                 __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
  78                 wmb();
  79                 udelay(1000);
  80         } else {
  81                 if (!(r & USBCFG_UCE))          /* UDC also off? */
  82                         r &= ~USBCFG_PPE;       /* yes: disable HS PHY PLL */
  83                 __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
  84                 wmb();
  85                 udelay(1000);
  86         }
  87 }
  88
  89 static inline void __au1200_udc_control(void __iomem *base, int enable)
  90 {
  91         unsigned long r = __raw_readl(base + AU1200_USBCFG);
  92         if (enable) {
  93                 __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
  94                 wmb();
  95         } else {
  96                 if (!(r & USBCFG_ECE))          /* EHCI also off? */
  97                         r &= ~USBCFG_PPE;       /* yes: disable HS PHY PLL */
  98                 __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
  99                 wmb();
 100         }
 101 }
 102
 103 static inline int au1200_coherency_bug(void)
 104 {
 105 #if defined(CONFIG_DMA_COHERENT)
 106         /* Au1200 AB USB does not support coherent memory */
 107         if (!(read_c0_prid() & 0xff)) {
 108                 printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
 109                 printk(KERN_INFO "Au1200 USB: update your board or re-configure"
 110                                  " the kernel\n");
 111                 return -ENODEV;
 112         }
 113 #endif
 114         return 0;
 115 }
 116
 117 static inline int au1200_usb_control(int block, int enable)
 118 {
 119         void __iomem *base =
 120                         (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
 121         int ret = 0;
 122
 123         switch (block) {
 124         case ALCHEMY_USB_OHCI0:
 125                 ret = au1200_coherency_bug();
 126                 if (ret && enable)
 127                         goto out;
 128                 __au1200_ohci_control(base, enable);
 129                 break;
 130         case ALCHEMY_USB_UDC0:
 131                 __au1200_udc_control(base, enable);
 132                 break;
 133         case ALCHEMY_USB_EHCI0:
 134                 ret = au1200_coherency_bug();
 135                 if (ret && enable)
 136                         goto out;
 137                 __au1200_ehci_control(base, enable);
 138                 break;
 139         default:
 140                 ret = -ENODEV;
 141         }
 142 out:
 143         return ret;
 144 }
 145
 146
 147 /* initialize USB block(s) to a known working state */
 148 static inline void au1200_usb_init(void)
 149 {
 150         void __iomem *base =
 151                         (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
 152         __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
 153         wmb();
 154         udelay(1000);
 155 }
 156
 157 static inline void au1000_usb_init(unsigned long rb, int reg)
 158 {
 159         void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
 160         unsigned long r = __raw_readl(base);
 161
 162 #if defined(__BIG_ENDIAN)
 163         r |= USBHEN_BE;
 164 #endif
 165         r |= USBHEN_C;
 166
 167         __raw_writel(r, base);
 168         wmb();
 169         udelay(1000);
 170 }
 171
 172
 173 static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
 174 {
 175         void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
 176         unsigned long r = __raw_readl(base + creg);
 177
 178         if (enable) {
 179                 __raw_writel(r | USBHEN_CE, base + creg);
 180                 wmb();
 181                 udelay(1000);
 182                 __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
 183                 wmb();
 184                 udelay(1000);
 185
 186                 /* wait for reset complete (read reg twice: au1500 erratum) */
 187                 while (__raw_readl(base + creg),
 188                         !(__raw_readl(base + creg) & USBHEN_RD))
 189                         udelay(1000);
 190         } else {
 191                 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
 192                 wmb();
 193         }
 194 }
 195
 196 static inline int au1000_usb_control(int block, int enable, unsigned long rb,
 197                                      int creg)
 198 {
 199         int ret = 0;
 200
 201         switch (block) {
 202         case ALCHEMY_USB_OHCI0:
 203                 __au1xx0_ohci_control(enable, rb, creg);
 204                 break;
 205         default:
 206                 ret = -ENODEV;
 207         }
 208         return ret;
 209 }
 210
 211 /*
 212  * alchemy_usb_control - control Alchemy on-chip USB blocks
 213  * @block:      USB block to target
 214  * @enable:     set 1 to enable a block, 0 to disable
 215  */
 216 int alchemy_usb_control(int block, int enable)
 217 {
 218         unsigned long flags;
 219         int ret;
 220
 221         spin_lock_irqsave(&alchemy_usb_lock, flags);
 222         switch (alchemy_get_cputype()) {
 223         case ALCHEMY_CPU_AU1000:
 224         case ALCHEMY_CPU_AU1500:
 225         case ALCHEMY_CPU_AU1100:
 226                 ret = au1000_usb_control(block, enable,
 227                                 AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
 228                 break;
 229         case ALCHEMY_CPU_AU1550:
 230                 ret = au1000_usb_control(block, enable,
 231                                 AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
 232                 break;
 233         case ALCHEMY_CPU_AU1200:
 234                 ret = au1200_usb_control(block, enable);
 235                 break;
 236         default:
 237                 ret = -ENODEV;
 238         }
 239         spin_unlock_irqrestore(&alchemy_usb_lock, flags);
 240         return ret;
 241 }
 242 EXPORT_SYMBOL_GPL(alchemy_usb_control);
 243
 244
 245 static unsigned long alchemy_usb_pmdata[2];
 246
 247 static void au1000_usb_pm(unsigned long br, int creg, int susp)
 248 {
 249         void __iomem *base = (void __iomem *)KSEG1ADDR(br);
 250
 251         if (susp) {
 252                 alchemy_usb_pmdata[0] = __raw_readl(base + creg);
 253                 /* There appears to be some undocumented reset register.... */
 254                 __raw_writel(0, base + 0x04);
 255                 wmb();
 256                 __raw_writel(0, base + creg);
 257                 wmb();
 258         } else {
 259                 __raw_writel(alchemy_usb_pmdata[0], base + creg);
 260                 wmb();
 261         }
 262 }
 263
 264 static void au1200_usb_pm(int susp)
 265 {
 266         void __iomem *base =
 267                         (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
 268         if (susp) {
 269                 /* save OTG_CAP/MUX registers which indicate port routing */
 270                 /* FIXME: write an OTG driver to do that */
 271                 alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
 272                 alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
 273         } else {
 274                 /* restore access to all MMIO areas */
 275                 au1200_usb_init();
 276
 277                 /* restore OTG_CAP/MUX registers */
 278                 __raw_writel(alchemy_usb_pmdata[0], base + 0x00);
 279                 __raw_writel(alchemy_usb_pmdata[1], base + 0x04);
 280                 wmb();
 281         }
 282 }
 283
 284 static void alchemy_usb_pm(int susp)
 285 {
 286         switch (alchemy_get_cputype()) {
 287         case ALCHEMY_CPU_AU1000:
 288         case ALCHEMY_CPU_AU1500:
 289         case ALCHEMY_CPU_AU1100:
 290                 au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
 291                 break;
 292         case ALCHEMY_CPU_AU1550:
 293                 au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
 294                 break;
 295         case ALCHEMY_CPU_AU1200:
 296                 au1200_usb_pm(susp);
 297                 break;
 298         }
 299 }
 300
 301 static int alchemy_usb_suspend(void)
 302 {
 303         alchemy_usb_pm(1);
 304         return 0;
 305 }
 306
 307 static void alchemy_usb_resume(void)
 308 {
 309         alchemy_usb_pm(0);
 310 }
 311
 312 static struct syscore_ops alchemy_usb_pm_ops = {
 313         .suspend        = alchemy_usb_suspend,
 314         .resume         = alchemy_usb_resume,
 315 };
 316
 317 static int __init alchemy_usb_init(void)
 318 {
 319         switch (alchemy_get_cputype()) {
 320         case ALCHEMY_CPU_AU1000:
 321         case ALCHEMY_CPU_AU1500:
 322         case ALCHEMY_CPU_AU1100:
 323                 au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
 324                 break;
 325         case ALCHEMY_CPU_AU1550:
 326                 au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
 327                 break;
 328         case ALCHEMY_CPU_AU1200:
 329                 au1200_usb_init();
 330                 break;
 331         }
 332
 333         register_syscore_ops(&alchemy_usb_pm_ops);
 334
 335         return 0;
 336 }
 337 arch_initcall(alchemy_usb_init);