i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / acpi / acpica / hwregs.c
blob4ea4eeb51bfdf588dcbc14e5b8830060e7a42378
2 /*******************************************************************************
4 * Module Name: hwregs - Read/write access functions for the various ACPI
5 * control and status registers.
7 ******************************************************************************/
9 /*
10 * Copyright (C) 2000 - 2012, Intel Corp.
11 * All rights reserved.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions, and the following disclaimer,
18 * without modification.
19 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
20 * substantially similar to the "NO WARRANTY" disclaimer below
21 * ("Disclaimer") and any redistribution must be conditioned upon
22 * including a substantially similar Disclaimer requirement for further
23 * binary redistribution.
24 * 3. Neither the names of the above-listed copyright holders nor the names
25 * of any contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
28 * Alternatively, this software may be distributed under the terms of the
29 * GNU General Public License ("GPL") version 2 as published by the Free
30 * Software Foundation.
32 * NO WARRANTY
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
42 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 * POSSIBILITY OF SUCH DAMAGES.
46 #include <acpi/acpi.h>
47 #include "accommon.h"
48 #include "acnamesp.h"
49 #include "acevents.h"
51 #define _COMPONENT ACPI_HARDWARE
52 ACPI_MODULE_NAME("hwregs")
54 /* Local Prototypes */
55 static acpi_status
56 acpi_hw_read_multiple(u32 *value,
57 struct acpi_generic_address *register_a,
58 struct acpi_generic_address *register_b);
60 static acpi_status
61 acpi_hw_write_multiple(u32 value,
62 struct acpi_generic_address *register_a,
63 struct acpi_generic_address *register_b);
65 /******************************************************************************
67 * FUNCTION: acpi_hw_validate_register
69 * PARAMETERS: Reg - GAS register structure
70 * max_bit_width - Max bit_width supported (32 or 64)
71 * Address - Pointer to where the gas->address
72 * is returned
74 * RETURN: Status
76 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS
77 * pointer, Address, space_id, bit_width, and bit_offset.
79 ******************************************************************************/
81 acpi_status
82 acpi_hw_validate_register(struct acpi_generic_address *reg,
83 u8 max_bit_width, u64 *address)
86 /* Must have a valid pointer to a GAS structure */
88 if (!reg) {
89 return (AE_BAD_PARAMETER);
93 * Copy the target address. This handles possible alignment issues.
94 * Address must not be null. A null address also indicates an optional
95 * ACPI register that is not supported, so no error message.
97 ACPI_MOVE_64_TO_64(address, &reg->address);
98 if (!(*address)) {
99 return (AE_BAD_ADDRESS);
102 /* Validate the space_iD */
104 if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
105 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
106 ACPI_ERROR((AE_INFO,
107 "Unsupported address space: 0x%X", reg->space_id));
108 return (AE_SUPPORT);
111 /* Validate the bit_width */
113 if ((reg->bit_width != 8) &&
114 (reg->bit_width != 16) &&
115 (reg->bit_width != 32) && (reg->bit_width != max_bit_width)) {
116 ACPI_ERROR((AE_INFO,
117 "Unsupported register bit width: 0x%X",
118 reg->bit_width));
119 return (AE_SUPPORT);
122 /* Validate the bit_offset. Just a warning for now. */
124 if (reg->bit_offset != 0) {
125 ACPI_WARNING((AE_INFO,
126 "Unsupported register bit offset: 0x%X",
127 reg->bit_offset));
130 return (AE_OK);
133 /******************************************************************************
135 * FUNCTION: acpi_hw_read
137 * PARAMETERS: Value - Where the value is returned
138 * Reg - GAS register structure
140 * RETURN: Status
142 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max
143 * version of acpi_read, used internally since the overhead of
144 * 64-bit values is not needed.
146 * LIMITATIONS: <These limitations also apply to acpi_hw_write>
147 * bit_width must be exactly 8, 16, or 32.
148 * space_iD must be system_memory or system_iO.
149 * bit_offset and access_width are currently ignored, as there has
150 * not been a need to implement these.
152 ******************************************************************************/
154 acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
156 u64 address;
157 acpi_status status;
159 ACPI_FUNCTION_NAME(hw_read);
161 /* Validate contents of the GAS register */
163 status = acpi_hw_validate_register(reg, 32, &address);
164 if (ACPI_FAILURE(status)) {
165 return (status);
168 /* Initialize entire 32-bit return value to zero */
170 *value = 0;
173 * Two address spaces supported: Memory or IO. PCI_Config is
174 * not supported here because the GAS structure is insufficient
176 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
177 status = acpi_os_read_memory((acpi_physical_address)
178 address, value, reg->bit_width);
179 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
181 status = acpi_hw_read_port((acpi_io_address)
182 address, value, reg->bit_width);
185 ACPI_DEBUG_PRINT((ACPI_DB_IO,
186 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n",
187 *value, reg->bit_width, ACPI_FORMAT_UINT64(address),
188 acpi_ut_get_region_name(reg->space_id)));
190 return (status);
193 /******************************************************************************
195 * FUNCTION: acpi_hw_write
197 * PARAMETERS: Value - Value to be written
198 * Reg - GAS register structure
200 * RETURN: Status
202 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max
203 * version of acpi_write, used internally since the overhead of
204 * 64-bit values is not needed.
206 ******************************************************************************/
208 acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
210 u64 address;
211 acpi_status status;
213 ACPI_FUNCTION_NAME(hw_write);
215 /* Validate contents of the GAS register */
217 status = acpi_hw_validate_register(reg, 32, &address);
218 if (ACPI_FAILURE(status)) {
219 return (status);
223 * Two address spaces supported: Memory or IO. PCI_Config is
224 * not supported here because the GAS structure is insufficient
226 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
227 status = acpi_os_write_memory((acpi_physical_address)
228 address, value, reg->bit_width);
229 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
231 status = acpi_hw_write_port((acpi_io_address)
232 address, value, reg->bit_width);
235 ACPI_DEBUG_PRINT((ACPI_DB_IO,
236 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
237 value, reg->bit_width, ACPI_FORMAT_UINT64(address),
238 acpi_ut_get_region_name(reg->space_id)));
240 return (status);
243 /*******************************************************************************
245 * FUNCTION: acpi_hw_clear_acpi_status
247 * PARAMETERS: None
249 * RETURN: Status
251 * DESCRIPTION: Clears all fixed and general purpose status bits
253 ******************************************************************************/
255 acpi_status acpi_hw_clear_acpi_status(void)
257 acpi_status status;
258 acpi_cpu_flags lock_flags = 0;
260 ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
262 ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
263 ACPI_BITMASK_ALL_FIXED_STATUS,
264 ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address)));
266 lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock);
268 /* Clear the fixed events in PM1 A/B */
270 status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
271 ACPI_BITMASK_ALL_FIXED_STATUS);
273 acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags);
275 if (ACPI_FAILURE(status))
276 goto exit;
278 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
280 status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
282 exit:
283 return_ACPI_STATUS(status);
286 /*******************************************************************************
288 * FUNCTION: acpi_hw_get_register_bit_mask
290 * PARAMETERS: register_id - Index of ACPI Register to access
292 * RETURN: The bitmask to be used when accessing the register
294 * DESCRIPTION: Map register_id into a register bitmask.
296 ******************************************************************************/
298 struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
300 ACPI_FUNCTION_ENTRY();
302 if (register_id > ACPI_BITREG_MAX) {
303 ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: 0x%X",
304 register_id));
305 return (NULL);
308 return (&acpi_gbl_bit_register_info[register_id]);
311 /******************************************************************************
313 * FUNCTION: acpi_hw_write_pm1_control
315 * PARAMETERS: pm1a_control - Value to be written to PM1A control
316 * pm1b_control - Value to be written to PM1B control
318 * RETURN: Status
320 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
321 * different than than the PM1 A/B status and enable registers
322 * in that different values can be written to the A/B registers.
323 * Most notably, the SLP_TYP bits can be different, as per the
324 * values returned from the _Sx predefined methods.
326 ******************************************************************************/
328 acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)
330 acpi_status status;
332 ACPI_FUNCTION_TRACE(hw_write_pm1_control);
334 status =
335 acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);
336 if (ACPI_FAILURE(status)) {
337 return_ACPI_STATUS(status);
340 if (acpi_gbl_FADT.xpm1b_control_block.address) {
341 status =
342 acpi_hw_write(pm1b_control,
343 &acpi_gbl_FADT.xpm1b_control_block);
345 return_ACPI_STATUS(status);
348 /******************************************************************************
350 * FUNCTION: acpi_hw_register_read
352 * PARAMETERS: register_id - ACPI Register ID
353 * return_value - Where the register value is returned
355 * RETURN: Status and the value read.
357 * DESCRIPTION: Read from the specified ACPI register
359 ******************************************************************************/
360 acpi_status
361 acpi_hw_register_read(u32 register_id, u32 * return_value)
363 u32 value = 0;
364 acpi_status status;
366 ACPI_FUNCTION_TRACE(hw_register_read);
368 switch (register_id) {
369 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
371 status = acpi_hw_read_multiple(&value,
372 &acpi_gbl_xpm1a_status,
373 &acpi_gbl_xpm1b_status);
374 break;
376 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
378 status = acpi_hw_read_multiple(&value,
379 &acpi_gbl_xpm1a_enable,
380 &acpi_gbl_xpm1b_enable);
381 break;
383 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
385 status = acpi_hw_read_multiple(&value,
386 &acpi_gbl_FADT.
387 xpm1a_control_block,
388 &acpi_gbl_FADT.
389 xpm1b_control_block);
392 * Zero the write-only bits. From the ACPI specification, "Hardware
393 * Write-Only Bits": "Upon reads to registers with write-only bits,
394 * software masks out all write-only bits."
396 value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
397 break;
399 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
401 status =
402 acpi_hw_read(&value, &acpi_gbl_FADT.xpm2_control_block);
403 break;
405 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
407 status = acpi_hw_read(&value, &acpi_gbl_FADT.xpm_timer_block);
408 break;
410 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
412 status =
413 acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8);
414 break;
416 default:
417 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
418 status = AE_BAD_PARAMETER;
419 break;
422 if (ACPI_SUCCESS(status)) {
423 *return_value = value;
426 return_ACPI_STATUS(status);
429 /******************************************************************************
431 * FUNCTION: acpi_hw_register_write
433 * PARAMETERS: register_id - ACPI Register ID
434 * Value - The value to write
436 * RETURN: Status
438 * DESCRIPTION: Write to the specified ACPI register
440 * NOTE: In accordance with the ACPI specification, this function automatically
441 * preserves the value of the following bits, meaning that these bits cannot be
442 * changed via this interface:
444 * PM1_CONTROL[0] = SCI_EN
445 * PM1_CONTROL[9]
446 * PM1_STATUS[11]
448 * ACPI References:
449 * 1) Hardware Ignored Bits: When software writes to a register with ignored
450 * bit fields, it preserves the ignored bit fields
451 * 2) SCI_EN: OSPM always preserves this bit position
453 ******************************************************************************/
455 acpi_status acpi_hw_register_write(u32 register_id, u32 value)
457 acpi_status status;
458 u32 read_value;
460 ACPI_FUNCTION_TRACE(hw_register_write);
462 switch (register_id) {
463 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
465 * Handle the "ignored" bit in PM1 Status. According to the ACPI
466 * specification, ignored bits are to be preserved when writing.
467 * Normally, this would mean a read/modify/write sequence. However,
468 * preserving a bit in the status register is different. Writing a
469 * one clears the status, and writing a zero preserves the status.
470 * Therefore, we must always write zero to the ignored bit.
472 * This behavior is clarified in the ACPI 4.0 specification.
474 value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
476 status = acpi_hw_write_multiple(value,
477 &acpi_gbl_xpm1a_status,
478 &acpi_gbl_xpm1b_status);
479 break;
481 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access */
483 status = acpi_hw_write_multiple(value,
484 &acpi_gbl_xpm1a_enable,
485 &acpi_gbl_xpm1b_enable);
486 break;
488 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
491 * Perform a read first to preserve certain bits (per ACPI spec)
492 * Note: This includes SCI_EN, we never want to change this bit
494 status = acpi_hw_read_multiple(&read_value,
495 &acpi_gbl_FADT.
496 xpm1a_control_block,
497 &acpi_gbl_FADT.
498 xpm1b_control_block);
499 if (ACPI_FAILURE(status)) {
500 goto exit;
503 /* Insert the bits to be preserved */
505 ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
506 read_value);
508 /* Now we can write the data */
510 status = acpi_hw_write_multiple(value,
511 &acpi_gbl_FADT.
512 xpm1a_control_block,
513 &acpi_gbl_FADT.
514 xpm1b_control_block);
515 break;
517 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
520 * For control registers, all reserved bits must be preserved,
521 * as per the ACPI spec.
523 status =
524 acpi_hw_read(&read_value,
525 &acpi_gbl_FADT.xpm2_control_block);
526 if (ACPI_FAILURE(status)) {
527 goto exit;
530 /* Insert the bits to be preserved */
532 ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS,
533 read_value);
535 status =
536 acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block);
537 break;
539 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
541 status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block);
542 break;
544 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
546 /* SMI_CMD is currently always in IO space */
548 status =
549 acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8);
550 break;
552 default:
553 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
554 status = AE_BAD_PARAMETER;
555 break;
558 exit:
559 return_ACPI_STATUS(status);
562 /******************************************************************************
564 * FUNCTION: acpi_hw_read_multiple
566 * PARAMETERS: Value - Where the register value is returned
567 * register_a - First ACPI register (required)
568 * register_b - Second ACPI register (optional)
570 * RETURN: Status
572 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
574 ******************************************************************************/
576 static acpi_status
577 acpi_hw_read_multiple(u32 *value,
578 struct acpi_generic_address *register_a,
579 struct acpi_generic_address *register_b)
581 u32 value_a = 0;
582 u32 value_b = 0;
583 acpi_status status;
585 /* The first register is always required */
587 status = acpi_hw_read(&value_a, register_a);
588 if (ACPI_FAILURE(status)) {
589 return (status);
592 /* Second register is optional */
594 if (register_b->address) {
595 status = acpi_hw_read(&value_b, register_b);
596 if (ACPI_FAILURE(status)) {
597 return (status);
602 * OR the two return values together. No shifting or masking is necessary,
603 * because of how the PM1 registers are defined in the ACPI specification:
605 * "Although the bits can be split between the two register blocks (each
606 * register block has a unique pointer within the FADT), the bit positions
607 * are maintained. The register block with unimplemented bits (that is,
608 * those implemented in the other register block) always returns zeros,
609 * and writes have no side effects"
611 *value = (value_a | value_b);
612 return (AE_OK);
615 /******************************************************************************
617 * FUNCTION: acpi_hw_write_multiple
619 * PARAMETERS: Value - The value to write
620 * register_a - First ACPI register (required)
621 * register_b - Second ACPI register (optional)
623 * RETURN: Status
625 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
627 ******************************************************************************/
629 static acpi_status
630 acpi_hw_write_multiple(u32 value,
631 struct acpi_generic_address *register_a,
632 struct acpi_generic_address *register_b)
634 acpi_status status;
636 /* The first register is always required */
638 status = acpi_hw_write(value, register_a);
639 if (ACPI_FAILURE(status)) {
640 return (status);
644 * Second register is optional
646 * No bit shifting or clearing is necessary, because of how the PM1
647 * registers are defined in the ACPI specification:
649 * "Although the bits can be split between the two register blocks (each
650 * register block has a unique pointer within the FADT), the bit positions
651 * are maintained. The register block with unimplemented bits (that is,
652 * those implemented in the other register block) always returns zeros,
653 * and writes have no side effects"
655 if (register_b->address) {
656 status = acpi_hw_write(value, register_b);
659 return (status);