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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / char / tpm / tpm_nsc.c
blob4d2464871ada87cab9b5beacc1ec817ee5a93d31
1 /*
2 * Copyright (C) 2004 IBM Corporation
3 *
4 * Authors:
5 * Leendert van Doorn <leendert@watson.ibm.com>
6 * Dave Safford <safford@watson.ibm.com>
7 * Reiner Sailer <sailer@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
9 *
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
11 *
12 * Device driver for TCG/TCPA TPM (trusted platform module).
13 * Specifications at www.trustedcomputinggroup.org
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation, version 2 of the
18 * License.
19 *
20 */
21
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include "tpm.h"
25
26 /* National definitions */
27 enum tpm_nsc_addr{
28 TPM_NSC_IRQ = 0x07,
29 TPM_NSC_BASE0_HI = 0x60,
30 TPM_NSC_BASE0_LO = 0x61,
31 TPM_NSC_BASE1_HI = 0x62,
32 TPM_NSC_BASE1_LO = 0x63
33 };
34
35 enum tpm_nsc_index {
36 NSC_LDN_INDEX = 0x07,
37 NSC_SID_INDEX = 0x20,
38 NSC_LDC_INDEX = 0x30,
39 NSC_DIO_INDEX = 0x60,
40 NSC_CIO_INDEX = 0x62,
41 NSC_IRQ_INDEX = 0x70,
42 NSC_ITS_INDEX = 0x71
43 };
44
45 enum tpm_nsc_status_loc {
46 NSC_STATUS = 0x01,
47 NSC_COMMAND = 0x01,
48 NSC_DATA = 0x00
49 };
50
51 /* status bits */
52 enum tpm_nsc_status {
53 NSC_STATUS_OBF = 0x01, /* output buffer full */
54 NSC_STATUS_IBF = 0x02, /* input buffer full */
55 NSC_STATUS_F0 = 0x04, /* F0 */
56 NSC_STATUS_A2 = 0x08, /* A2 */
57 NSC_STATUS_RDY = 0x10, /* ready to receive command */
58 NSC_STATUS_IBR = 0x20 /* ready to receive data */
59 };
60
61 /* command bits */
62 enum tpm_nsc_cmd_mode {
63 NSC_COMMAND_NORMAL = 0x01, /* normal mode */
64 NSC_COMMAND_EOC = 0x03,
65 NSC_COMMAND_CANCEL = 0x22
66 };
67 /*
68 * Wait for a certain status to appear
69 */
70 static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
71 {
72 unsigned long stop;
73
74 /* status immediately available check */
75 *data = inb(chip->vendor.base + NSC_STATUS);
76 if ((*data & mask) == val)
77 return 0;
78
79 /* wait for status */
80 stop = jiffies + 10 * HZ;
81 do {
82 msleep(TPM_TIMEOUT);
83 *data = inb(chip->vendor.base + 1);
84 if ((*data & mask) == val)
85 return 0;
86 }
87 while (time_before(jiffies, stop));
88
89 return -EBUSY;
90 }
91
92 static int nsc_wait_for_ready(struct tpm_chip *chip)
93 {
94 int status;
95 unsigned long stop;
96
97 /* status immediately available check */
98 status = inb(chip->vendor.base + NSC_STATUS);
99 if (status & NSC_STATUS_OBF)
100 status = inb(chip->vendor.base + NSC_DATA);
101 if (status & NSC_STATUS_RDY)
102 return 0;
103
104 /* wait for status */
105 stop = jiffies + 100;
106 do {
107 msleep(TPM_TIMEOUT);
108 status = inb(chip->vendor.base + NSC_STATUS);
109 if (status & NSC_STATUS_OBF)
110 status = inb(chip->vendor.base + NSC_DATA);
111 if (status & NSC_STATUS_RDY)
112 return 0;
113 }
114 while (time_before(jiffies, stop));
115
116 dev_info(chip->dev, "wait for ready failed\n");
117 return -EBUSY;
118 }
119
120
121 static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
122 {
123 u8 *buffer = buf;
124 u8 data, *p;
125 u32 size;
126 __be32 *native_size;
127
128 if (count < 6)
129 return -EIO;
130
131 if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
132 dev_err(chip->dev, "F0 timeout\n");
133 return -EIO;
134 }
135 if ((data =
136 inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
137 dev_err(chip->dev, "not in normal mode (0x%x)\n",
138 data);
139 return -EIO;
140 }
141
142 /* read the whole packet */
143 for (p = buffer; p < &buffer[count]; p++) {
144 if (wait_for_stat
145 (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
146 dev_err(chip->dev,
147 "OBF timeout (while reading data)\n");
148 return -EIO;
149 }
150 if (data & NSC_STATUS_F0)
151 break;
152 *p = inb(chip->vendor.base + NSC_DATA);
153 }
154
155 if ((data & NSC_STATUS_F0) == 0 &&
156 (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
157 dev_err(chip->dev, "F0 not set\n");
158 return -EIO;
159 }
160 if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) {
161 dev_err(chip->dev,
162 "expected end of command(0x%x)\n", data);
163 return -EIO;
164 }
165
166 native_size = (__force __be32 *) (buf + 2);
167 size = be32_to_cpu(*native_size);
168
169 if (count < size)
170 return -EIO;
171
172 return size;
173 }
174
175 static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
176 {
177 u8 data;
178 int i;
179
180 /*
181 * If we hit the chip with back to back commands it locks up
182 * and never set IBF. Hitting it with this "hammer" seems to
183 * fix it. Not sure why this is needed, we followed the flow
184 * chart in the manual to the letter.
185 */
186 outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
187
188 if (nsc_wait_for_ready(chip) != 0)
189 return -EIO;
190
191 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
192 dev_err(chip->dev, "IBF timeout\n");
193 return -EIO;
194 }
195
196 outb(NSC_COMMAND_NORMAL, chip->vendor.base + NSC_COMMAND);
197 if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
198 dev_err(chip->dev, "IBR timeout\n");
199 return -EIO;
200 }
201
202 for (i = 0; i < count; i++) {
203 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
204 dev_err(chip->dev,
205 "IBF timeout (while writing data)\n");
206 return -EIO;
207 }
208 outb(buf[i], chip->vendor.base + NSC_DATA);
209 }
210
211 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
212 dev_err(chip->dev, "IBF timeout\n");
213 return -EIO;
214 }
215 outb(NSC_COMMAND_EOC, chip->vendor.base + NSC_COMMAND);
216
217 return count;
218 }
219
220 static void tpm_nsc_cancel(struct tpm_chip *chip)
221 {
222 outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
223 }
224
225 static u8 tpm_nsc_status(struct tpm_chip *chip)
226 {
227 return inb(chip->vendor.base + NSC_STATUS);
228 }
229
230 static const struct file_operations nsc_ops = {
231 .owner = THIS_MODULE,
232 .llseek = no_llseek,
233 .open = tpm_open,
234 .read = tpm_read,
235 .write = tpm_write,
236 .release = tpm_release,
237 };
238
239 static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
240 static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
241 static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL);
242 static DEVICE_ATTR(cancel, S_IWUSR|S_IWGRP, NULL, tpm_store_cancel);
243
244 static struct attribute * nsc_attrs[] = {
245 &dev_attr_pubek.attr,
246 &dev_attr_pcrs.attr,
247 &dev_attr_caps.attr,
248 &dev_attr_cancel.attr,
249 NULL,
250 };
251
252 static struct attribute_group nsc_attr_grp = { .attrs = nsc_attrs };
253
254 static const struct tpm_vendor_specific tpm_nsc = {
255 .recv = tpm_nsc_recv,
256 .send = tpm_nsc_send,
257 .cancel = tpm_nsc_cancel,
258 .status = tpm_nsc_status,
259 .req_complete_mask = NSC_STATUS_OBF,
260 .req_complete_val = NSC_STATUS_OBF,
261 .req_canceled = NSC_STATUS_RDY,
262 .attr_group = &nsc_attr_grp,
263 .miscdev = { .fops = &nsc_ops, },
264 };
265
266 static struct platform_device *pdev = NULL;
267
268 static void tpm_nsc_remove(struct device *dev)
269 {
270 struct tpm_chip *chip = dev_get_drvdata(dev);
271 if ( chip ) {
272 release_region(chip->vendor.base, 2);
273 tpm_remove_hardware(chip->dev);
274 }
275 }
276
277 static int tpm_nsc_suspend(struct platform_device *dev, pm_message_t msg)
278 {
279 return tpm_pm_suspend(&dev->dev, msg);
280 }
281
282 static int tpm_nsc_resume(struct platform_device *dev)
283 {
284 return tpm_pm_resume(&dev->dev);
285 }
286
287 static struct platform_driver nsc_drv = {
288 .suspend = tpm_nsc_suspend,
289 .resume = tpm_nsc_resume,
290 .driver = {
291 .name = "tpm_nsc",
292 .owner = THIS_MODULE,
293 },
294 };
295
296 static int __init init_nsc(void)
297 {
298 int rc = 0;
299 int lo, hi, err;
300 int nscAddrBase = TPM_ADDR;
301 struct tpm_chip *chip;
302 unsigned long base;
303
304 /* verify that it is a National part (SID) */
305 if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
306 nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
307 (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
308 if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
309 return -ENODEV;
310 }
311
312 err = platform_driver_register(&nsc_drv);
313 if (err)
314 return err;
315
316 hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
317 lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
318 base = (hi<<8) | lo;
319
320 /* enable the DPM module */
321 tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
322
323 pdev = platform_device_alloc("tpm_nscl0", -1);
324 if (!pdev) {
325 rc = -ENOMEM;
326 goto err_unreg_drv;
327 }
328
329 pdev->num_resources = 0;
330 pdev->dev.driver = &nsc_drv.driver;
331 pdev->dev.release = tpm_nsc_remove;
332
333 if ((rc = platform_device_add(pdev)) < 0)
334 goto err_put_dev;
335
336 if (request_region(base, 2, "tpm_nsc0") == NULL ) {
337 rc = -EBUSY;
338 goto err_del_dev;
339 }
340
341 if (!(chip = tpm_register_hardware(&pdev->dev, &tpm_nsc))) {
342 rc = -ENODEV;
343 goto err_rel_reg;
344 }
345
346 dev_dbg(&pdev->dev, "NSC TPM detected\n");
347 dev_dbg(&pdev->dev,
348 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
349 tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
350 tpm_read_index(nscAddrBase,0x27));
351 dev_dbg(&pdev->dev,
352 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
353 tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
354 tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
355 dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
356 (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
357 dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
358 (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
359 dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
360 tpm_read_index(nscAddrBase,0x70));
361 dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
362 tpm_read_index(nscAddrBase,0x71));
363 dev_dbg(&pdev->dev,
364 "NSC DMA channel select0 0x%x, select1 0x%x\n",
365 tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
366 dev_dbg(&pdev->dev,
367 "NSC Config "
368 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
369 tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
370 tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
371 tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
372 tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
373 tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
374
375 dev_info(&pdev->dev,
376 "NSC TPM revision %d\n",
377 tpm_read_index(nscAddrBase, 0x27) & 0x1F);
378
379 chip->vendor.base = base;
380
381 return 0;
382
383 err_rel_reg:
384 release_region(base, 2);
385 err_del_dev:
386 platform_device_del(pdev);
387 err_put_dev:
388 platform_device_put(pdev);
389 err_unreg_drv:
390 platform_driver_unregister(&nsc_drv);
391 return rc;
392 }
393
394 static void __exit cleanup_nsc(void)
395 {
396 if (pdev) {
397 tpm_nsc_remove(&pdev->dev);
398 platform_device_unregister(pdev);
399 }
400
401 platform_driver_unregister(&nsc_drv);
402 }
403
404 module_init(init_nsc);
405 module_exit(cleanup_nsc);
406
407 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
408 MODULE_DESCRIPTION("TPM Driver");
409 MODULE_VERSION("2.0");
410 MODULE_LICENSE("GPL");