drivers/crypto/caam/regs.h

   1 /*
   2  * CAAM hardware register-level view
   3  *
   4  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   5  */
   6
   7 #ifndef REGS_H
   8 #define REGS_H
   9
  10 #include <linux/types.h>
  11 #include <linux/io.h>
  12
  13 /*
  14  * Architecture-specific register access methods
  15  *
  16  * CAAM's bus-addressable registers are 64 bits internally.
  17  * They have been wired to be safely accessible on 32-bit
  18  * architectures, however. Registers were organized such
  19  * that (a) they can be contained in 32 bits, (b) if not, then they
  20  * can be treated as two 32-bit entities, or finally (c) if they
  21  * must be treated as a single 64-bit value, then this can safely
  22  * be done with two 32-bit cycles.
  23  *
  24  * For 32-bit operations on 64-bit values, CAAM follows the same
  25  * 64-bit register access conventions as it's predecessors, in that
  26  * writes are "triggered" by a write to the register at the numerically
  27  * higher address, thus, a full 64-bit write cycle requires a write
  28  * to the lower address, followed by a write to the higher address,
  29  * which will latch/execute the write cycle.
  30  *
  31  * For example, let's assume a SW reset of CAAM through the master
  32  * configuration register.
  33  * - SWRST is in bit 31 of MCFG.
  34  * - MCFG begins at base+0x0000.
  35  * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
  36  * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
  37  *
  38  * (and on Power, the convention is 0-31, 32-63, I know...)
  39  *
  40  * Assuming a 64-bit write to this MCFG to perform a software reset
  41  * would then require a write of 0 to base+0x0000, followed by a
  42  * write of 0x80000000 to base+0x0004, which would "execute" the
  43  * reset.
  44  *
  45  * Of course, since MCFG 63-32 is all zero, we could cheat and simply
  46  * write 0x8000000 to base+0x0004, and the reset would work fine.
  47  * However, since CAAM does contain some write-and-read-intended
  48  * 64-bit registers, this code defines 64-bit access methods for
  49  * the sake of internal consistency and simplicity, and so that a
  50  * clean transition to 64-bit is possible when it becomes necessary.
  51  *
  52  * There are limitations to this that the developer must recognize.
  53  * 32-bit architectures cannot enforce an atomic-64 operation,
  54  * Therefore:
  55  *
  56  * - On writes, since the HW is assumed to latch the cycle on the
  57  *   write of the higher-numeric-address word, then ordered
  58  *   writes work OK.
  59  *
  60  * - For reads, where a register contains a relevant value of more
  61  *   that 32 bits, the hardware employs logic to latch the other
  62  *   "half" of the data until read, ensuring an accurate value.
  63  *   This is of particular relevance when dealing with CAAM's
  64  *   performance counters.
  65  *
  66  */
  67
  68 #ifdef __BIG_ENDIAN
  69 #define wr_reg32(reg, data) out_be32(reg, data)
  70 #define rd_reg32(reg) in_be32(reg)
  71 #ifdef CONFIG_64BIT
  72 #define wr_reg64(reg, data) out_be64(reg, data)
  73 #define rd_reg64(reg) in_be64(reg)
  74 #endif
  75 #else
  76 #ifdef __LITTLE_ENDIAN
  77 #define wr_reg32(reg, data) __raw_writel(reg, data)
  78 #define rd_reg32(reg) __raw_readl(reg)
  79 #ifdef CONFIG_64BIT
  80 #define wr_reg64(reg, data) __raw_writeq(reg, data)
  81 #define rd_reg64(reg) __raw_readq(reg)
  82 #endif
  83 #endif
  84 #endif
  85
  86 #ifndef CONFIG_64BIT
  87 static inline void wr_reg64(u64 __iomem *reg, u64 data)
  88 {
  89         wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
  90         wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull);
  91 }
  92
  93 static inline u64 rd_reg64(u64 __iomem *reg)
  94 {
  95         return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
  96                 ((u64)rd_reg32((u32 __iomem *)reg + 1));
  97 }
  98 #endif
  99
 100 /*
 101  * jr_outentry
 102  * Represents each entry in a JobR output ring
 103  */
 104 struct jr_outentry {
 105         dma_addr_t desc;/* Pointer to completed descriptor */
 106         u32 jrstatus;   /* Status for completed descriptor */
 107 } __packed;
 108
 109 /*
 110  * caam_perfmon - Performance Monitor/Secure Memory Status/
 111  *                CAAM Global Status/Component Version IDs
 112  *
 113  * Spans f00-fff wherever instantiated
 114  */
 115
 116 /* Number of DECOs */
 117 #define CHA_NUM_DECONUM_SHIFT   56
 118 #define CHA_NUM_DECONUM_MASK    (0xfull << CHA_NUM_DECONUM_SHIFT)
 119
 120 struct caam_perfmon {
 121         /* Performance Monitor Registers                        f00-f9f */
 122         u64 req_dequeued;       /* PC_REQ_DEQ - Dequeued Requests            */
 123         u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
 124         u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests  */
 125         u64 ob_enc_bytes;       /* PC_OB_ENCRYPT - Outbound Bytes Encrypted  */
 126         u64 ob_prot_bytes;      /* PC_OB_PROTECT - Outbound Bytes Protected  */
 127         u64 ib_dec_bytes;       /* PC_IB_DECRYPT - Inbound Bytes Decrypted   */
 128         u64 ib_valid_bytes;     /* PC_IB_VALIDATED Inbound Bytes Validated   */
 129         u64 rsvd[13];
 130
 131         /* CAAM Hardware Instantiation Parameters               fa0-fbf */
 132         u64 cha_rev;            /* CRNR - CHA Revision Number           */
 133 #define CTPR_QI_SHIFT           57
 134 #define CTPR_QI_MASK            (0x1ull << CTPR_QI_SHIFT)
 135         u64 comp_parms; /* CTPR - Compile Parameters Register   */
 136         u64 rsvd1[2];
 137
 138         /* CAAM Global Status                                   fc0-fdf */
 139         u64 faultaddr;  /* FAR  - Fault Address         */
 140         u32 faultliodn; /* FALR - Fault Address LIODN   */
 141         u32 faultdetail;        /* FADR - Fault Addr Detail     */
 142         u32 rsvd2;
 143         u32 status;             /* CSTA - CAAM Status */
 144         u64 rsvd3;
 145
 146         /* Component Instantiation Parameters                   fe0-fff */
 147         u32 rtic_id;            /* RVID - RTIC Version ID       */
 148         u32 ccb_id;             /* CCBVID - CCB Version ID      */
 149         u64 cha_id;             /* CHAVID - CHA Version ID      */
 150         u64 cha_num;            /* CHANUM - CHA Number          */
 151         u64 caam_id;            /* CAAMVID - CAAM Version ID    */
 152 };
 153
 154 /* LIODN programming for DMA configuration */
 155 #define MSTRID_LOCK_LIODN       0x80000000
 156 #define MSTRID_LOCK_MAKETRUSTED 0x00010000      /* only for JR masterid */
 157
 158 #define MSTRID_LIODN_MASK       0x0fff
 159 struct masterid {
 160         u32 liodn_ms;   /* lock and make-trusted control bits */
 161         u32 liodn_ls;   /* LIODN for non-sequence and seq access */
 162 };
 163
 164 /* Partition ID for DMA configuration */
 165 struct partid {
 166         u32 rsvd1;
 167         u32 pidr;       /* partition ID, DECO */
 168 };
 169
 170 /* RNG test mode (replicated twice in some configurations) */
 171 /* Padded out to 0x100 */
 172 struct rngtst {
 173         u32 mode;               /* RTSTMODEx - Test mode */
 174         u32 rsvd1[3];
 175         u32 reset;              /* RTSTRESETx - Test reset control */
 176         u32 rsvd2[3];
 177         u32 status;             /* RTSTSSTATUSx - Test status */
 178         u32 rsvd3;
 179         u32 errstat;            /* RTSTERRSTATx - Test error status */
 180         u32 rsvd4;
 181         u32 errctl;             /* RTSTERRCTLx - Test error control */
 182         u32 rsvd5;
 183         u32 entropy;            /* RTSTENTROPYx - Test entropy */
 184         u32 rsvd6[15];
 185         u32 verifctl;   /* RTSTVERIFCTLx - Test verification control */
 186         u32 rsvd7;
 187         u32 verifstat;  /* RTSTVERIFSTATx - Test verification status */
 188         u32 rsvd8;
 189         u32 verifdata;  /* RTSTVERIFDx - Test verification data */
 190         u32 rsvd9;
 191         u32 xkey;               /* RTSTXKEYx - Test XKEY */
 192         u32 rsvd10;
 193         u32 oscctctl;   /* RTSTOSCCTCTLx - Test osc. counter control */
 194         u32 rsvd11;
 195         u32 oscct;              /* RTSTOSCCTx - Test oscillator counter */
 196         u32 rsvd12;
 197         u32 oscctstat;  /* RTSTODCCTSTATx - Test osc counter status */
 198         u32 rsvd13[2];
 199         u32 ofifo[4];   /* RTSTOFIFOx - Test output FIFO */
 200         u32 rsvd14[15];
 201 };
 202
 203 /*
 204  * caam_ctrl - basic core configuration
 205  * starts base + 0x0000 padded out to 0x1000
 206  */
 207
 208 #define KEK_KEY_SIZE            8
 209 #define TKEK_KEY_SIZE           8
 210 #define TDSK_KEY_SIZE           8
 211
 212 #define DECO_RESET      1       /* Use with DECO reset/availability regs */
 213 #define DECO_RESET_0    (DECO_RESET << 0)
 214 #define DECO_RESET_1    (DECO_RESET << 1)
 215 #define DECO_RESET_2    (DECO_RESET << 2)
 216 #define DECO_RESET_3    (DECO_RESET << 3)
 217 #define DECO_RESET_4    (DECO_RESET << 4)
 218
 219 struct caam_ctrl {
 220         /* Basic Configuration Section                          000-01f */
 221         /* Read/Writable                                                */
 222         u32 rsvd1;
 223         u32 mcr;                /* MCFG      Master Config Register  */
 224         u32 rsvd2[2];
 225
 226         /* Bus Access Configuration Section                     010-11f */
 227         /* Read/Writable                                                */
 228         struct masterid jr_mid[4];      /* JRxLIODNR - JobR LIODN setup */
 229         u32 rsvd3[12];
 230         struct masterid rtic_mid[4];    /* RTICxLIODNR - RTIC LIODN setup */
 231         u32 rsvd4[7];
 232         u32 deco_rq;                    /* DECORR - DECO Request */
 233         struct partid deco_mid[5];      /* DECOxLIODNR - 1 per DECO */
 234         u32 rsvd5[22];
 235
 236         /* DECO Availability/Reset Section                      120-3ff */
 237         u32 deco_avail;         /* DAR - DECO availability */
 238         u32 deco_reset;         /* DRR - DECO reset */
 239         u32 rsvd6[182];
 240
 241         /* Key Encryption/Decryption Configuration              400-5ff */
 242         /* Read/Writable only while in Non-secure mode                  */
 243         u32 kek[KEK_KEY_SIZE];  /* JDKEKR - Key Encryption Key */
 244         u32 tkek[TKEK_KEY_SIZE];        /* TDKEKR - Trusted Desc KEK */
 245         u32 tdsk[TDSK_KEY_SIZE];        /* TDSKR - Trusted Desc Signing Key */
 246         u32 rsvd7[32];
 247         u64 sknonce;                    /* SKNR - Secure Key Nonce */
 248         u32 rsvd8[70];
 249
 250         /* RNG Test/Verification/Debug Access                   600-7ff */
 251         /* (Useful in Test/Debug modes only...)                         */
 252         struct rngtst rtst[2];
 253
 254         u32 rsvd9[448];
 255
 256         /* Performance Monitor                                  f00-fff */
 257         struct caam_perfmon perfmon;
 258 };
 259
 260 /*
 261  * Controller master config register defs
 262  */
 263 #define MCFGR_SWRESET           0x80000000 /* software reset */
 264 #define MCFGR_WDENABLE          0x40000000 /* DECO watchdog enable */
 265 #define MCFGR_WDFAIL            0x20000000 /* DECO watchdog force-fail */
 266 #define MCFGR_DMA_RESET         0x10000000
 267 #define MCFGR_LONG_PTR          0x00010000 /* Use >32-bit desc addressing */
 268
 269 /* AXI read cache control */
 270 #define MCFGR_ARCACHE_SHIFT     12
 271 #define MCFGR_ARCACHE_MASK      (0xf << MCFGR_ARCACHE_SHIFT)
 272
 273 /* AXI write cache control */
 274 #define MCFGR_AWCACHE_SHIFT     8
 275 #define MCFGR_AWCACHE_MASK      (0xf << MCFGR_AWCACHE_SHIFT)
 276
 277 /* AXI pipeline depth */
 278 #define MCFGR_AXIPIPE_SHIFT     4
 279 #define MCFGR_AXIPIPE_MASK      (0xf << MCFGR_AXIPIPE_SHIFT)
 280
 281 #define MCFGR_AXIPRI            0x00000008 /* Assert AXI priority sideband */
 282 #define MCFGR_BURST_64          0x00000001 /* Max burst size */
 283
 284 /*
 285  * caam_job_ring - direct job ring setup
 286  * 1-4 possible per instantiation, base + 1000/2000/3000/4000
 287  * Padded out to 0x1000
 288  */
 289 struct caam_job_ring {
 290         /* Input ring */
 291         u64 inpring_base;       /* IRBAx -  Input desc ring baseaddr */
 292         u32 rsvd1;
 293         u32 inpring_size;       /* IRSx - Input ring size */
 294         u32 rsvd2;
 295         u32 inpring_avail;      /* IRSAx - Input ring room remaining */
 296         u32 rsvd3;
 297         u32 inpring_jobadd;     /* IRJAx - Input ring jobs added */
 298
 299         /* Output Ring */
 300         u64 outring_base;       /* ORBAx - Output status ring base addr */
 301         u32 rsvd4;
 302         u32 outring_size;       /* ORSx - Output ring size */
 303         u32 rsvd5;
 304         u32 outring_rmvd;       /* ORJRx - Output ring jobs removed */
 305         u32 rsvd6;
 306         u32 outring_used;       /* ORSFx - Output ring slots full */
 307
 308         /* Status/Configuration */
 309         u32 rsvd7;
 310         u32 jroutstatus;        /* JRSTAx - JobR output status */
 311         u32 rsvd8;
 312         u32 jrintstatus;        /* JRINTx - JobR interrupt status */
 313         u32 rconfig_hi; /* JRxCFG - Ring configuration */
 314         u32 rconfig_lo;
 315
 316         /* Indices. CAAM maintains as "heads" of each queue */
 317         u32 rsvd9;
 318         u32 inp_rdidx;  /* IRRIx - Input ring read index */
 319         u32 rsvd10;
 320         u32 out_wtidx;  /* ORWIx - Output ring write index */
 321
 322         /* Command/control */
 323         u32 rsvd11;
 324         u32 jrcommand;  /* JRCRx - JobR command */
 325
 326         u32 rsvd12[932];
 327
 328         /* Performance Monitor                                  f00-fff */
 329         struct caam_perfmon perfmon;
 330 };
 331
 332 #define JR_RINGSIZE_MASK        0x03ff
 333 /*
 334  * jrstatus - Job Ring Output Status
 335  * All values in lo word
 336  * Also note, same values written out as status through QI
 337  * in the command/status field of a frame descriptor
 338  */
 339 #define JRSTA_SSRC_SHIFT            28
 340 #define JRSTA_SSRC_MASK             0xf0000000
 341
 342 #define JRSTA_SSRC_NONE             0x00000000
 343 #define JRSTA_SSRC_CCB_ERROR        0x20000000
 344 #define JRSTA_SSRC_JUMP_HALT_USER   0x30000000
 345 #define JRSTA_SSRC_DECO             0x40000000
 346 #define JRSTA_SSRC_JRERROR          0x60000000
 347 #define JRSTA_SSRC_JUMP_HALT_CC     0x70000000
 348
 349 #define JRSTA_DECOERR_JUMP          0x08000000
 350 #define JRSTA_DECOERR_INDEX_SHIFT   8
 351 #define JRSTA_DECOERR_INDEX_MASK    0xff00
 352 #define JRSTA_DECOERR_ERROR_MASK    0x00ff
 353
 354 #define JRSTA_DECOERR_NONE          0x00
 355 #define JRSTA_DECOERR_LINKLEN       0x01
 356 #define JRSTA_DECOERR_LINKPTR       0x02
 357 #define JRSTA_DECOERR_JRCTRL        0x03
 358 #define JRSTA_DECOERR_DESCCMD       0x04
 359 #define JRSTA_DECOERR_ORDER         0x05
 360 #define JRSTA_DECOERR_KEYCMD        0x06
 361 #define JRSTA_DECOERR_LOADCMD       0x07
 362 #define JRSTA_DECOERR_STORECMD      0x08
 363 #define JRSTA_DECOERR_OPCMD         0x09
 364 #define JRSTA_DECOERR_FIFOLDCMD     0x0a
 365 #define JRSTA_DECOERR_FIFOSTCMD     0x0b
 366 #define JRSTA_DECOERR_MOVECMD       0x0c
 367 #define JRSTA_DECOERR_JUMPCMD       0x0d
 368 #define JRSTA_DECOERR_MATHCMD       0x0e
 369 #define JRSTA_DECOERR_SHASHCMD      0x0f
 370 #define JRSTA_DECOERR_SEQCMD        0x10
 371 #define JRSTA_DECOERR_DECOINTERNAL  0x11
 372 #define JRSTA_DECOERR_SHDESCHDR     0x12
 373 #define JRSTA_DECOERR_HDRLEN        0x13
 374 #define JRSTA_DECOERR_BURSTER       0x14
 375 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
 376 #define JRSTA_DECOERR_DMA           0x16
 377 #define JRSTA_DECOERR_BURSTFIFO     0x17
 378 #define JRSTA_DECOERR_JRRESET       0x1a
 379 #define JRSTA_DECOERR_JOBFAIL       0x1b
 380 #define JRSTA_DECOERR_DNRERR        0x80
 381 #define JRSTA_DECOERR_UNDEFPCL      0x81
 382 #define JRSTA_DECOERR_PDBERR        0x82
 383 #define JRSTA_DECOERR_ANRPLY_LATE   0x83
 384 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
 385 #define JRSTA_DECOERR_SEQOVF        0x85
 386 #define JRSTA_DECOERR_INVSIGN       0x86
 387 #define JRSTA_DECOERR_DSASIGN       0x87
 388
 389 #define JRSTA_CCBERR_JUMP           0x08000000
 390 #define JRSTA_CCBERR_INDEX_MASK     0xff00
 391 #define JRSTA_CCBERR_INDEX_SHIFT    8
 392 #define JRSTA_CCBERR_CHAID_MASK     0x00f0
 393 #define JRSTA_CCBERR_CHAID_SHIFT    4
 394 #define JRSTA_CCBERR_ERRID_MASK     0x000f
 395
 396 #define JRSTA_CCBERR_CHAID_AES      (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
 397 #define JRSTA_CCBERR_CHAID_DES      (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
 398 #define JRSTA_CCBERR_CHAID_ARC4     (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
 399 #define JRSTA_CCBERR_CHAID_MD       (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
 400 #define JRSTA_CCBERR_CHAID_RNG      (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
 401 #define JRSTA_CCBERR_CHAID_SNOW     (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
 402 #define JRSTA_CCBERR_CHAID_KASUMI   (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
 403 #define JRSTA_CCBERR_CHAID_PK       (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
 404 #define JRSTA_CCBERR_CHAID_CRC      (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
 405
 406 #define JRSTA_CCBERR_ERRID_NONE     0x00
 407 #define JRSTA_CCBERR_ERRID_MODE     0x01
 408 #define JRSTA_CCBERR_ERRID_DATASIZ  0x02
 409 #define JRSTA_CCBERR_ERRID_KEYSIZ   0x03
 410 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
 411 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
 412 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
 413 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
 414 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
 415 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
 416 #define JRSTA_CCBERR_ERRID_ICVCHK   0x0a
 417 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
 418 #define JRSTA_CCBERR_ERRID_CCMAAD   0x0c
 419 #define JRSTA_CCBERR_ERRID_INVCHA   0x0f
 420
 421 #define JRINT_ERR_INDEX_MASK        0x3fff0000
 422 #define JRINT_ERR_INDEX_SHIFT       16
 423 #define JRINT_ERR_TYPE_MASK         0xf00
 424 #define JRINT_ERR_TYPE_SHIFT        8
 425 #define JRINT_ERR_HALT_MASK         0xc
 426 #define JRINT_ERR_HALT_SHIFT        2
 427 #define JRINT_ERR_HALT_INPROGRESS   0x4
 428 #define JRINT_ERR_HALT_COMPLETE     0x8
 429 #define JRINT_JR_ERROR              0x02
 430 #define JRINT_JR_INT                0x01
 431
 432 #define JRINT_ERR_TYPE_WRITE        1
 433 #define JRINT_ERR_TYPE_BAD_INPADDR  3
 434 #define JRINT_ERR_TYPE_BAD_OUTADDR  4
 435 #define JRINT_ERR_TYPE_INV_INPWRT   5
 436 #define JRINT_ERR_TYPE_INV_OUTWRT   6
 437 #define JRINT_ERR_TYPE_RESET        7
 438 #define JRINT_ERR_TYPE_REMOVE_OFL   8
 439 #define JRINT_ERR_TYPE_ADD_OFL      9
 440
 441 #define JRCFG_SOE               0x04
 442 #define JRCFG_ICEN              0x02
 443 #define JRCFG_IMSK              0x01
 444 #define JRCFG_ICDCT_SHIFT       8
 445 #define JRCFG_ICTT_SHIFT        16
 446
 447 #define JRCR_RESET                  0x01
 448
 449 /*
 450  * caam_assurance - Assurance Controller View
 451  * base + 0x6000 padded out to 0x1000
 452  */
 453
 454 struct rtic_element {
 455         u64 address;
 456         u32 rsvd;
 457         u32 length;
 458 };
 459
 460 struct rtic_block {
 461         struct rtic_element element[2];
 462 };
 463
 464 struct rtic_memhash {
 465         u32 memhash_be[32];
 466         u32 memhash_le[32];
 467 };
 468
 469 struct caam_assurance {
 470     /* Status/Command/Watchdog */
 471         u32 rsvd1;
 472         u32 status;             /* RSTA - Status */
 473         u32 rsvd2;
 474         u32 cmd;                /* RCMD - Command */
 475         u32 rsvd3;
 476         u32 ctrl;               /* RCTL - Control */
 477         u32 rsvd4;
 478         u32 throttle;   /* RTHR - Throttle */
 479         u32 rsvd5[2];
 480         u64 watchdog;   /* RWDOG - Watchdog Timer */
 481         u32 rsvd6;
 482         u32 rend;               /* REND - Endian corrections */
 483         u32 rsvd7[50];
 484
 485         /* Block access/configuration @ 100/110/120/130 */
 486         struct rtic_block memblk[4];    /* Memory Blocks A-D */
 487         u32 rsvd8[32];
 488
 489         /* Block hashes @ 200/300/400/500 */
 490         struct rtic_memhash hash[4];    /* Block hash values A-D */
 491         u32 rsvd_3[640];
 492 };
 493
 494 /*
 495  * caam_queue_if - QI configuration and control
 496  * starts base + 0x7000, padded out to 0x1000 long
 497  */
 498
 499 struct caam_queue_if {
 500         u32 qi_control_hi;      /* QICTL  - QI Control */
 501         u32 qi_control_lo;
 502         u32 rsvd1;
 503         u32 qi_status;  /* QISTA  - QI Status */
 504         u32 qi_deq_cfg_hi;      /* QIDQC  - QI Dequeue Configuration */
 505         u32 qi_deq_cfg_lo;
 506         u32 qi_enq_cfg_hi;      /* QISEQC - QI Enqueue Command     */
 507         u32 qi_enq_cfg_lo;
 508         u32 rsvd2[1016];
 509 };
 510
 511 /* QI control bits - low word */
 512 #define QICTL_DQEN      0x01              /* Enable frame pop          */
 513 #define QICTL_STOP      0x02              /* Stop dequeue/enqueue      */
 514 #define QICTL_SOE       0x04              /* Stop on error             */
 515
 516 /* QI control bits - high word */
 517 #define QICTL_MBSI      0x01
 518 #define QICTL_MHWSI     0x02
 519 #define QICTL_MWSI      0x04
 520 #define QICTL_MDWSI     0x08
 521 #define QICTL_CBSI      0x10            /* CtrlDataByteSwapInput     */
 522 #define QICTL_CHWSI     0x20            /* CtrlDataHalfSwapInput     */
 523 #define QICTL_CWSI      0x40            /* CtrlDataWordSwapInput     */
 524 #define QICTL_CDWSI     0x80            /* CtrlDataDWordSwapInput    */
 525 #define QICTL_MBSO      0x0100
 526 #define QICTL_MHWSO     0x0200
 527 #define QICTL_MWSO      0x0400
 528 #define QICTL_MDWSO     0x0800
 529 #define QICTL_CBSO      0x1000          /* CtrlDataByteSwapOutput    */
 530 #define QICTL_CHWSO     0x2000          /* CtrlDataHalfSwapOutput    */
 531 #define QICTL_CWSO      0x4000          /* CtrlDataWordSwapOutput    */
 532 #define QICTL_CDWSO     0x8000          /* CtrlDataDWordSwapOutput   */
 533 #define QICTL_DMBS      0x010000
 534 #define QICTL_EPO       0x020000
 535
 536 /* QI status bits */
 537 #define QISTA_PHRDERR   0x01              /* PreHeader Read Error      */
 538 #define QISTA_CFRDERR   0x02              /* Compound Frame Read Error */
 539 #define QISTA_OFWRERR   0x04              /* Output Frame Read Error   */
 540 #define QISTA_BPDERR    0x08              /* Buffer Pool Depleted      */
 541 #define QISTA_BTSERR    0x10              /* Buffer Undersize          */
 542 #define QISTA_CFWRERR   0x20              /* Compound Frame Write Err  */
 543 #define QISTA_STOPD     0x80000000        /* QI Stopped (see QICTL)    */
 544
 545 /* deco_sg_table - DECO view of scatter/gather table */
 546 struct deco_sg_table {
 547         u64 addr;               /* Segment Address */
 548         u32 elen;               /* E, F bits + 30-bit length */
 549         u32 bpid_offset;        /* Buffer Pool ID + 16-bit length */
 550 };
 551
 552 /*
 553  * caam_deco - descriptor controller - CHA cluster block
 554  *
 555  * Only accessible when direct DECO access is turned on
 556  * (done in DECORR, via MID programmed in DECOxMID
 557  *
 558  * 5 typical, base + 0x8000/9000/a000/b000
 559  * Padded out to 0x1000 long
 560  */
 561 struct caam_deco {
 562         u32 rsvd1;
 563         u32 cls1_mode;  /* CxC1MR -  Class 1 Mode */
 564         u32 rsvd2;
 565         u32 cls1_keysize;       /* CxC1KSR - Class 1 Key Size */
 566         u32 cls1_datasize_hi;   /* CxC1DSR - Class 1 Data Size */
 567         u32 cls1_datasize_lo;
 568         u32 rsvd3;
 569         u32 cls1_icvsize;       /* CxC1ICVSR - Class 1 ICV size */
 570         u32 rsvd4[5];
 571         u32 cha_ctrl;   /* CCTLR - CHA control */
 572         u32 rsvd5;
 573         u32 irq_crtl;   /* CxCIRQ - CCB interrupt done/error/clear */
 574         u32 rsvd6;
 575         u32 clr_written;        /* CxCWR - Clear-Written */
 576         u32 ccb_status_hi;      /* CxCSTA - CCB Status/Error */
 577         u32 ccb_status_lo;
 578         u32 rsvd7[3];
 579         u32 aad_size;   /* CxAADSZR - Current AAD Size */
 580         u32 rsvd8;
 581         u32 cls1_iv_size;       /* CxC1IVSZR - Current Class 1 IV Size */
 582         u32 rsvd9[7];
 583         u32 pkha_a_size;        /* PKASZRx - Size of PKHA A */
 584         u32 rsvd10;
 585         u32 pkha_b_size;        /* PKBSZRx - Size of PKHA B */
 586         u32 rsvd11;
 587         u32 pkha_n_size;        /* PKNSZRx - Size of PKHA N */
 588         u32 rsvd12;
 589         u32 pkha_e_size;        /* PKESZRx - Size of PKHA E */
 590         u32 rsvd13[24];
 591         u32 cls1_ctx[16];       /* CxC1CTXR - Class 1 Context @100 */
 592         u32 rsvd14[48];
 593         u32 cls1_key[8];        /* CxC1KEYR - Class 1 Key @200 */
 594         u32 rsvd15[121];
 595         u32 cls2_mode;  /* CxC2MR - Class 2 Mode */
 596         u32 rsvd16;
 597         u32 cls2_keysize;       /* CxX2KSR - Class 2 Key Size */
 598         u32 cls2_datasize_hi;   /* CxC2DSR - Class 2 Data Size */
 599         u32 cls2_datasize_lo;
 600         u32 rsvd17;
 601         u32 cls2_icvsize;       /* CxC2ICVSZR - Class 2 ICV Size */
 602         u32 rsvd18[56];
 603         u32 cls2_ctx[18];       /* CxC2CTXR - Class 2 Context @500 */
 604         u32 rsvd19[46];
 605         u32 cls2_key[32];       /* CxC2KEYR - Class2 Key @600 */
 606         u32 rsvd20[84];
 607         u32 inp_infofifo_hi;    /* CxIFIFO - Input Info FIFO @7d0 */
 608         u32 inp_infofifo_lo;
 609         u32 rsvd21[2];
 610         u64 inp_datafifo;       /* CxDFIFO - Input Data FIFO */
 611         u32 rsvd22[2];
 612         u64 out_datafifo;       /* CxOFIFO - Output Data FIFO */
 613         u32 rsvd23[2];
 614         u32 jr_ctl_hi;  /* CxJRR - JobR Control Register      @800 */
 615         u32 jr_ctl_lo;
 616         u64 jr_descaddr;        /* CxDADR - JobR Descriptor Address */
 617         u32 op_status_hi;       /* DxOPSTA - DECO Operation Status */
 618         u32 op_status_lo;
 619         u32 rsvd24[2];
 620         u32 liodn;              /* DxLSR - DECO LIODN Status - non-seq */
 621         u32 td_liodn;   /* DxLSR - DECO LIODN Status - trustdesc */
 622         u32 rsvd26[6];
 623         u64 math[4];            /* DxMTH - Math register */
 624         u32 rsvd27[8];
 625         struct deco_sg_table gthr_tbl[4];       /* DxGTR - Gather Tables */
 626         u32 rsvd28[16];
 627         struct deco_sg_table sctr_tbl[4];       /* DxSTR - Scatter Tables */
 628         u32 rsvd29[48];
 629         u32 descbuf[64];        /* DxDESB - Descriptor buffer */
 630         u32 rsvd30[320];
 631 };
 632
 633 /*
 634  * Current top-level view of memory map is:
 635  *
 636  * 0x0000 - 0x0fff - CAAM Top-Level Control
 637  * 0x1000 - 0x1fff - Job Ring 0
 638  * 0x2000 - 0x2fff - Job Ring 1
 639  * 0x3000 - 0x3fff - Job Ring 2
 640  * 0x4000 - 0x4fff - Job Ring 3
 641  * 0x5000 - 0x5fff - (unused)
 642  * 0x6000 - 0x6fff - Assurance Controller
 643  * 0x7000 - 0x7fff - Queue Interface
 644  * 0x8000 - 0x8fff - DECO-CCB 0
 645  * 0x9000 - 0x9fff - DECO-CCB 1
 646  * 0xa000 - 0xafff - DECO-CCB 2
 647  * 0xb000 - 0xbfff - DECO-CCB 3
 648  * 0xc000 - 0xcfff - DECO-CCB 4
 649  *
 650  * caam_full describes the full register view of CAAM if useful,
 651  * although many configurations may choose to implement parts of
 652  * the register map separately, in differing privilege regions
 653  */
 654 struct caam_full {
 655         struct caam_ctrl __iomem ctrl;
 656         struct caam_job_ring jr[4];
 657         u64 rsvd[512];
 658         struct caam_assurance assure;
 659         struct caam_queue_if qi;
 660 };
 661
 662 #endif /* REGS_H */