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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / gpu / drm / nouveau / nv20_graph.c
blob183e37512ef90c6f300e5b7176a716e8fb410f2a
1 #include "drmP.h"
2 #include "drm.h"
3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
5
6 /*
7 * NV20
8 * -----
9 * There are 3 families :
10 * NV20 is 0x10de:0x020*
11 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
12 * NV2A is 0x10de:0x02A0
13 *
14 * NV30
15 * -----
16 * There are 3 families :
17 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
18 * NV34 is 0x10de:0x032*
19 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
20 *
21 * Not seen in the wild, no dumps (probably NV35) :
22 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
23 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
24 *
25 */
26
27 struct nv20_graph_engine {
28 struct nouveau_exec_engine base;
29 struct nouveau_gpuobj *ctxtab;
30 void (*grctx_init)(struct nouveau_gpuobj *);
31 u32 grctx_size;
32 u32 grctx_user;
33 };
34
35 #define NV20_GRCTX_SIZE (3580*4)
36 #define NV25_GRCTX_SIZE (3529*4)
37 #define NV2A_GRCTX_SIZE (3500*4)
38
39 #define NV30_31_GRCTX_SIZE (24392)
40 #define NV34_GRCTX_SIZE (18140)
41 #define NV35_36_GRCTX_SIZE (22396)
42
43 int
44 nv20_graph_unload_context(struct drm_device *dev)
45 {
46 struct drm_nouveau_private *dev_priv = dev->dev_private;
47 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
48 struct nouveau_channel *chan;
49 struct nouveau_gpuobj *grctx;
50 u32 tmp;
51
52 chan = nv10_graph_channel(dev);
53 if (!chan)
54 return 0;
55 grctx = chan->engctx[NVOBJ_ENGINE_GR];
56
57 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, grctx->pinst >> 4);
58 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
59 NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
60
61 nouveau_wait_for_idle(dev);
62
63 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
64 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
65 tmp |= (pfifo->channels - 1) << 24;
66 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
67 return 0;
68 }
69
70 static void
71 nv20_graph_rdi(struct drm_device *dev)
72 {
73 struct drm_nouveau_private *dev_priv = dev->dev_private;
74 int i, writecount = 32;
75 uint32_t rdi_index = 0x2c80000;
76
77 if (dev_priv->chipset == 0x20) {
78 rdi_index = 0x3d0000;
79 writecount = 15;
80 }
81
82 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index);
83 for (i = 0; i < writecount; i++)
84 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0);
85
86 nouveau_wait_for_idle(dev);
87 }
88
89 static void
90 nv20_graph_context_init(struct nouveau_gpuobj *ctx)
91 {
92 int i;
93
94 nv_wo32(ctx, 0x033c, 0xffff0000);
95 nv_wo32(ctx, 0x03a0, 0x0fff0000);
96 nv_wo32(ctx, 0x03a4, 0x0fff0000);
97 nv_wo32(ctx, 0x047c, 0x00000101);
98 nv_wo32(ctx, 0x0490, 0x00000111);
99 nv_wo32(ctx, 0x04a8, 0x44400000);
100 for (i = 0x04d4; i <= 0x04e0; i += 4)
101 nv_wo32(ctx, i, 0x00030303);
102 for (i = 0x04f4; i <= 0x0500; i += 4)
103 nv_wo32(ctx, i, 0x00080000);
104 for (i = 0x050c; i <= 0x0518; i += 4)
105 nv_wo32(ctx, i, 0x01012000);
106 for (i = 0x051c; i <= 0x0528; i += 4)
107 nv_wo32(ctx, i, 0x000105b8);
108 for (i = 0x052c; i <= 0x0538; i += 4)
109 nv_wo32(ctx, i, 0x00080008);
110 for (i = 0x055c; i <= 0x0598; i += 4)
111 nv_wo32(ctx, i, 0x07ff0000);
112 nv_wo32(ctx, 0x05a4, 0x4b7fffff);
113 nv_wo32(ctx, 0x05fc, 0x00000001);
114 nv_wo32(ctx, 0x0604, 0x00004000);
115 nv_wo32(ctx, 0x0610, 0x00000001);
116 nv_wo32(ctx, 0x0618, 0x00040000);
117 nv_wo32(ctx, 0x061c, 0x00010000);
118 for (i = 0x1c1c; i <= 0x248c; i += 16) {
119 nv_wo32(ctx, (i + 0), 0x10700ff9);
120 nv_wo32(ctx, (i + 4), 0x0436086c);
121 nv_wo32(ctx, (i + 8), 0x000c001b);
122 }
123 nv_wo32(ctx, 0x281c, 0x3f800000);
124 nv_wo32(ctx, 0x2830, 0x3f800000);
125 nv_wo32(ctx, 0x285c, 0x40000000);
126 nv_wo32(ctx, 0x2860, 0x3f800000);
127 nv_wo32(ctx, 0x2864, 0x3f000000);
128 nv_wo32(ctx, 0x286c, 0x40000000);
129 nv_wo32(ctx, 0x2870, 0x3f800000);
130 nv_wo32(ctx, 0x2878, 0xbf800000);
131 nv_wo32(ctx, 0x2880, 0xbf800000);
132 nv_wo32(ctx, 0x34a4, 0x000fe000);
133 nv_wo32(ctx, 0x3530, 0x000003f8);
134 nv_wo32(ctx, 0x3540, 0x002fe000);
135 for (i = 0x355c; i <= 0x3578; i += 4)
136 nv_wo32(ctx, i, 0x001c527c);
137 }
138
139 static void
140 nv25_graph_context_init(struct nouveau_gpuobj *ctx)
141 {
142 int i;
143
144 nv_wo32(ctx, 0x035c, 0xffff0000);
145 nv_wo32(ctx, 0x03c0, 0x0fff0000);
146 nv_wo32(ctx, 0x03c4, 0x0fff0000);
147 nv_wo32(ctx, 0x049c, 0x00000101);
148 nv_wo32(ctx, 0x04b0, 0x00000111);
149 nv_wo32(ctx, 0x04c8, 0x00000080);
150 nv_wo32(ctx, 0x04cc, 0xffff0000);
151 nv_wo32(ctx, 0x04d0, 0x00000001);
152 nv_wo32(ctx, 0x04e4, 0x44400000);
153 nv_wo32(ctx, 0x04fc, 0x4b800000);
154 for (i = 0x0510; i <= 0x051c; i += 4)
155 nv_wo32(ctx, i, 0x00030303);
156 for (i = 0x0530; i <= 0x053c; i += 4)
157 nv_wo32(ctx, i, 0x00080000);
158 for (i = 0x0548; i <= 0x0554; i += 4)
159 nv_wo32(ctx, i, 0x01012000);
160 for (i = 0x0558; i <= 0x0564; i += 4)
161 nv_wo32(ctx, i, 0x000105b8);
162 for (i = 0x0568; i <= 0x0574; i += 4)
163 nv_wo32(ctx, i, 0x00080008);
164 for (i = 0x0598; i <= 0x05d4; i += 4)
165 nv_wo32(ctx, i, 0x07ff0000);
166 nv_wo32(ctx, 0x05e0, 0x4b7fffff);
167 nv_wo32(ctx, 0x0620, 0x00000080);
168 nv_wo32(ctx, 0x0624, 0x30201000);
169 nv_wo32(ctx, 0x0628, 0x70605040);
170 nv_wo32(ctx, 0x062c, 0xb0a09080);
171 nv_wo32(ctx, 0x0630, 0xf0e0d0c0);
172 nv_wo32(ctx, 0x0664, 0x00000001);
173 nv_wo32(ctx, 0x066c, 0x00004000);
174 nv_wo32(ctx, 0x0678, 0x00000001);
175 nv_wo32(ctx, 0x0680, 0x00040000);
176 nv_wo32(ctx, 0x0684, 0x00010000);
177 for (i = 0x1b04; i <= 0x2374; i += 16) {
178 nv_wo32(ctx, (i + 0), 0x10700ff9);
179 nv_wo32(ctx, (i + 4), 0x0436086c);
180 nv_wo32(ctx, (i + 8), 0x000c001b);
181 }
182 nv_wo32(ctx, 0x2704, 0x3f800000);
183 nv_wo32(ctx, 0x2718, 0x3f800000);
184 nv_wo32(ctx, 0x2744, 0x40000000);
185 nv_wo32(ctx, 0x2748, 0x3f800000);
186 nv_wo32(ctx, 0x274c, 0x3f000000);
187 nv_wo32(ctx, 0x2754, 0x40000000);
188 nv_wo32(ctx, 0x2758, 0x3f800000);
189 nv_wo32(ctx, 0x2760, 0xbf800000);
190 nv_wo32(ctx, 0x2768, 0xbf800000);
191 nv_wo32(ctx, 0x308c, 0x000fe000);
192 nv_wo32(ctx, 0x3108, 0x000003f8);
193 nv_wo32(ctx, 0x3468, 0x002fe000);
194 for (i = 0x3484; i <= 0x34a0; i += 4)
195 nv_wo32(ctx, i, 0x001c527c);
196 }
197
198 static void
199 nv2a_graph_context_init(struct nouveau_gpuobj *ctx)
200 {
201 int i;
202
203 nv_wo32(ctx, 0x033c, 0xffff0000);
204 nv_wo32(ctx, 0x03a0, 0x0fff0000);
205 nv_wo32(ctx, 0x03a4, 0x0fff0000);
206 nv_wo32(ctx, 0x047c, 0x00000101);
207 nv_wo32(ctx, 0x0490, 0x00000111);
208 nv_wo32(ctx, 0x04a8, 0x44400000);
209 for (i = 0x04d4; i <= 0x04e0; i += 4)
210 nv_wo32(ctx, i, 0x00030303);
211 for (i = 0x04f4; i <= 0x0500; i += 4)
212 nv_wo32(ctx, i, 0x00080000);
213 for (i = 0x050c; i <= 0x0518; i += 4)
214 nv_wo32(ctx, i, 0x01012000);
215 for (i = 0x051c; i <= 0x0528; i += 4)
216 nv_wo32(ctx, i, 0x000105b8);
217 for (i = 0x052c; i <= 0x0538; i += 4)
218 nv_wo32(ctx, i, 0x00080008);
219 for (i = 0x055c; i <= 0x0598; i += 4)
220 nv_wo32(ctx, i, 0x07ff0000);
221 nv_wo32(ctx, 0x05a4, 0x4b7fffff);
222 nv_wo32(ctx, 0x05fc, 0x00000001);
223 nv_wo32(ctx, 0x0604, 0x00004000);
224 nv_wo32(ctx, 0x0610, 0x00000001);
225 nv_wo32(ctx, 0x0618, 0x00040000);
226 nv_wo32(ctx, 0x061c, 0x00010000);
227 for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
228 nv_wo32(ctx, (i + 0), 0x10700ff9);
229 nv_wo32(ctx, (i + 4), 0x0436086c);
230 nv_wo32(ctx, (i + 8), 0x000c001b);
231 }
232 nv_wo32(ctx, 0x269c, 0x3f800000);
233 nv_wo32(ctx, 0x26b0, 0x3f800000);
234 nv_wo32(ctx, 0x26dc, 0x40000000);
235 nv_wo32(ctx, 0x26e0, 0x3f800000);
236 nv_wo32(ctx, 0x26e4, 0x3f000000);
237 nv_wo32(ctx, 0x26ec, 0x40000000);
238 nv_wo32(ctx, 0x26f0, 0x3f800000);
239 nv_wo32(ctx, 0x26f8, 0xbf800000);
240 nv_wo32(ctx, 0x2700, 0xbf800000);
241 nv_wo32(ctx, 0x3024, 0x000fe000);
242 nv_wo32(ctx, 0x30a0, 0x000003f8);
243 nv_wo32(ctx, 0x33fc, 0x002fe000);
244 for (i = 0x341c; i <= 0x3438; i += 4)
245 nv_wo32(ctx, i, 0x001c527c);
246 }
247
248 static void
249 nv30_31_graph_context_init(struct nouveau_gpuobj *ctx)
250 {
251 int i;
252
253 nv_wo32(ctx, 0x0410, 0x00000101);
254 nv_wo32(ctx, 0x0424, 0x00000111);
255 nv_wo32(ctx, 0x0428, 0x00000060);
256 nv_wo32(ctx, 0x0444, 0x00000080);
257 nv_wo32(ctx, 0x0448, 0xffff0000);
258 nv_wo32(ctx, 0x044c, 0x00000001);
259 nv_wo32(ctx, 0x0460, 0x44400000);
260 nv_wo32(ctx, 0x048c, 0xffff0000);
261 for (i = 0x04e0; i < 0x04e8; i += 4)
262 nv_wo32(ctx, i, 0x0fff0000);
263 nv_wo32(ctx, 0x04ec, 0x00011100);
264 for (i = 0x0508; i < 0x0548; i += 4)
265 nv_wo32(ctx, i, 0x07ff0000);
266 nv_wo32(ctx, 0x0550, 0x4b7fffff);
267 nv_wo32(ctx, 0x058c, 0x00000080);
268 nv_wo32(ctx, 0x0590, 0x30201000);
269 nv_wo32(ctx, 0x0594, 0x70605040);
270 nv_wo32(ctx, 0x0598, 0xb8a89888);
271 nv_wo32(ctx, 0x059c, 0xf8e8d8c8);
272 nv_wo32(ctx, 0x05b0, 0xb0000000);
273 for (i = 0x0600; i < 0x0640; i += 4)
274 nv_wo32(ctx, i, 0x00010588);
275 for (i = 0x0640; i < 0x0680; i += 4)
276 nv_wo32(ctx, i, 0x00030303);
277 for (i = 0x06c0; i < 0x0700; i += 4)
278 nv_wo32(ctx, i, 0x0008aae4);
279 for (i = 0x0700; i < 0x0740; i += 4)
280 nv_wo32(ctx, i, 0x01012000);
281 for (i = 0x0740; i < 0x0780; i += 4)
282 nv_wo32(ctx, i, 0x00080008);
283 nv_wo32(ctx, 0x085c, 0x00040000);
284 nv_wo32(ctx, 0x0860, 0x00010000);
285 for (i = 0x0864; i < 0x0874; i += 4)
286 nv_wo32(ctx, i, 0x00040004);
287 for (i = 0x1f18; i <= 0x3088 ; i += 16) {
288 nv_wo32(ctx, i + 0, 0x10700ff9);
289 nv_wo32(ctx, i + 1, 0x0436086c);
290 nv_wo32(ctx, i + 2, 0x000c001b);
291 }
292 for (i = 0x30b8; i < 0x30c8; i += 4)
293 nv_wo32(ctx, i, 0x0000ffff);
294 nv_wo32(ctx, 0x344c, 0x3f800000);
295 nv_wo32(ctx, 0x3808, 0x3f800000);
296 nv_wo32(ctx, 0x381c, 0x3f800000);
297 nv_wo32(ctx, 0x3848, 0x40000000);
298 nv_wo32(ctx, 0x384c, 0x3f800000);
299 nv_wo32(ctx, 0x3850, 0x3f000000);
300 nv_wo32(ctx, 0x3858, 0x40000000);
301 nv_wo32(ctx, 0x385c, 0x3f800000);
302 nv_wo32(ctx, 0x3864, 0xbf800000);
303 nv_wo32(ctx, 0x386c, 0xbf800000);
304 }
305
306 static void
307 nv34_graph_context_init(struct nouveau_gpuobj *ctx)
308 {
309 int i;
310
311 nv_wo32(ctx, 0x040c, 0x01000101);
312 nv_wo32(ctx, 0x0420, 0x00000111);
313 nv_wo32(ctx, 0x0424, 0x00000060);
314 nv_wo32(ctx, 0x0440, 0x00000080);
315 nv_wo32(ctx, 0x0444, 0xffff0000);
316 nv_wo32(ctx, 0x0448, 0x00000001);
317 nv_wo32(ctx, 0x045c, 0x44400000);
318 nv_wo32(ctx, 0x0480, 0xffff0000);
319 for (i = 0x04d4; i < 0x04dc; i += 4)
320 nv_wo32(ctx, i, 0x0fff0000);
321 nv_wo32(ctx, 0x04e0, 0x00011100);
322 for (i = 0x04fc; i < 0x053c; i += 4)
323 nv_wo32(ctx, i, 0x07ff0000);
324 nv_wo32(ctx, 0x0544, 0x4b7fffff);
325 nv_wo32(ctx, 0x057c, 0x00000080);
326 nv_wo32(ctx, 0x0580, 0x30201000);
327 nv_wo32(ctx, 0x0584, 0x70605040);
328 nv_wo32(ctx, 0x0588, 0xb8a89888);
329 nv_wo32(ctx, 0x058c, 0xf8e8d8c8);
330 nv_wo32(ctx, 0x05a0, 0xb0000000);
331 for (i = 0x05f0; i < 0x0630; i += 4)
332 nv_wo32(ctx, i, 0x00010588);
333 for (i = 0x0630; i < 0x0670; i += 4)
334 nv_wo32(ctx, i, 0x00030303);
335 for (i = 0x06b0; i < 0x06f0; i += 4)
336 nv_wo32(ctx, i, 0x0008aae4);
337 for (i = 0x06f0; i < 0x0730; i += 4)
338 nv_wo32(ctx, i, 0x01012000);
339 for (i = 0x0730; i < 0x0770; i += 4)
340 nv_wo32(ctx, i, 0x00080008);
341 nv_wo32(ctx, 0x0850, 0x00040000);
342 nv_wo32(ctx, 0x0854, 0x00010000);
343 for (i = 0x0858; i < 0x0868; i += 4)
344 nv_wo32(ctx, i, 0x00040004);
345 for (i = 0x15ac; i <= 0x271c ; i += 16) {
346 nv_wo32(ctx, i + 0, 0x10700ff9);
347 nv_wo32(ctx, i + 1, 0x0436086c);
348 nv_wo32(ctx, i + 2, 0x000c001b);
349 }
350 for (i = 0x274c; i < 0x275c; i += 4)
351 nv_wo32(ctx, i, 0x0000ffff);
352 nv_wo32(ctx, 0x2ae0, 0x3f800000);
353 nv_wo32(ctx, 0x2e9c, 0x3f800000);
354 nv_wo32(ctx, 0x2eb0, 0x3f800000);
355 nv_wo32(ctx, 0x2edc, 0x40000000);
356 nv_wo32(ctx, 0x2ee0, 0x3f800000);
357 nv_wo32(ctx, 0x2ee4, 0x3f000000);
358 nv_wo32(ctx, 0x2eec, 0x40000000);
359 nv_wo32(ctx, 0x2ef0, 0x3f800000);
360 nv_wo32(ctx, 0x2ef8, 0xbf800000);
361 nv_wo32(ctx, 0x2f00, 0xbf800000);
362 }
363
364 static void
365 nv35_36_graph_context_init(struct nouveau_gpuobj *ctx)
366 {
367 int i;
368
369 nv_wo32(ctx, 0x040c, 0x00000101);
370 nv_wo32(ctx, 0x0420, 0x00000111);
371 nv_wo32(ctx, 0x0424, 0x00000060);
372 nv_wo32(ctx, 0x0440, 0x00000080);
373 nv_wo32(ctx, 0x0444, 0xffff0000);
374 nv_wo32(ctx, 0x0448, 0x00000001);
375 nv_wo32(ctx, 0x045c, 0x44400000);
376 nv_wo32(ctx, 0x0488, 0xffff0000);
377 for (i = 0x04dc; i < 0x04e4; i += 4)
378 nv_wo32(ctx, i, 0x0fff0000);
379 nv_wo32(ctx, 0x04e8, 0x00011100);
380 for (i = 0x0504; i < 0x0544; i += 4)
381 nv_wo32(ctx, i, 0x07ff0000);
382 nv_wo32(ctx, 0x054c, 0x4b7fffff);
383 nv_wo32(ctx, 0x0588, 0x00000080);
384 nv_wo32(ctx, 0x058c, 0x30201000);
385 nv_wo32(ctx, 0x0590, 0x70605040);
386 nv_wo32(ctx, 0x0594, 0xb8a89888);
387 nv_wo32(ctx, 0x0598, 0xf8e8d8c8);
388 nv_wo32(ctx, 0x05ac, 0xb0000000);
389 for (i = 0x0604; i < 0x0644; i += 4)
390 nv_wo32(ctx, i, 0x00010588);
391 for (i = 0x0644; i < 0x0684; i += 4)
392 nv_wo32(ctx, i, 0x00030303);
393 for (i = 0x06c4; i < 0x0704; i += 4)
394 nv_wo32(ctx, i, 0x0008aae4);
395 for (i = 0x0704; i < 0x0744; i += 4)
396 nv_wo32(ctx, i, 0x01012000);
397 for (i = 0x0744; i < 0x0784; i += 4)
398 nv_wo32(ctx, i, 0x00080008);
399 nv_wo32(ctx, 0x0860, 0x00040000);
400 nv_wo32(ctx, 0x0864, 0x00010000);
401 for (i = 0x0868; i < 0x0878; i += 4)
402 nv_wo32(ctx, i, 0x00040004);
403 for (i = 0x1f1c; i <= 0x308c ; i += 16) {
404 nv_wo32(ctx, i + 0, 0x10700ff9);
405 nv_wo32(ctx, i + 4, 0x0436086c);
406 nv_wo32(ctx, i + 8, 0x000c001b);
407 }
408 for (i = 0x30bc; i < 0x30cc; i += 4)
409 nv_wo32(ctx, i, 0x0000ffff);
410 nv_wo32(ctx, 0x3450, 0x3f800000);
411 nv_wo32(ctx, 0x380c, 0x3f800000);
412 nv_wo32(ctx, 0x3820, 0x3f800000);
413 nv_wo32(ctx, 0x384c, 0x40000000);
414 nv_wo32(ctx, 0x3850, 0x3f800000);
415 nv_wo32(ctx, 0x3854, 0x3f000000);
416 nv_wo32(ctx, 0x385c, 0x40000000);
417 nv_wo32(ctx, 0x3860, 0x3f800000);
418 nv_wo32(ctx, 0x3868, 0xbf800000);
419 nv_wo32(ctx, 0x3870, 0xbf800000);
420 }
421
422 int
423 nv20_graph_context_new(struct nouveau_channel *chan, int engine)
424 {
425 struct nv20_graph_engine *pgraph = nv_engine(chan->dev, engine);
426 struct nouveau_gpuobj *grctx = NULL;
427 struct drm_device *dev = chan->dev;
428 int ret;
429
430 ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
431 NVOBJ_FLAG_ZERO_ALLOC, &grctx);
432 if (ret)
433 return ret;
434
435 /* Initialise default context values */
436 pgraph->grctx_init(grctx);
437
438 /* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
439 /* CTX_USER */
440 nv_wo32(grctx, pgraph->grctx_user, (chan->id << 24) | 0x1);
441
442 nv_wo32(pgraph->ctxtab, chan->id * 4, grctx->pinst >> 4);
443 chan->engctx[engine] = grctx;
444 return 0;
445 }
446
447 void
448 nv20_graph_context_del(struct nouveau_channel *chan, int engine)
449 {
450 struct nv20_graph_engine *pgraph = nv_engine(chan->dev, engine);
451 struct nouveau_gpuobj *grctx = chan->engctx[engine];
452 struct drm_device *dev = chan->dev;
453 struct drm_nouveau_private *dev_priv = dev->dev_private;
454 unsigned long flags;
455
456 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
457 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
458
459 /* Unload the context if it's the currently active one */
460 if (nv10_graph_channel(dev) == chan)
461 nv20_graph_unload_context(dev);
462
463 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
464 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
465
466 /* Free the context resources */
467 nv_wo32(pgraph->ctxtab, chan->id * 4, 0);
468
469 nouveau_gpuobj_ref(NULL, &grctx);
470 chan->engctx[engine] = NULL;
471 }
472
473 static void
474 nv20_graph_set_tile_region(struct drm_device *dev, int i)
475 {
476 struct drm_nouveau_private *dev_priv = dev->dev_private;
477 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
478
479 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
480 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
481 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
482
483 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
484 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->limit);
485 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
486 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->pitch);
487 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
488 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->addr);
489
490 if (dev_priv->card_type == NV_20) {
491 nv_wr32(dev, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
492 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
493 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->zcomp);
494 }
495 }
496
497 int
498 nv20_graph_init(struct drm_device *dev, int engine)
499 {
500 struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
501 struct drm_nouveau_private *dev_priv = dev->dev_private;
502 uint32_t tmp, vramsz;
503 int i;
504
505 nv_wr32(dev, NV03_PMC_ENABLE,
506 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
507 nv_wr32(dev, NV03_PMC_ENABLE,
508 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH);
509
510 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
511
512 nv20_graph_rdi(dev);
513
514 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
515 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
516
517 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
518 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
519 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x00118700);
520 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
521 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
522 nv_wr32(dev, 0x40009C , 0x00000040);
523
524 if (dev_priv->chipset >= 0x25) {
525 nv_wr32(dev, 0x400890, 0x00a8cfff);
526 nv_wr32(dev, 0x400610, 0x304B1FB6);
527 nv_wr32(dev, 0x400B80, 0x1cbd3883);
528 nv_wr32(dev, 0x400B84, 0x44000000);
529 nv_wr32(dev, 0x400098, 0x40000080);
530 nv_wr32(dev, 0x400B88, 0x000000ff);
531
532 } else {
533 nv_wr32(dev, 0x400880, 0x0008c7df);
534 nv_wr32(dev, 0x400094, 0x00000005);
535 nv_wr32(dev, 0x400B80, 0x45eae20e);
536 nv_wr32(dev, 0x400B84, 0x24000000);
537 nv_wr32(dev, 0x400098, 0x00000040);
538 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
539 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
540 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
541 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
542 }
543
544 /* Turn all the tiling regions off. */
545 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
546 nv20_graph_set_tile_region(dev, i);
547
548 nv_wr32(dev, 0x4009a0, nv_rd32(dev, 0x100324));
549 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
550 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, nv_rd32(dev, 0x100324));
551
552 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
553 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
554
555 tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) & 0x0007ff00;
556 nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp);
557 tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) | 0x00020100;
558 nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp);
559
560 /* begin RAM config */
561 vramsz = pci_resource_len(dev->pdev, 0) - 1;
562 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
563 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
564 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
565 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG0));
566 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
567 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG1));
568 nv_wr32(dev, 0x400820, 0);
569 nv_wr32(dev, 0x400824, 0);
570 nv_wr32(dev, 0x400864, vramsz - 1);
571 nv_wr32(dev, 0x400868, vramsz - 1);
572
573 /* interesting.. the below overwrites some of the tile setup above.. */
574 nv_wr32(dev, 0x400B20, 0x00000000);
575 nv_wr32(dev, 0x400B04, 0xFFFFFFFF);
576
577 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
578 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
579 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
580 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
581
582 return 0;
583 }
584
585 int
586 nv30_graph_init(struct drm_device *dev, int engine)
587 {
588 struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
589 struct drm_nouveau_private *dev_priv = dev->dev_private;
590 int i;
591
592 nv_wr32(dev, NV03_PMC_ENABLE,
593 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
594 nv_wr32(dev, NV03_PMC_ENABLE,
595 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH);
596
597 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
598
599 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
600 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
601
602 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
603 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
604 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
605 nv_wr32(dev, 0x400890, 0x01b463ff);
606 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
607 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
608 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
609 nv_wr32(dev, 0x400B80, 0x1003d888);
610 nv_wr32(dev, 0x400B84, 0x0c000000);
611 nv_wr32(dev, 0x400098, 0x00000000);
612 nv_wr32(dev, 0x40009C, 0x0005ad00);
613 nv_wr32(dev, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
614 nv_wr32(dev, 0x4000a0, 0x00000000);
615 nv_wr32(dev, 0x4000a4, 0x00000008);
616 nv_wr32(dev, 0x4008a8, 0xb784a400);
617 nv_wr32(dev, 0x400ba0, 0x002f8685);
618 nv_wr32(dev, 0x400ba4, 0x00231f3f);
619 nv_wr32(dev, 0x4008a4, 0x40000020);
620
621 if (dev_priv->chipset == 0x34) {
622 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
623 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00200201);
624 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
625 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000008);
626 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
627 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000032);
628 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
629 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000002);
630 }
631
632 nv_wr32(dev, 0x4000c0, 0x00000016);
633
634 /* Turn all the tiling regions off. */
635 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
636 nv20_graph_set_tile_region(dev, i);
637
638 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
639 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
640 nv_wr32(dev, 0x0040075c , 0x00000001);
641
642 /* begin RAM config */
643 /* vramsz = pci_resource_len(dev->pdev, 0) - 1; */
644 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
645 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
646 if (dev_priv->chipset != 0x34) {
647 nv_wr32(dev, 0x400750, 0x00EA0000);
648 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG0));
649 nv_wr32(dev, 0x400750, 0x00EA0004);
650 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG1));
651 }
652
653 return 0;
654 }
655
656 int
657 nv20_graph_fini(struct drm_device *dev, int engine, bool suspend)
658 {
659 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
660 if (!nv_wait(dev, NV04_PGRAPH_STATUS, ~0, 0) && suspend) {
661 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
662 return -EBUSY;
663 }
664 nv20_graph_unload_context(dev);
665 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
666 return 0;
667 }
668
669 static void
670 nv20_graph_isr(struct drm_device *dev)
671 {
672 u32 stat;
673
674 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
675 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
676 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
677 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
678 u32 chid = (addr & 0x01f00000) >> 20;
679 u32 subc = (addr & 0x00070000) >> 16;
680 u32 mthd = (addr & 0x00001ffc);
681 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
682 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xfff;
683 u32 show = stat;
684
685 if (stat & NV_PGRAPH_INTR_ERROR) {
686 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
687 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
688 show &= ~NV_PGRAPH_INTR_ERROR;
689 }
690 }
691
692 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
693 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
694
695 if (show && nouveau_ratelimit()) {
696 NV_INFO(dev, "PGRAPH -");
697 nouveau_bitfield_print(nv10_graph_intr, show);
698 printk(" nsource:");
699 nouveau_bitfield_print(nv04_graph_nsource, nsource);
700 printk(" nstatus:");
701 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
702 printk("\n");
703 NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
704 "mthd 0x%04x data 0x%08x\n",
705 chid, subc, class, mthd, data);
706 }
707 }
708 }
709
710 static void
711 nv20_graph_destroy(struct drm_device *dev, int engine)
712 {
713 struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
714
715 nouveau_irq_unregister(dev, 12);
716 nouveau_gpuobj_ref(NULL, &pgraph->ctxtab);
717
718 NVOBJ_ENGINE_DEL(dev, GR);
719 kfree(pgraph);
720 }
721
722 int
723 nv20_graph_create(struct drm_device *dev)
724 {
725 struct drm_nouveau_private *dev_priv = dev->dev_private;
726 struct nv20_graph_engine *pgraph;
727 int ret;
728
729 pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
730 if (!pgraph)
731 return -ENOMEM;
732
733 pgraph->base.destroy = nv20_graph_destroy;
734 pgraph->base.fini = nv20_graph_fini;
735 pgraph->base.context_new = nv20_graph_context_new;
736 pgraph->base.context_del = nv20_graph_context_del;
737 pgraph->base.object_new = nv04_graph_object_new;
738 pgraph->base.set_tile_region = nv20_graph_set_tile_region;
739
740 pgraph->grctx_user = 0x0028;
741 if (dev_priv->card_type == NV_20) {
742 pgraph->base.init = nv20_graph_init;
743 switch (dev_priv->chipset) {
744 case 0x20:
745 pgraph->grctx_init = nv20_graph_context_init;
746 pgraph->grctx_size = NV20_GRCTX_SIZE;
747 pgraph->grctx_user = 0x0000;
748 break;
749 case 0x25:
750 case 0x28:
751 pgraph->grctx_init = nv25_graph_context_init;
752 pgraph->grctx_size = NV25_GRCTX_SIZE;
753 break;
754 case 0x2a:
755 pgraph->grctx_init = nv2a_graph_context_init;
756 pgraph->grctx_size = NV2A_GRCTX_SIZE;
757 pgraph->grctx_user = 0x0000;
758 break;
759 default:
760 NV_ERROR(dev, "PGRAPH: unknown chipset\n");
761 kfree(pgraph);
762 return 0;
763 }
764 } else {
765 pgraph->base.init = nv30_graph_init;
766 switch (dev_priv->chipset) {
767 case 0x30:
768 case 0x31:
769 pgraph->grctx_init = nv30_31_graph_context_init;
770 pgraph->grctx_size = NV30_31_GRCTX_SIZE;
771 break;
772 case 0x34:
773 pgraph->grctx_init = nv34_graph_context_init;
774 pgraph->grctx_size = NV34_GRCTX_SIZE;
775 break;
776 case 0x35:
777 case 0x36:
778 pgraph->grctx_init = nv35_36_graph_context_init;
779 pgraph->grctx_size = NV35_36_GRCTX_SIZE;
780 break;
781 default:
782 NV_ERROR(dev, "PGRAPH: unknown chipset\n");
783 kfree(pgraph);
784 return 0;
785 }
786 }
787
788 /* Create Context Pointer Table */
789 ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC,
790 &pgraph->ctxtab);
791 if (ret) {
792 kfree(pgraph);
793 return ret;
794 }
795
796 NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
797 nouveau_irq_register(dev, 12, nv20_graph_isr);
798
799 /* nvsw */
800 NVOBJ_CLASS(dev, 0x506e, SW);
801 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
802
803 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
804 NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
805 NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
806 NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
807 NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
808 NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
809 NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
810 NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
811 NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
812 NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
813 NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
814 NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
815 if (dev_priv->card_type == NV_20) {
816 NVOBJ_CLASS(dev, 0x009e, GR); /* swzsurf */
817 NVOBJ_CLASS(dev, 0x0096, GR); /* celcius */
818
819 /* kelvin */
820 if (dev_priv->chipset < 0x25)
821 NVOBJ_CLASS(dev, 0x0097, GR);
822 else
823 NVOBJ_CLASS(dev, 0x0597, GR);
824 } else {
825 NVOBJ_CLASS(dev, 0x038a, GR); /* ifc (nv30) */
826 NVOBJ_CLASS(dev, 0x0389, GR); /* sifm (nv30) */
827 NVOBJ_CLASS(dev, 0x0362, GR); /* surf2d (nv30) */
828 NVOBJ_CLASS(dev, 0x039e, GR); /* swzsurf */
829
830 /* rankine */
831 if (0x00000003 & (1 << (dev_priv->chipset & 0x0f)))
832 NVOBJ_CLASS(dev, 0x0397, GR);
833 else
834 if (0x00000010 & (1 << (dev_priv->chipset & 0x0f)))
835 NVOBJ_CLASS(dev, 0x0697, GR);
836 else
837 if (0x000001e0 & (1 << (dev_priv->chipset & 0x0f)))
838 NVOBJ_CLASS(dev, 0x0497, GR);
839 }
840
841 return 0;
842 }