drivers/gpu/drm/nouveau/nvc0_graph.h

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #ifndef __NVC0_GRAPH_H__
  26 #define __NVC0_GRAPH_H__
  27
  28 #define GPC_MAX 4
  29 #define TP_MAX 32
  30
  31 #define ROP_BCAST(r)     (0x408800 + (r))
  32 #define ROP_UNIT(u, r)   (0x410000 + (u) * 0x400 + (r))
  33 #define GPC_BCAST(r)     (0x418000 + (r))
  34 #define GPC_UNIT(t, r)   (0x500000 + (t) * 0x8000 + (r))
  35 #define TP_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
  36
  37 struct nvc0_graph_fuc {
  38         u32 *data;
  39         u32  size;
  40 };
  41
  42 struct nvc0_graph_priv {
  43         struct nouveau_exec_engine base;
  44
  45         struct nvc0_graph_fuc fuc409c;
  46         struct nvc0_graph_fuc fuc409d;
  47         struct nvc0_graph_fuc fuc41ac;
  48         struct nvc0_graph_fuc fuc41ad;
  49
  50         u8 gpc_nr;
  51         u8 rop_nr;
  52         u8 tp_nr[GPC_MAX];
  53         u8 tp_total;
  54
  55         u32  grctx_size;
  56         u32 *grctx_vals;
  57         struct nouveau_gpuobj *unk4188b4;
  58         struct nouveau_gpuobj *unk4188b8;
  59
  60         u8 magic_not_rop_nr;
  61 };
  62
  63 struct nvc0_graph_chan {
  64         struct nouveau_gpuobj *grctx;
  65         struct nouveau_gpuobj *unk408004; /* 0x418810 too */
  66         struct nouveau_gpuobj *unk40800c; /* 0x419004 too */
  67         struct nouveau_gpuobj *unk418810; /* 0x419848 too */
  68         struct nouveau_gpuobj *mmio;
  69         int mmio_nr;
  70 };
  71
  72 int nvc0_grctx_generate(struct nouveau_channel *);
  73
  74 /* nvc0_graph.c uses this also to determine supported chipsets */
  75 static inline u32
  76 nvc0_graph_class(struct drm_device *dev)
  77 {
  78         struct drm_nouveau_private *dev_priv = dev->dev_private;
  79
  80         switch (dev_priv->chipset) {
  81         case 0xc0:
  82         case 0xc3:
  83         case 0xc4:
  84         case 0xce: /* guess, mmio trace shows only 0x9097 state */
  85         case 0xcf: /* guess, mmio trace shows only 0x9097 state */
  86                 return 0x9097;
  87         case 0xc1:
  88                 return 0x9197;
  89         case 0xc8:
  90         case 0xd9:
  91                 return 0x9297;
  92         default:
  93                 return 0;
  94         }
  95 }
  96
  97 #endif