drivers/gpu/drm/radeon/r600_blit_shaders.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29
  30 /*
  31  * R6xx+ cards need to use the 3D engine to blit data which requires
  32  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
  33  * (which normally generates the 3D state) into the DRM, we opt to use
  34  * statically generated state tables.  The regsiter state and shaders
  35  * were hand generated to support blitting functionality.  See the 3D
  36  * driver or documentation for descriptions of the registers and
  37  * shader instructions.
  38  */
  39
  40 const u32 r6xx_default_state[] =
  41 {
  42         0xc0002400, /* START_3D_CMDBUF */
  43         0x00000000,
  44
  45         0xc0012800, /* CONTEXT_CONTROL */
  46         0x80000000,
  47         0x80000000,
  48
  49         0xc0016800,
  50         0x00000010,
  51         0x00008000, /* WAIT_UNTIL */
  52
  53         0xc0016800,
  54         0x00000542,
  55         0x07000003, /* TA_CNTL_AUX */
  56
  57         0xc0016800,
  58         0x000005c5,
  59         0x00000000, /* VC_ENHANCE */
  60
  61         0xc0016800,
  62         0x00000363,
  63         0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
  64
  65         0xc0016800,
  66         0x0000060c,
  67         0x82000000, /* DB_DEBUG */
  68
  69         0xc0016800,
  70         0x0000060e,
  71         0x01020204, /* DB_WATERMARKS */
  72
  73         0xc0026f00,
  74         0x00000000,
  75         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
  76         0x00000000, /* SQ_VTX_START_INST_LOC */
  77
  78         0xc0096900,
  79         0x0000022a,
  80         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
  81         0x00000000,
  82         0x00000000,
  83         0x00000000,
  84         0x00000000,
  85         0x00000000,
  86         0x00000000,
  87         0x00000000,
  88         0x00000000,
  89
  90         0xc0016900,
  91         0x00000004,
  92         0x00000000, /* DB_DEPTH_INFO */
  93
  94         0xc0026900,
  95         0x0000000a,
  96         0x00000000, /* DB_STENCIL_CLEAR */
  97         0x00000000, /* DB_DEPTH_CLEAR */
  98
  99         0xc0016900,
 100         0x00000200,
 101         0x00000000, /* DB_DEPTH_CONTROL */
 102
 103         0xc0026900,
 104         0x00000343,
 105         0x00000060, /* DB_RENDER_CONTROL */
 106         0x00000040, /* DB_RENDER_OVERRIDE */
 107
 108         0xc0016900,
 109         0x00000351,
 110         0x0000aa00, /* DB_ALPHA_TO_MASK */
 111
 112         0xc00f6900,
 113         0x00000100,
 114         0x00000800, /* VGT_MAX_VTX_INDX */
 115         0x00000000, /* VGT_MIN_VTX_INDX */
 116         0x00000000, /* VGT_INDX_OFFSET */
 117         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 118         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 119         0x00000000, /* CB_BLEND_RED */
 120         0x00000000,
 121         0x00000000,
 122         0x00000000,
 123         0x00000000, /* CB_FOG_RED */
 124         0x00000000,
 125         0x00000000,
 126         0x00000000, /* DB_STENCILREFMASK */
 127         0x00000000, /* DB_STENCILREFMASK_BF */
 128         0x00000000, /* SX_ALPHA_REF */
 129
 130         0xc0046900,
 131         0x0000030c,
 132         0x01000000, /* CB_CLRCMP_CNTL */
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136
 137         0xc0046900,
 138         0x00000048,
 139         0x3f800000, /* CB_CLEAR_RED */
 140         0x00000000,
 141         0x3f800000,
 142         0x3f800000,
 143
 144         0xc0016900,
 145         0x00000080,
 146         0x00000000, /* PA_SC_WINDOW_OFFSET */
 147
 148         0xc00a6900,
 149         0x00000083,
 150         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 151         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 152         0x20002000,
 153         0x00000000,
 154         0x20002000,
 155         0x00000000,
 156         0x20002000,
 157         0x00000000,
 158         0x20002000,
 159         0x00000000, /* PA_SC_EDGERULE */
 160
 161         0xc0406900,
 162         0x00000094,
 163         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 164         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 165         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 166         0x20002000,
 167         0x80000000,
 168         0x20002000,
 169         0x80000000,
 170         0x20002000,
 171         0x80000000,
 172         0x20002000,
 173         0x80000000,
 174         0x20002000,
 175         0x80000000,
 176         0x20002000,
 177         0x80000000,
 178         0x20002000,
 179         0x80000000,
 180         0x20002000,
 181         0x80000000,
 182         0x20002000,
 183         0x80000000,
 184         0x20002000,
 185         0x80000000,
 186         0x20002000,
 187         0x80000000,
 188         0x20002000,
 189         0x80000000,
 190         0x20002000,
 191         0x80000000,
 192         0x20002000,
 193         0x80000000,
 194         0x20002000,
 195         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 196         0x3f800000,
 197         0x00000000,
 198         0x3f800000,
 199         0x00000000,
 200         0x3f800000,
 201         0x00000000,
 202         0x3f800000,
 203         0x00000000,
 204         0x3f800000,
 205         0x00000000,
 206         0x3f800000,
 207         0x00000000,
 208         0x3f800000,
 209         0x00000000,
 210         0x3f800000,
 211         0x00000000,
 212         0x3f800000,
 213         0x00000000,
 214         0x3f800000,
 215         0x00000000,
 216         0x3f800000,
 217         0x00000000,
 218         0x3f800000,
 219         0x00000000,
 220         0x3f800000,
 221         0x00000000,
 222         0x3f800000,
 223         0x00000000,
 224         0x3f800000,
 225         0x00000000,
 226         0x3f800000,
 227
 228         0xc0026900,
 229         0x00000292,
 230         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 231         0x00004010, /* PA_SC_MODE_CNTL */
 232
 233         0xc0096900,
 234         0x00000300,
 235         0x00000000, /* PA_SC_LINE_CNTL */
 236         0x00000000, /* PA_SC_AA_CONFIG */
 237         0x0000002d, /* PA_SU_VTX_CNTL */
 238         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 239         0x3f800000,
 240         0x3f800000,
 241         0x3f800000,
 242         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 243         0x00000000,
 244
 245         0xc0016900,
 246         0x00000312,
 247         0xffffffff, /* PA_SC_AA_MASK */
 248
 249         0xc0066900,
 250         0x0000037e,
 251         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 252         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 253         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 254         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 255         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 256         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 257
 258         0xc0046900,
 259         0x000001b6,
 260         0x00000000, /* SPI_INPUT_Z */
 261         0x00000000, /* SPI_FOG_CNTL */
 262         0x00000000, /* SPI_FOG_FUNC_SCALE */
 263         0x00000000, /* SPI_FOG_FUNC_BIAS */
 264
 265         0xc0016900,
 266         0x00000225,
 267         0x00000000, /* SQ_PGM_START_FS */
 268
 269         0xc0016900,
 270         0x00000229,
 271         0x00000000, /* SQ_PGM_RESOURCES_FS */
 272
 273         0xc0016900,
 274         0x00000237,
 275         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 276
 277         0xc0026900,
 278         0x000002a8,
 279         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 280         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 281
 282         0xc0116900,
 283         0x00000280,
 284         0x00000000, /* PA_SU_POINT_SIZE */
 285         0x00000000, /* PA_SU_POINT_MINMAX */
 286         0x00000008, /* PA_SU_LINE_CNTL */
 287         0x00000000, /* PA_SC_LINE_STIPPLE */
 288         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 289         0x00000000, /* VGT_HOS_CNTL */
 290         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 291         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 292         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 293         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 294         0x00000000, /* VGT_GROUP_FIRST_DECR */
 295         0x00000000, /* VGT_GROUP_DECR */
 296         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 297         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 298         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 299         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 300         0x00000000, /* VGT_GS_MODE */
 301
 302         0xc0016900,
 303         0x000002a1,
 304         0x00000000, /* VGT_PRIMITIVEID_EN */
 305
 306         0xc0016900,
 307         0x000002a5,
 308         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 309
 310         0xc0036900,
 311         0x000002ac,
 312         0x00000000, /* VGT_STRMOUT_EN */
 313         0x00000000, /* VGT_REUSE_OFF */
 314         0x00000000, /* VGT_VTX_CNT_EN */
 315
 316         0xc0016900,
 317         0x000000d4,
 318         0x00000000, /* SX_MISC */
 319
 320         0xc0016900,
 321         0x000002c8,
 322         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 323
 324         0xc0076900,
 325         0x00000202,
 326         0x00cc0000, /* CB_COLOR_CONTROL */
 327         0x00000210, /* DB_SHADER_CNTL */
 328         0x00010000, /* PA_CL_CLIP_CNTL */
 329         0x00000244, /* PA_SU_SC_MODE_CNTL */
 330         0x00000100, /* PA_CL_VTE_CNTL */
 331         0x00000000, /* PA_CL_VS_OUT_CNTL */
 332         0x00000000, /* PA_CL_NANINF_CNTL */
 333
 334         0xc0026900,
 335         0x0000008e,
 336         0x0000000f, /* CB_TARGET_MASK */
 337         0x0000000f, /* CB_SHADER_MASK */
 338
 339         0xc0016900,
 340         0x000001e8,
 341         0x00000001, /* CB_SHADER_CONTROL */
 342
 343         0xc0016900,
 344         0x00000185,
 345         0x00000000, /* SPI_VS_OUT_ID_0 */
 346
 347         0xc0016900,
 348         0x00000191,
 349         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 350
 351         0xc0056900,
 352         0x000001b1,
 353         0x00000000, /* SPI_VS_OUT_CONFIG */
 354         0x00000000, /* SPI_THREAD_GROUPING */
 355         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 356         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 357         0x00000000, /* SPI_INTERP_CONTROL_0 */
 358
 359         0xc0036e00, /* SET_SAMPLER */
 360         0x00000000,
 361         0x00000012,
 362         0x00000000,
 363         0x00000000,
 364 };
 365
 366 const u32 r7xx_default_state[] =
 367 {
 368         0xc0012800, /* CONTEXT_CONTROL */
 369         0x80000000,
 370         0x80000000,
 371
 372         0xc0016800,
 373         0x00000010,
 374         0x00008000, /* WAIT_UNTIL */
 375
 376         0xc0016800,
 377         0x00000542,
 378         0x07000002, /* TA_CNTL_AUX */
 379
 380         0xc0016800,
 381         0x000005c5,
 382         0x00000000, /* VC_ENHANCE */
 383
 384         0xc0016800,
 385         0x00000363,
 386         0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
 387
 388         0xc0016800,
 389         0x0000060c,
 390         0x00000000, /* DB_DEBUG */
 391
 392         0xc0016800,
 393         0x0000060e,
 394         0x00420204, /* DB_WATERMARKS */
 395
 396         0xc0026f00,
 397         0x00000000,
 398         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
 399         0x00000000, /* SQ_VTX_START_INST_LOC */
 400
 401         0xc0096900,
 402         0x0000022a,
 403         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
 404         0x00000000,
 405         0x00000000,
 406         0x00000000,
 407         0x00000000,
 408         0x00000000,
 409         0x00000000,
 410         0x00000000,
 411         0x00000000,
 412
 413         0xc0016900,
 414         0x00000004,
 415         0x00000000, /* DB_DEPTH_INFO */
 416
 417         0xc0026900,
 418         0x0000000a,
 419         0x00000000, /* DB_STENCIL_CLEAR */
 420         0x00000000, /* DB_DEPTH_CLEAR */
 421
 422         0xc0016900,
 423         0x00000200,
 424         0x00000000, /* DB_DEPTH_CONTROL */
 425
 426         0xc0026900,
 427         0x00000343,
 428         0x00000060, /* DB_RENDER_CONTROL */
 429         0x00000000, /* DB_RENDER_OVERRIDE */
 430
 431         0xc0016900,
 432         0x00000351,
 433         0x0000aa00, /* DB_ALPHA_TO_MASK */
 434
 435         0xc0096900,
 436         0x00000100,
 437         0x00000800, /* VGT_MAX_VTX_INDX */
 438         0x00000000, /* VGT_MIN_VTX_INDX */
 439         0x00000000, /* VGT_INDX_OFFSET */
 440         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 441         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 442         0x00000000, /* CB_BLEND_RED */
 443         0x00000000,
 444         0x00000000,
 445         0x00000000,
 446
 447         0xc0036900,
 448         0x0000010c,
 449         0x00000000, /* DB_STENCILREFMASK */
 450         0x00000000, /* DB_STENCILREFMASK_BF */
 451         0x00000000, /* SX_ALPHA_REF */
 452
 453         0xc0046900,
 454         0x0000030c, /* CB_CLRCMP_CNTL */
 455         0x01000000,
 456         0x00000000,
 457         0x00000000,
 458         0x00000000,
 459
 460         0xc0016900,
 461         0x00000080,
 462         0x00000000, /* PA_SC_WINDOW_OFFSET */
 463
 464         0xc00a6900,
 465         0x00000083,
 466         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 467         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 468         0x20002000,
 469         0x00000000,
 470         0x20002000,
 471         0x00000000,
 472         0x20002000,
 473         0x00000000,
 474         0x20002000,
 475         0xaaaaaaaa, /* PA_SC_EDGERULE */
 476
 477         0xc0406900,
 478         0x00000094,
 479         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 480         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 481         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 482         0x20002000,
 483         0x80000000,
 484         0x20002000,
 485         0x80000000,
 486         0x20002000,
 487         0x80000000,
 488         0x20002000,
 489         0x80000000,
 490         0x20002000,
 491         0x80000000,
 492         0x20002000,
 493         0x80000000,
 494         0x20002000,
 495         0x80000000,
 496         0x20002000,
 497         0x80000000,
 498         0x20002000,
 499         0x80000000,
 500         0x20002000,
 501         0x80000000,
 502         0x20002000,
 503         0x80000000,
 504         0x20002000,
 505         0x80000000,
 506         0x20002000,
 507         0x80000000,
 508         0x20002000,
 509         0x80000000,
 510         0x20002000,
 511         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 512         0x3f800000,
 513         0x00000000,
 514         0x3f800000,
 515         0x00000000,
 516         0x3f800000,
 517         0x00000000,
 518         0x3f800000,
 519         0x00000000,
 520         0x3f800000,
 521         0x00000000,
 522         0x3f800000,
 523         0x00000000,
 524         0x3f800000,
 525         0x00000000,
 526         0x3f800000,
 527         0x00000000,
 528         0x3f800000,
 529         0x00000000,
 530         0x3f800000,
 531         0x00000000,
 532         0x3f800000,
 533         0x00000000,
 534         0x3f800000,
 535         0x00000000,
 536         0x3f800000,
 537         0x00000000,
 538         0x3f800000,
 539         0x00000000,
 540         0x3f800000,
 541         0x00000000,
 542         0x3f800000,
 543
 544         0xc0026900,
 545         0x00000292,
 546         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 547         0x00514000, /* PA_SC_MODE_CNTL */
 548
 549         0xc0096900,
 550         0x00000300,
 551         0x00000000, /* PA_SC_LINE_CNTL */
 552         0x00000000, /* PA_SC_AA_CONFIG */
 553         0x0000002d, /* PA_SU_VTX_CNTL */
 554         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 555         0x3f800000,
 556         0x3f800000,
 557         0x3f800000,
 558         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 559         0x00000000,
 560
 561         0xc0016900,
 562         0x00000312,
 563         0xffffffff, /* PA_SC_AA_MASK */
 564
 565         0xc0066900,
 566         0x0000037e,
 567         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 568         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 569         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 570         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 571         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 572         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 573
 574         0xc0046900,
 575         0x000001b6,
 576         0x00000000, /* SPI_INPUT_Z */
 577         0x00000000, /* SPI_FOG_CNTL */
 578         0x00000000, /* SPI_FOG_FUNC_SCALE */
 579         0x00000000, /* SPI_FOG_FUNC_BIAS */
 580
 581         0xc0016900,
 582         0x00000225,
 583         0x00000000, /* SQ_PGM_START_FS */
 584
 585         0xc0016900,
 586         0x00000229,
 587         0x00000000, /* SQ_PGM_RESOURCES_FS */
 588
 589         0xc0016900,
 590         0x00000237,
 591         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 592
 593         0xc0026900,
 594         0x000002a8,
 595         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 596         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 597
 598         0xc0116900,
 599         0x00000280,
 600         0x00000000, /* PA_SU_POINT_SIZE */
 601         0x00000000, /* PA_SU_POINT_MINMAX */
 602         0x00000008, /* PA_SU_LINE_CNTL */
 603         0x00000000, /* PA_SC_LINE_STIPPLE */
 604         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 605         0x00000000, /* VGT_HOS_CNTL */
 606         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 607         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 608         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 609         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 610         0x00000000, /* VGT_GROUP_FIRST_DECR */
 611         0x00000000, /* VGT_GROUP_DECR */
 612         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 613         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 614         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 615         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 616         0x00000000, /* VGT_GS_MODE */
 617
 618         0xc0016900,
 619         0x000002a1,
 620         0x00000000, /* VGT_PRIMITIVEID_EN */
 621
 622         0xc0016900,
 623         0x000002a5,
 624         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 625
 626         0xc0036900,
 627         0x000002ac,
 628         0x00000000, /* VGT_STRMOUT_EN */
 629         0x00000000, /* VGT_REUSE_OFF */
 630         0x00000000, /* VGT_VTX_CNT_EN */
 631
 632         0xc0016900,
 633         0x000000d4,
 634         0x00000000, /* SX_MISC */
 635
 636         0xc0016900,
 637         0x000002c8,
 638         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 639
 640         0xc0076900,
 641         0x00000202,
 642         0x00cc0000, /* CB_COLOR_CONTROL */
 643         0x00000210, /* DB_SHADER_CNTL */
 644         0x00010000, /* PA_CL_CLIP_CNTL */
 645         0x00000244, /* PA_SU_SC_MODE_CNTL */
 646         0x00000100, /* PA_CL_VTE_CNTL */
 647         0x00000000, /* PA_CL_VS_OUT_CNTL */
 648         0x00000000, /* PA_CL_NANINF_CNTL */
 649
 650         0xc0026900,
 651         0x0000008e,
 652         0x0000000f, /* CB_TARGET_MASK */
 653         0x0000000f, /* CB_SHADER_MASK */
 654
 655         0xc0016900,
 656         0x000001e8,
 657         0x00000001, /* CB_SHADER_CONTROL */
 658
 659         0xc0016900,
 660         0x00000185,
 661         0x00000000, /* SPI_VS_OUT_ID_0 */
 662
 663         0xc0016900,
 664         0x00000191,
 665         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 666
 667         0xc0056900,
 668         0x000001b1,
 669         0x00000000, /* SPI_VS_OUT_CONFIG */
 670         0x00000001, /* SPI_THREAD_GROUPING */
 671         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 672         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 673         0x00000000, /* SPI_INTERP_CONTROL_0 */
 674
 675         0xc0036e00, /* SET_SAMPLER */
 676         0x00000000,
 677         0x00000012,
 678         0x00000000,
 679         0x00000000,
 680 };
 681
 682 /* same for r6xx/r7xx */
 683 const u32 r6xx_vs[] =
 684 {
 685         0x00000004,
 686         0x81000000,
 687         0x0000203c,
 688         0x94000b08,
 689         0x00004000,
 690         0x14200b1a,
 691         0x00000000,
 692         0x00000000,
 693         0x3c000000,
 694         0x68cd1000,
 695 #ifdef __BIG_ENDIAN
 696         0x000a0000,
 697 #else
 698         0x00080000,
 699 #endif
 700         0x00000000,
 701 };
 702
 703 const u32 r6xx_ps[] =
 704 {
 705         0x00000002,
 706         0x80800000,
 707         0x00000000,
 708         0x94200688,
 709         0x00000010,
 710         0x000d1000,
 711         0xb0800000,
 712         0x00000000,
 713 };
 714
 715 const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
 716 const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
 717 const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
 718 const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);