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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / gpu / drm / radeon / radeon_display.c
blob3d314338d8432398580a6789a78696f50c36871f
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
37 {
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 int i;
42
43 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
44 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
45
46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
49
50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
53
54 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
55 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
56 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
57
58 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
59 for (i = 0; i < 256; i++) {
60 WREG32(AVIVO_DC_LUT_30_COLOR,
61 (radeon_crtc->lut_r[i] << 20) |
62 (radeon_crtc->lut_g[i] << 10) |
63 (radeon_crtc->lut_b[i] << 0));
64 }
65
66 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
67 }
68
69 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
70 {
71 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
72 struct drm_device *dev = crtc->dev;
73 struct radeon_device *rdev = dev->dev_private;
74 int i;
75
76 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
77 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
78
79 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
86
87 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
88 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
89
90 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
91 for (i = 0; i < 256; i++) {
92 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
93 (radeon_crtc->lut_r[i] << 20) |
94 (radeon_crtc->lut_g[i] << 10) |
95 (radeon_crtc->lut_b[i] << 0));
96 }
97 }
98
99 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
100 {
101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
102 struct drm_device *dev = crtc->dev;
103 struct radeon_device *rdev = dev->dev_private;
104 int i;
105
106 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
107
108 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
109 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
110 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
111 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
112 NI_GRPH_PRESCALE_BYPASS);
113 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
114 NI_OVL_PRESCALE_BYPASS);
115 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
116 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
117 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
118
119 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
120
121 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
128
129 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
131
132 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
133 for (i = 0; i < 256; i++) {
134 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
135 (radeon_crtc->lut_r[i] << 20) |
136 (radeon_crtc->lut_g[i] << 10) |
137 (radeon_crtc->lut_b[i] << 0));
138 }
139
140 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
141 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
142 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
143 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
145 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
146 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
147 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
148 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
150 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
151 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
152 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
153 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
154 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
155 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
156
157 }
158
159 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
160 {
161 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
162 struct drm_device *dev = crtc->dev;
163 struct radeon_device *rdev = dev->dev_private;
164 int i;
165 uint32_t dac2_cntl;
166
167 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
168 if (radeon_crtc->crtc_id == 0)
169 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
170 else
171 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
172 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
173
174 WREG8(RADEON_PALETTE_INDEX, 0);
175 for (i = 0; i < 256; i++) {
176 WREG32(RADEON_PALETTE_30_DATA,
177 (radeon_crtc->lut_r[i] << 20) |
178 (radeon_crtc->lut_g[i] << 10) |
179 (radeon_crtc->lut_b[i] << 0));
180 }
181 }
182
183 void radeon_crtc_load_lut(struct drm_crtc *crtc)
184 {
185 struct drm_device *dev = crtc->dev;
186 struct radeon_device *rdev = dev->dev_private;
187
188 if (!crtc->enabled)
189 return;
190
191 if (ASIC_IS_DCE5(rdev))
192 dce5_crtc_load_lut(crtc);
193 else if (ASIC_IS_DCE4(rdev))
194 dce4_crtc_load_lut(crtc);
195 else if (ASIC_IS_AVIVO(rdev))
196 avivo_crtc_load_lut(crtc);
197 else
198 legacy_crtc_load_lut(crtc);
199 }
200
201 /** Sets the color ramps on behalf of fbcon */
202 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
203 u16 blue, int regno)
204 {
205 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
206
207 radeon_crtc->lut_r[regno] = red >> 6;
208 radeon_crtc->lut_g[regno] = green >> 6;
209 radeon_crtc->lut_b[regno] = blue >> 6;
210 }
211
212 /** Gets the color ramps on behalf of fbcon */
213 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
214 u16 *blue, int regno)
215 {
216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
217
218 *red = radeon_crtc->lut_r[regno] << 6;
219 *green = radeon_crtc->lut_g[regno] << 6;
220 *blue = radeon_crtc->lut_b[regno] << 6;
221 }
222
223 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, uint32_t start, uint32_t size)
225 {
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 int end = (start + size > 256) ? 256 : start + size, i;
228
229 /* userspace palettes are always correct as is */
230 for (i = start; i < end; i++) {
231 radeon_crtc->lut_r[i] = red[i] >> 6;
232 radeon_crtc->lut_g[i] = green[i] >> 6;
233 radeon_crtc->lut_b[i] = blue[i] >> 6;
234 }
235 radeon_crtc_load_lut(crtc);
236 }
237
238 static void radeon_crtc_destroy(struct drm_crtc *crtc)
239 {
240 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
241
242 drm_crtc_cleanup(crtc);
243 kfree(radeon_crtc);
244 }
245
246 /*
247 * Handle unpin events outside the interrupt handler proper.
248 */
249 static void radeon_unpin_work_func(struct work_struct *__work)
250 {
251 struct radeon_unpin_work *work =
252 container_of(__work, struct radeon_unpin_work, work);
253 int r;
254
255 /* unpin of the old buffer */
256 r = radeon_bo_reserve(work->old_rbo, false);
257 if (likely(r == 0)) {
258 r = radeon_bo_unpin(work->old_rbo);
259 if (unlikely(r != 0)) {
260 DRM_ERROR("failed to unpin buffer after flip\n");
261 }
262 radeon_bo_unreserve(work->old_rbo);
263 } else
264 DRM_ERROR("failed to reserve buffer after flip\n");
265
266 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
267 kfree(work);
268 }
269
270 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
271 {
272 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
273 struct radeon_unpin_work *work;
274 struct drm_pending_vblank_event *e;
275 struct timeval now;
276 unsigned long flags;
277 u32 update_pending;
278 int vpos, hpos;
279
280 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
281 work = radeon_crtc->unpin_work;
282 if (work == NULL ||
283 (work->fence && !radeon_fence_signaled(work->fence))) {
284 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
285 return;
286 }
287 /* New pageflip, or just completion of a previous one? */
288 if (!radeon_crtc->deferred_flip_completion) {
289 /* do the flip (mmio) */
290 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
291 } else {
292 /* This is just a completion of a flip queued in crtc
293 * at last invocation. Make sure we go directly to
294 * completion routine.
295 */
296 update_pending = 0;
297 radeon_crtc->deferred_flip_completion = 0;
298 }
299
300 /* Has the pageflip already completed in crtc, or is it certain
301 * to complete in this vblank?
302 */
303 if (update_pending &&
304 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
305 &vpos, &hpos)) &&
306 (vpos >=0) &&
307 (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
308 /* crtc didn't flip in this target vblank interval,
309 * but flip is pending in crtc. It will complete it
310 * in next vblank interval, so complete the flip at
311 * next vblank irq.
312 */
313 radeon_crtc->deferred_flip_completion = 1;
314 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
315 return;
316 }
317
318 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
319 radeon_crtc->unpin_work = NULL;
320
321 /* wakeup userspace */
322 if (work->event) {
323 e = work->event;
324 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
325 e->event.tv_sec = now.tv_sec;
326 e->event.tv_usec = now.tv_usec;
327 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
328 wake_up_interruptible(&e->base.file_priv->event_wait);
329 }
330 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
331
332 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
333 radeon_fence_unref(&work->fence);
334 radeon_post_page_flip(work->rdev, work->crtc_id);
335 schedule_work(&work->work);
336 }
337
338 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
339 struct drm_framebuffer *fb,
340 struct drm_pending_vblank_event *event)
341 {
342 struct drm_device *dev = crtc->dev;
343 struct radeon_device *rdev = dev->dev_private;
344 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
345 struct radeon_framebuffer *old_radeon_fb;
346 struct radeon_framebuffer *new_radeon_fb;
347 struct drm_gem_object *obj;
348 struct radeon_bo *rbo;
349 struct radeon_unpin_work *work;
350 unsigned long flags;
351 u32 tiling_flags, pitch_pixels;
352 u64 base;
353 int r;
354
355 work = kzalloc(sizeof *work, GFP_KERNEL);
356 if (work == NULL)
357 return -ENOMEM;
358
359 work->event = event;
360 work->rdev = rdev;
361 work->crtc_id = radeon_crtc->crtc_id;
362 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
363 new_radeon_fb = to_radeon_framebuffer(fb);
364 /* schedule unpin of the old buffer */
365 obj = old_radeon_fb->obj;
366 /* take a reference to the old object */
367 drm_gem_object_reference(obj);
368 rbo = gem_to_radeon_bo(obj);
369 work->old_rbo = rbo;
370 obj = new_radeon_fb->obj;
371 rbo = gem_to_radeon_bo(obj);
372 if (rbo->tbo.sync_obj)
373 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
374 INIT_WORK(&work->work, radeon_unpin_work_func);
375
376 /* We borrow the event spin lock for protecting unpin_work */
377 spin_lock_irqsave(&dev->event_lock, flags);
378 if (radeon_crtc->unpin_work) {
379 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
380 r = -EBUSY;
381 goto unlock_free;
382 }
383 radeon_crtc->unpin_work = work;
384 radeon_crtc->deferred_flip_completion = 0;
385 spin_unlock_irqrestore(&dev->event_lock, flags);
386
387 /* pin the new buffer */
388 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
389 work->old_rbo, rbo);
390
391 r = radeon_bo_reserve(rbo, false);
392 if (unlikely(r != 0)) {
393 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
394 goto pflip_cleanup;
395 }
396 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
397 if (unlikely(r != 0)) {
398 radeon_bo_unreserve(rbo);
399 r = -EINVAL;
400 DRM_ERROR("failed to pin new rbo buffer before flip\n");
401 goto pflip_cleanup;
402 }
403 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
404 radeon_bo_unreserve(rbo);
405
406 if (!ASIC_IS_AVIVO(rdev)) {
407 /* crtc offset is from display base addr not FB location */
408 base -= radeon_crtc->legacy_display_base_addr;
409 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
410
411 if (tiling_flags & RADEON_TILING_MACRO) {
412 if (ASIC_IS_R300(rdev)) {
413 base &= ~0x7ff;
414 } else {
415 int byteshift = fb->bits_per_pixel >> 4;
416 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
417 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
418 }
419 } else {
420 int offset = crtc->y * pitch_pixels + crtc->x;
421 switch (fb->bits_per_pixel) {
422 case 8:
423 default:
424 offset *= 1;
425 break;
426 case 15:
427 case 16:
428 offset *= 2;
429 break;
430 case 24:
431 offset *= 3;
432 break;
433 case 32:
434 offset *= 4;
435 break;
436 }
437 base += offset;
438 }
439 base &= ~7;
440 }
441
442 spin_lock_irqsave(&dev->event_lock, flags);
443 work->new_crtc_base = base;
444 spin_unlock_irqrestore(&dev->event_lock, flags);
445
446 /* update crtc fb */
447 crtc->fb = fb;
448
449 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
450 if (r) {
451 DRM_ERROR("failed to get vblank before flip\n");
452 goto pflip_cleanup1;
453 }
454
455 /* set the proper interrupt */
456 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
457
458 return 0;
459
460 pflip_cleanup1:
461 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
462 DRM_ERROR("failed to reserve new rbo in error path\n");
463 goto pflip_cleanup;
464 }
465 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
466 DRM_ERROR("failed to unpin new rbo in error path\n");
467 }
468 radeon_bo_unreserve(rbo);
469
470 pflip_cleanup:
471 spin_lock_irqsave(&dev->event_lock, flags);
472 radeon_crtc->unpin_work = NULL;
473 unlock_free:
474 spin_unlock_irqrestore(&dev->event_lock, flags);
475 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
476 radeon_fence_unref(&work->fence);
477 kfree(work);
478
479 return r;
480 }
481
482 static const struct drm_crtc_funcs radeon_crtc_funcs = {
483 .cursor_set = radeon_crtc_cursor_set,
484 .cursor_move = radeon_crtc_cursor_move,
485 .gamma_set = radeon_crtc_gamma_set,
486 .set_config = drm_crtc_helper_set_config,
487 .destroy = radeon_crtc_destroy,
488 .page_flip = radeon_crtc_page_flip,
489 };
490
491 static void radeon_crtc_init(struct drm_device *dev, int index)
492 {
493 struct radeon_device *rdev = dev->dev_private;
494 struct radeon_crtc *radeon_crtc;
495 int i;
496
497 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
498 if (radeon_crtc == NULL)
499 return;
500
501 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
502
503 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
504 radeon_crtc->crtc_id = index;
505 rdev->mode_info.crtcs[index] = radeon_crtc;
506
507 #if 0
508 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
509 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
510 radeon_crtc->mode_set.num_connectors = 0;
511 #endif
512
513 for (i = 0; i < 256; i++) {
514 radeon_crtc->lut_r[i] = i << 2;
515 radeon_crtc->lut_g[i] = i << 2;
516 radeon_crtc->lut_b[i] = i << 2;
517 }
518
519 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
520 radeon_atombios_init_crtc(dev, radeon_crtc);
521 else
522 radeon_legacy_init_crtc(dev, radeon_crtc);
523 }
524
525 static const char *encoder_names[36] = {
526 "NONE",
527 "INTERNAL_LVDS",
528 "INTERNAL_TMDS1",
529 "INTERNAL_TMDS2",
530 "INTERNAL_DAC1",
531 "INTERNAL_DAC2",
532 "INTERNAL_SDVOA",
533 "INTERNAL_SDVOB",
534 "SI170B",
535 "CH7303",
536 "CH7301",
537 "INTERNAL_DVO1",
538 "EXTERNAL_SDVOA",
539 "EXTERNAL_SDVOB",
540 "TITFP513",
541 "INTERNAL_LVTM1",
542 "VT1623",
543 "HDMI_SI1930",
544 "HDMI_INTERNAL",
545 "INTERNAL_KLDSCP_TMDS1",
546 "INTERNAL_KLDSCP_DVO1",
547 "INTERNAL_KLDSCP_DAC1",
548 "INTERNAL_KLDSCP_DAC2",
549 "SI178",
550 "MVPU_FPGA",
551 "INTERNAL_DDI",
552 "VT1625",
553 "HDMI_SI1932",
554 "DP_AN9801",
555 "DP_DP501",
556 "INTERNAL_UNIPHY",
557 "INTERNAL_KLDSCP_LVTMA",
558 "INTERNAL_UNIPHY1",
559 "INTERNAL_UNIPHY2",
560 "NUTMEG",
561 "TRAVIS",
562 };
563
564 static const char *connector_names[15] = {
565 "Unknown",
566 "VGA",
567 "DVI-I",
568 "DVI-D",
569 "DVI-A",
570 "Composite",
571 "S-video",
572 "LVDS",
573 "Component",
574 "DIN",
575 "DisplayPort",
576 "HDMI-A",
577 "HDMI-B",
578 "TV",
579 "eDP",
580 };
581
582 static const char *hpd_names[6] = {
583 "HPD1",
584 "HPD2",
585 "HPD3",
586 "HPD4",
587 "HPD5",
588 "HPD6",
589 };
590
591 static void radeon_print_display_setup(struct drm_device *dev)
592 {
593 struct drm_connector *connector;
594 struct radeon_connector *radeon_connector;
595 struct drm_encoder *encoder;
596 struct radeon_encoder *radeon_encoder;
597 uint32_t devices;
598 int i = 0;
599
600 DRM_INFO("Radeon Display Connectors\n");
601 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
602 radeon_connector = to_radeon_connector(connector);
603 DRM_INFO("Connector %d:\n", i);
604 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
605 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
606 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
607 if (radeon_connector->ddc_bus) {
608 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
609 radeon_connector->ddc_bus->rec.mask_clk_reg,
610 radeon_connector->ddc_bus->rec.mask_data_reg,
611 radeon_connector->ddc_bus->rec.a_clk_reg,
612 radeon_connector->ddc_bus->rec.a_data_reg,
613 radeon_connector->ddc_bus->rec.en_clk_reg,
614 radeon_connector->ddc_bus->rec.en_data_reg,
615 radeon_connector->ddc_bus->rec.y_clk_reg,
616 radeon_connector->ddc_bus->rec.y_data_reg);
617 if (radeon_connector->router.ddc_valid)
618 DRM_INFO(" DDC Router 0x%x/0x%x\n",
619 radeon_connector->router.ddc_mux_control_pin,
620 radeon_connector->router.ddc_mux_state);
621 if (radeon_connector->router.cd_valid)
622 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
623 radeon_connector->router.cd_mux_control_pin,
624 radeon_connector->router.cd_mux_state);
625 } else {
626 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
627 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
628 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
629 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
630 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
631 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
632 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
633 }
634 DRM_INFO(" Encoders:\n");
635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
636 radeon_encoder = to_radeon_encoder(encoder);
637 devices = radeon_encoder->devices & radeon_connector->devices;
638 if (devices) {
639 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
640 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
641 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
642 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
643 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
644 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
645 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
646 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
647 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
648 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
649 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
650 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
651 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
652 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
653 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
654 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
655 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
656 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
657 if (devices & ATOM_DEVICE_TV1_SUPPORT)
658 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
659 if (devices & ATOM_DEVICE_CV_SUPPORT)
660 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
661 }
662 }
663 i++;
664 }
665 }
666
667 static bool radeon_setup_enc_conn(struct drm_device *dev)
668 {
669 struct radeon_device *rdev = dev->dev_private;
670 bool ret = false;
671
672 if (rdev->bios) {
673 if (rdev->is_atom_bios) {
674 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
675 if (ret == false)
676 ret = radeon_get_atom_connector_info_from_object_table(dev);
677 } else {
678 ret = radeon_get_legacy_connector_info_from_bios(dev);
679 if (ret == false)
680 ret = radeon_get_legacy_connector_info_from_table(dev);
681 }
682 } else {
683 if (!ASIC_IS_AVIVO(rdev))
684 ret = radeon_get_legacy_connector_info_from_table(dev);
685 }
686 if (ret) {
687 radeon_setup_encoder_clones(dev);
688 radeon_print_display_setup(dev);
689 }
690
691 return ret;
692 }
693
694 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
695 {
696 struct drm_device *dev = radeon_connector->base.dev;
697 struct radeon_device *rdev = dev->dev_private;
698 int ret = 0;
699
700 /* on hw with routers, select right port */
701 if (radeon_connector->router.ddc_valid)
702 radeon_router_select_ddc_port(radeon_connector);
703
704 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
705 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
706 (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
707 ENCODER_OBJECT_ID_NONE)) {
708 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
709
710 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
711 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
712 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
713 &dig->dp_i2c_bus->adapter);
714 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
715 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
716 &radeon_connector->ddc_bus->adapter);
717 } else {
718 if (radeon_connector->ddc_bus && !radeon_connector->edid)
719 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
720 &radeon_connector->ddc_bus->adapter);
721 }
722
723 if (!radeon_connector->edid) {
724 if (rdev->is_atom_bios) {
725 /* some laptops provide a hardcoded edid in rom for LCDs */
726 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
727 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
728 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
729 } else
730 /* some servers provide a hardcoded edid in rom for KVMs */
731 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
732 }
733 if (radeon_connector->edid) {
734 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
735 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
736 return ret;
737 }
738 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
739 return 0;
740 }
741
742 /* avivo */
743 static void avivo_get_fb_div(struct radeon_pll *pll,
744 u32 target_clock,
745 u32 post_div,
746 u32 ref_div,
747 u32 *fb_div,
748 u32 *frac_fb_div)
749 {
750 u32 tmp = post_div * ref_div;
751
752 tmp *= target_clock;
753 *fb_div = tmp / pll->reference_freq;
754 *frac_fb_div = tmp % pll->reference_freq;
755
756 if (*fb_div > pll->max_feedback_div)
757 *fb_div = pll->max_feedback_div;
758 else if (*fb_div < pll->min_feedback_div)
759 *fb_div = pll->min_feedback_div;
760 }
761
762 static u32 avivo_get_post_div(struct radeon_pll *pll,
763 u32 target_clock)
764 {
765 u32 vco, post_div, tmp;
766
767 if (pll->flags & RADEON_PLL_USE_POST_DIV)
768 return pll->post_div;
769
770 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
771 if (pll->flags & RADEON_PLL_IS_LCD)
772 vco = pll->lcd_pll_out_min;
773 else
774 vco = pll->pll_out_min;
775 } else {
776 if (pll->flags & RADEON_PLL_IS_LCD)
777 vco = pll->lcd_pll_out_max;
778 else
779 vco = pll->pll_out_max;
780 }
781
782 post_div = vco / target_clock;
783 tmp = vco % target_clock;
784
785 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
786 if (tmp)
787 post_div++;
788 } else {
789 if (!tmp)
790 post_div--;
791 }
792
793 if (post_div > pll->max_post_div)
794 post_div = pll->max_post_div;
795 else if (post_div < pll->min_post_div)
796 post_div = pll->min_post_div;
797
798 return post_div;
799 }
800
801 #define MAX_TOLERANCE 10
802
803 void radeon_compute_pll_avivo(struct radeon_pll *pll,
804 u32 freq,
805 u32 *dot_clock_p,
806 u32 *fb_div_p,
807 u32 *frac_fb_div_p,
808 u32 *ref_div_p,
809 u32 *post_div_p)
810 {
811 u32 target_clock = freq / 10;
812 u32 post_div = avivo_get_post_div(pll, target_clock);
813 u32 ref_div = pll->min_ref_div;
814 u32 fb_div = 0, frac_fb_div = 0, tmp;
815
816 if (pll->flags & RADEON_PLL_USE_REF_DIV)
817 ref_div = pll->reference_div;
818
819 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
820 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
821 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
822 if (frac_fb_div >= 5) {
823 frac_fb_div -= 5;
824 frac_fb_div = frac_fb_div / 10;
825 frac_fb_div++;
826 }
827 if (frac_fb_div >= 10) {
828 fb_div++;
829 frac_fb_div = 0;
830 }
831 } else {
832 while (ref_div <= pll->max_ref_div) {
833 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
834 &fb_div, &frac_fb_div);
835 if (frac_fb_div >= (pll->reference_freq / 2))
836 fb_div++;
837 frac_fb_div = 0;
838 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
839 tmp = (tmp * 10000) / target_clock;
840
841 if (tmp > (10000 + MAX_TOLERANCE))
842 ref_div++;
843 else if (tmp >= (10000 - MAX_TOLERANCE))
844 break;
845 else
846 ref_div++;
847 }
848 }
849
850 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
851 (ref_div * post_div * 10);
852 *fb_div_p = fb_div;
853 *frac_fb_div_p = frac_fb_div;
854 *ref_div_p = ref_div;
855 *post_div_p = post_div;
856 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
857 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
858 }
859
860 /* pre-avivo */
861 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
862 {
863 uint64_t mod;
864
865 n += d / 2;
866
867 mod = do_div(n, d);
868 return n;
869 }
870
871 void radeon_compute_pll_legacy(struct radeon_pll *pll,
872 uint64_t freq,
873 uint32_t *dot_clock_p,
874 uint32_t *fb_div_p,
875 uint32_t *frac_fb_div_p,
876 uint32_t *ref_div_p,
877 uint32_t *post_div_p)
878 {
879 uint32_t min_ref_div = pll->min_ref_div;
880 uint32_t max_ref_div = pll->max_ref_div;
881 uint32_t min_post_div = pll->min_post_div;
882 uint32_t max_post_div = pll->max_post_div;
883 uint32_t min_fractional_feed_div = 0;
884 uint32_t max_fractional_feed_div = 0;
885 uint32_t best_vco = pll->best_vco;
886 uint32_t best_post_div = 1;
887 uint32_t best_ref_div = 1;
888 uint32_t best_feedback_div = 1;
889 uint32_t best_frac_feedback_div = 0;
890 uint32_t best_freq = -1;
891 uint32_t best_error = 0xffffffff;
892 uint32_t best_vco_diff = 1;
893 uint32_t post_div;
894 u32 pll_out_min, pll_out_max;
895
896 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
897 freq = freq * 1000;
898
899 if (pll->flags & RADEON_PLL_IS_LCD) {
900 pll_out_min = pll->lcd_pll_out_min;
901 pll_out_max = pll->lcd_pll_out_max;
902 } else {
903 pll_out_min = pll->pll_out_min;
904 pll_out_max = pll->pll_out_max;
905 }
906
907 if (pll_out_min > 64800)
908 pll_out_min = 64800;
909
910 if (pll->flags & RADEON_PLL_USE_REF_DIV)
911 min_ref_div = max_ref_div = pll->reference_div;
912 else {
913 while (min_ref_div < max_ref_div-1) {
914 uint32_t mid = (min_ref_div + max_ref_div) / 2;
915 uint32_t pll_in = pll->reference_freq / mid;
916 if (pll_in < pll->pll_in_min)
917 max_ref_div = mid;
918 else if (pll_in > pll->pll_in_max)
919 min_ref_div = mid;
920 else
921 break;
922 }
923 }
924
925 if (pll->flags & RADEON_PLL_USE_POST_DIV)
926 min_post_div = max_post_div = pll->post_div;
927
928 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
929 min_fractional_feed_div = pll->min_frac_feedback_div;
930 max_fractional_feed_div = pll->max_frac_feedback_div;
931 }
932
933 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
934 uint32_t ref_div;
935
936 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
937 continue;
938
939 /* legacy radeons only have a few post_divs */
940 if (pll->flags & RADEON_PLL_LEGACY) {
941 if ((post_div == 5) ||
942 (post_div == 7) ||
943 (post_div == 9) ||
944 (post_div == 10) ||
945 (post_div == 11) ||
946 (post_div == 13) ||
947 (post_div == 14) ||
948 (post_div == 15))
949 continue;
950 }
951
952 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
953 uint32_t feedback_div, current_freq = 0, error, vco_diff;
954 uint32_t pll_in = pll->reference_freq / ref_div;
955 uint32_t min_feed_div = pll->min_feedback_div;
956 uint32_t max_feed_div = pll->max_feedback_div + 1;
957
958 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
959 continue;
960
961 while (min_feed_div < max_feed_div) {
962 uint32_t vco;
963 uint32_t min_frac_feed_div = min_fractional_feed_div;
964 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
965 uint32_t frac_feedback_div;
966 uint64_t tmp;
967
968 feedback_div = (min_feed_div + max_feed_div) / 2;
969
970 tmp = (uint64_t)pll->reference_freq * feedback_div;
971 vco = radeon_div(tmp, ref_div);
972
973 if (vco < pll_out_min) {
974 min_feed_div = feedback_div + 1;
975 continue;
976 } else if (vco > pll_out_max) {
977 max_feed_div = feedback_div;
978 continue;
979 }
980
981 while (min_frac_feed_div < max_frac_feed_div) {
982 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
983 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
984 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
985 current_freq = radeon_div(tmp, ref_div * post_div);
986
987 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
988 if (freq < current_freq)
989 error = 0xffffffff;
990 else
991 error = freq - current_freq;
992 } else
993 error = abs(current_freq - freq);
994 vco_diff = abs(vco - best_vco);
995
996 if ((best_vco == 0 && error < best_error) ||
997 (best_vco != 0 &&
998 ((best_error > 100 && error < best_error - 100) ||
999 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1000 best_post_div = post_div;
1001 best_ref_div = ref_div;
1002 best_feedback_div = feedback_div;
1003 best_frac_feedback_div = frac_feedback_div;
1004 best_freq = current_freq;
1005 best_error = error;
1006 best_vco_diff = vco_diff;
1007 } else if (current_freq == freq) {
1008 if (best_freq == -1) {
1009 best_post_div = post_div;
1010 best_ref_div = ref_div;
1011 best_feedback_div = feedback_div;
1012 best_frac_feedback_div = frac_feedback_div;
1013 best_freq = current_freq;
1014 best_error = error;
1015 best_vco_diff = vco_diff;
1016 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1017 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1018 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1019 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1020 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1021 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1022 best_post_div = post_div;
1023 best_ref_div = ref_div;
1024 best_feedback_div = feedback_div;
1025 best_frac_feedback_div = frac_feedback_div;
1026 best_freq = current_freq;
1027 best_error = error;
1028 best_vco_diff = vco_diff;
1029 }
1030 }
1031 if (current_freq < freq)
1032 min_frac_feed_div = frac_feedback_div + 1;
1033 else
1034 max_frac_feed_div = frac_feedback_div;
1035 }
1036 if (current_freq < freq)
1037 min_feed_div = feedback_div + 1;
1038 else
1039 max_feed_div = feedback_div;
1040 }
1041 }
1042 }
1043
1044 *dot_clock_p = best_freq / 10000;
1045 *fb_div_p = best_feedback_div;
1046 *frac_fb_div_p = best_frac_feedback_div;
1047 *ref_div_p = best_ref_div;
1048 *post_div_p = best_post_div;
1049 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1050 (long long)freq,
1051 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1052 best_ref_div, best_post_div);
1053
1054 }
1055
1056 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1057 {
1058 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1059
1060 if (radeon_fb->obj) {
1061 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1062 }
1063 drm_framebuffer_cleanup(fb);
1064 kfree(radeon_fb);
1065 }
1066
1067 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1068 struct drm_file *file_priv,
1069 unsigned int *handle)
1070 {
1071 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1072
1073 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1074 }
1075
1076 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1077 .destroy = radeon_user_framebuffer_destroy,
1078 .create_handle = radeon_user_framebuffer_create_handle,
1079 };
1080
1081 int
1082 radeon_framebuffer_init(struct drm_device *dev,
1083 struct radeon_framebuffer *rfb,
1084 struct drm_mode_fb_cmd2 *mode_cmd,
1085 struct drm_gem_object *obj)
1086 {
1087 int ret;
1088 rfb->obj = obj;
1089 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1090 if (ret) {
1091 rfb->obj = NULL;
1092 return ret;
1093 }
1094 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1095 return 0;
1096 }
1097
1098 static struct drm_framebuffer *
1099 radeon_user_framebuffer_create(struct drm_device *dev,
1100 struct drm_file *file_priv,
1101 struct drm_mode_fb_cmd2 *mode_cmd)
1102 {
1103 struct drm_gem_object *obj;
1104 struct radeon_framebuffer *radeon_fb;
1105 int ret;
1106
1107 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1108 if (obj == NULL) {
1109 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1110 "can't create framebuffer\n", mode_cmd->handles[0]);
1111 return ERR_PTR(-ENOENT);
1112 }
1113
1114 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1115 if (radeon_fb == NULL)
1116 return ERR_PTR(-ENOMEM);
1117
1118 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1119 if (ret) {
1120 kfree(radeon_fb);
1121 drm_gem_object_unreference_unlocked(obj);
1122 return NULL;
1123 }
1124
1125 return &radeon_fb->base;
1126 }
1127
1128 static void radeon_output_poll_changed(struct drm_device *dev)
1129 {
1130 struct radeon_device *rdev = dev->dev_private;
1131 radeon_fb_output_poll_changed(rdev);
1132 }
1133
1134 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1135 .fb_create = radeon_user_framebuffer_create,
1136 .output_poll_changed = radeon_output_poll_changed
1137 };
1138
1139 struct drm_prop_enum_list {
1140 int type;
1141 char *name;
1142 };
1143
1144 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1145 { { 0, "driver" },
1146 { 1, "bios" },
1147 };
1148
1149 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1150 { { TV_STD_NTSC, "ntsc" },
1151 { TV_STD_PAL, "pal" },
1152 { TV_STD_PAL_M, "pal-m" },
1153 { TV_STD_PAL_60, "pal-60" },
1154 { TV_STD_NTSC_J, "ntsc-j" },
1155 { TV_STD_SCART_PAL, "scart-pal" },
1156 { TV_STD_PAL_CN, "pal-cn" },
1157 { TV_STD_SECAM, "secam" },
1158 };
1159
1160 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1161 { { UNDERSCAN_OFF, "off" },
1162 { UNDERSCAN_ON, "on" },
1163 { UNDERSCAN_AUTO, "auto" },
1164 };
1165
1166 static int radeon_modeset_create_props(struct radeon_device *rdev)
1167 {
1168 int i, sz;
1169
1170 if (rdev->is_atom_bios) {
1171 rdev->mode_info.coherent_mode_property =
1172 drm_property_create(rdev->ddev,
1173 DRM_MODE_PROP_RANGE,
1174 "coherent", 2);
1175 if (!rdev->mode_info.coherent_mode_property)
1176 return -ENOMEM;
1177
1178 rdev->mode_info.coherent_mode_property->values[0] = 0;
1179 rdev->mode_info.coherent_mode_property->values[1] = 1;
1180 }
1181
1182 if (!ASIC_IS_AVIVO(rdev)) {
1183 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1184 rdev->mode_info.tmds_pll_property =
1185 drm_property_create(rdev->ddev,
1186 DRM_MODE_PROP_ENUM,
1187 "tmds_pll", sz);
1188 for (i = 0; i < sz; i++) {
1189 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
1190 i,
1191 radeon_tmds_pll_enum_list[i].type,
1192 radeon_tmds_pll_enum_list[i].name);
1193 }
1194 }
1195
1196 rdev->mode_info.load_detect_property =
1197 drm_property_create(rdev->ddev,
1198 DRM_MODE_PROP_RANGE,
1199 "load detection", 2);
1200 if (!rdev->mode_info.load_detect_property)
1201 return -ENOMEM;
1202 rdev->mode_info.load_detect_property->values[0] = 0;
1203 rdev->mode_info.load_detect_property->values[1] = 1;
1204
1205 drm_mode_create_scaling_mode_property(rdev->ddev);
1206
1207 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1208 rdev->mode_info.tv_std_property =
1209 drm_property_create(rdev->ddev,
1210 DRM_MODE_PROP_ENUM,
1211 "tv standard", sz);
1212 for (i = 0; i < sz; i++) {
1213 drm_property_add_enum(rdev->mode_info.tv_std_property,
1214 i,
1215 radeon_tv_std_enum_list[i].type,
1216 radeon_tv_std_enum_list[i].name);
1217 }
1218
1219 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1220 rdev->mode_info.underscan_property =
1221 drm_property_create(rdev->ddev,
1222 DRM_MODE_PROP_ENUM,
1223 "underscan", sz);
1224 for (i = 0; i < sz; i++) {
1225 drm_property_add_enum(rdev->mode_info.underscan_property,
1226 i,
1227 radeon_underscan_enum_list[i].type,
1228 radeon_underscan_enum_list[i].name);
1229 }
1230
1231 rdev->mode_info.underscan_hborder_property =
1232 drm_property_create(rdev->ddev,
1233 DRM_MODE_PROP_RANGE,
1234 "underscan hborder", 2);
1235 if (!rdev->mode_info.underscan_hborder_property)
1236 return -ENOMEM;
1237 rdev->mode_info.underscan_hborder_property->values[0] = 0;
1238 rdev->mode_info.underscan_hborder_property->values[1] = 128;
1239
1240 rdev->mode_info.underscan_vborder_property =
1241 drm_property_create(rdev->ddev,
1242 DRM_MODE_PROP_RANGE,
1243 "underscan vborder", 2);
1244 if (!rdev->mode_info.underscan_vborder_property)
1245 return -ENOMEM;
1246 rdev->mode_info.underscan_vborder_property->values[0] = 0;
1247 rdev->mode_info.underscan_vborder_property->values[1] = 128;
1248
1249 return 0;
1250 }
1251
1252 void radeon_update_display_priority(struct radeon_device *rdev)
1253 {
1254 /* adjustment options for the display watermarks */
1255 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1256 /* set display priority to high for r3xx, rv515 chips
1257 * this avoids flickering due to underflow to the
1258 * display controllers during heavy acceleration.
1259 * Don't force high on rs4xx igp chips as it seems to
1260 * affect the sound card. See kernel bug 15982.
1261 */
1262 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1263 !(rdev->flags & RADEON_IS_IGP))
1264 rdev->disp_priority = 2;
1265 else
1266 rdev->disp_priority = 0;
1267 } else
1268 rdev->disp_priority = radeon_disp_priority;
1269
1270 }
1271
1272 int radeon_modeset_init(struct radeon_device *rdev)
1273 {
1274 int i;
1275 int ret;
1276
1277 drm_mode_config_init(rdev->ddev);
1278 rdev->mode_info.mode_config_initialized = true;
1279
1280 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1281
1282 if (ASIC_IS_DCE5(rdev)) {
1283 rdev->ddev->mode_config.max_width = 16384;
1284 rdev->ddev->mode_config.max_height = 16384;
1285 } else if (ASIC_IS_AVIVO(rdev)) {
1286 rdev->ddev->mode_config.max_width = 8192;
1287 rdev->ddev->mode_config.max_height = 8192;
1288 } else {
1289 rdev->ddev->mode_config.max_width = 4096;
1290 rdev->ddev->mode_config.max_height = 4096;
1291 }
1292
1293 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1294
1295 ret = radeon_modeset_create_props(rdev);
1296 if (ret) {
1297 return ret;
1298 }
1299
1300 /* init i2c buses */
1301 radeon_i2c_init(rdev);
1302
1303 /* check combios for a valid hardcoded EDID - Sun servers */
1304 if (!rdev->is_atom_bios) {
1305 /* check for hardcoded EDID in BIOS */
1306 radeon_combios_check_hardcoded_edid(rdev);
1307 }
1308
1309 /* allocate crtcs */
1310 for (i = 0; i < rdev->num_crtc; i++) {
1311 radeon_crtc_init(rdev->ddev, i);
1312 }
1313
1314 /* okay we should have all the bios connectors */
1315 ret = radeon_setup_enc_conn(rdev->ddev);
1316 if (!ret) {
1317 return ret;
1318 }
1319
1320 /* init dig PHYs, disp eng pll */
1321 if (rdev->is_atom_bios) {
1322 radeon_atom_encoder_init(rdev);
1323 radeon_atom_dcpll_init(rdev);
1324 }
1325
1326 /* initialize hpd */
1327 radeon_hpd_init(rdev);
1328
1329 /* Initialize power management */
1330 radeon_pm_init(rdev);
1331
1332 radeon_fbdev_init(rdev);
1333 drm_kms_helper_poll_init(rdev->ddev);
1334
1335 return 0;
1336 }
1337
1338 void radeon_modeset_fini(struct radeon_device *rdev)
1339 {
1340 radeon_fbdev_fini(rdev);
1341 kfree(rdev->mode_info.bios_hardcoded_edid);
1342 radeon_pm_fini(rdev);
1343
1344 if (rdev->mode_info.mode_config_initialized) {
1345 drm_kms_helper_poll_fini(rdev->ddev);
1346 radeon_hpd_fini(rdev);
1347 drm_mode_config_cleanup(rdev->ddev);
1348 rdev->mode_info.mode_config_initialized = false;
1349 }
1350 /* free i2c buses */
1351 radeon_i2c_fini(rdev);
1352 }
1353
1354 static bool is_hdtv_mode(struct drm_display_mode *mode)
1355 {
1356 /* try and guess if this is a tv or a monitor */
1357 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1358 (mode->vdisplay == 576) || /* 576p */
1359 (mode->vdisplay == 720) || /* 720p */
1360 (mode->vdisplay == 1080)) /* 1080p */
1361 return true;
1362 else
1363 return false;
1364 }
1365
1366 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1367 struct drm_display_mode *mode,
1368 struct drm_display_mode *adjusted_mode)
1369 {
1370 struct drm_device *dev = crtc->dev;
1371 struct radeon_device *rdev = dev->dev_private;
1372 struct drm_encoder *encoder;
1373 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1374 struct radeon_encoder *radeon_encoder;
1375 struct drm_connector *connector;
1376 struct radeon_connector *radeon_connector;
1377 bool first = true;
1378 u32 src_v = 1, dst_v = 1;
1379 u32 src_h = 1, dst_h = 1;
1380
1381 radeon_crtc->h_border = 0;
1382 radeon_crtc->v_border = 0;
1383
1384 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1385 if (encoder->crtc != crtc)
1386 continue;
1387 radeon_encoder = to_radeon_encoder(encoder);
1388 connector = radeon_get_connector_for_encoder(encoder);
1389 radeon_connector = to_radeon_connector(connector);
1390
1391 if (first) {
1392 /* set scaling */
1393 if (radeon_encoder->rmx_type == RMX_OFF)
1394 radeon_crtc->rmx_type = RMX_OFF;
1395 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1396 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1397 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1398 else
1399 radeon_crtc->rmx_type = RMX_OFF;
1400 /* copy native mode */
1401 memcpy(&radeon_crtc->native_mode,
1402 &radeon_encoder->native_mode,
1403 sizeof(struct drm_display_mode));
1404 src_v = crtc->mode.vdisplay;
1405 dst_v = radeon_crtc->native_mode.vdisplay;
1406 src_h = crtc->mode.hdisplay;
1407 dst_h = radeon_crtc->native_mode.hdisplay;
1408
1409 /* fix up for overscan on hdmi */
1410 if (ASIC_IS_AVIVO(rdev) &&
1411 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1412 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1413 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1414 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1415 is_hdtv_mode(mode)))) {
1416 if (radeon_encoder->underscan_hborder != 0)
1417 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1418 else
1419 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1420 if (radeon_encoder->underscan_vborder != 0)
1421 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1422 else
1423 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1424 radeon_crtc->rmx_type = RMX_FULL;
1425 src_v = crtc->mode.vdisplay;
1426 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1427 src_h = crtc->mode.hdisplay;
1428 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1429 }
1430 first = false;
1431 } else {
1432 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1433 /* WARNING: Right now this can't happen but
1434 * in the future we need to check that scaling
1435 * are consistent across different encoder
1436 * (ie all encoder can work with the same
1437 * scaling).
1438 */
1439 DRM_ERROR("Scaling not consistent across encoder.\n");
1440 return false;
1441 }
1442 }
1443 }
1444 if (radeon_crtc->rmx_type != RMX_OFF) {
1445 fixed20_12 a, b;
1446 a.full = dfixed_const(src_v);
1447 b.full = dfixed_const(dst_v);
1448 radeon_crtc->vsc.full = dfixed_div(a, b);
1449 a.full = dfixed_const(src_h);
1450 b.full = dfixed_const(dst_h);
1451 radeon_crtc->hsc.full = dfixed_div(a, b);
1452 } else {
1453 radeon_crtc->vsc.full = dfixed_const(1);
1454 radeon_crtc->hsc.full = dfixed_const(1);
1455 }
1456 return true;
1457 }
1458
1459 /*
1460 * Retrieve current video scanout position of crtc on a given gpu.
1461 *
1462 * \param dev Device to query.
1463 * \param crtc Crtc to query.
1464 * \param *vpos Location where vertical scanout position should be stored.
1465 * \param *hpos Location where horizontal scanout position should go.
1466 *
1467 * Returns vpos as a positive number while in active scanout area.
1468 * Returns vpos as a negative number inside vblank, counting the number
1469 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1470 * until start of active scanout / end of vblank."
1471 *
1472 * \return Flags, or'ed together as follows:
1473 *
1474 * DRM_SCANOUTPOS_VALID = Query successful.
1475 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1476 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1477 * this flag means that returned position may be offset by a constant but
1478 * unknown small number of scanlines wrt. real scanout position.
1479 *
1480 */
1481 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1482 {
1483 u32 stat_crtc = 0, vbl = 0, position = 0;
1484 int vbl_start, vbl_end, vtotal, ret = 0;
1485 bool in_vbl = true;
1486
1487 struct radeon_device *rdev = dev->dev_private;
1488
1489 if (ASIC_IS_DCE4(rdev)) {
1490 if (crtc == 0) {
1491 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1492 EVERGREEN_CRTC0_REGISTER_OFFSET);
1493 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1494 EVERGREEN_CRTC0_REGISTER_OFFSET);
1495 ret |= DRM_SCANOUTPOS_VALID;
1496 }
1497 if (crtc == 1) {
1498 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1499 EVERGREEN_CRTC1_REGISTER_OFFSET);
1500 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1501 EVERGREEN_CRTC1_REGISTER_OFFSET);
1502 ret |= DRM_SCANOUTPOS_VALID;
1503 }
1504 if (crtc == 2) {
1505 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1506 EVERGREEN_CRTC2_REGISTER_OFFSET);
1507 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1508 EVERGREEN_CRTC2_REGISTER_OFFSET);
1509 ret |= DRM_SCANOUTPOS_VALID;
1510 }
1511 if (crtc == 3) {
1512 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1513 EVERGREEN_CRTC3_REGISTER_OFFSET);
1514 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1515 EVERGREEN_CRTC3_REGISTER_OFFSET);
1516 ret |= DRM_SCANOUTPOS_VALID;
1517 }
1518 if (crtc == 4) {
1519 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1520 EVERGREEN_CRTC4_REGISTER_OFFSET);
1521 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1522 EVERGREEN_CRTC4_REGISTER_OFFSET);
1523 ret |= DRM_SCANOUTPOS_VALID;
1524 }
1525 if (crtc == 5) {
1526 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1527 EVERGREEN_CRTC5_REGISTER_OFFSET);
1528 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1529 EVERGREEN_CRTC5_REGISTER_OFFSET);
1530 ret |= DRM_SCANOUTPOS_VALID;
1531 }
1532 } else if (ASIC_IS_AVIVO(rdev)) {
1533 if (crtc == 0) {
1534 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1535 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1536 ret |= DRM_SCANOUTPOS_VALID;
1537 }
1538 if (crtc == 1) {
1539 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1540 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1541 ret |= DRM_SCANOUTPOS_VALID;
1542 }
1543 } else {
1544 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1545 if (crtc == 0) {
1546 /* Assume vbl_end == 0, get vbl_start from
1547 * upper 16 bits.
1548 */
1549 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1550 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1551 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1552 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1553 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1554 if (!(stat_crtc & 1))
1555 in_vbl = false;
1556
1557 ret |= DRM_SCANOUTPOS_VALID;
1558 }
1559 if (crtc == 1) {
1560 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1561 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1562 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1563 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1564 if (!(stat_crtc & 1))
1565 in_vbl = false;
1566
1567 ret |= DRM_SCANOUTPOS_VALID;
1568 }
1569 }
1570
1571 /* Decode into vertical and horizontal scanout position. */
1572 *vpos = position & 0x1fff;
1573 *hpos = (position >> 16) & 0x1fff;
1574
1575 /* Valid vblank area boundaries from gpu retrieved? */
1576 if (vbl > 0) {
1577 /* Yes: Decode. */
1578 ret |= DRM_SCANOUTPOS_ACCURATE;
1579 vbl_start = vbl & 0x1fff;
1580 vbl_end = (vbl >> 16) & 0x1fff;
1581 }
1582 else {
1583 /* No: Fake something reasonable which gives at least ok results. */
1584 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1585 vbl_end = 0;
1586 }
1587
1588 /* Test scanout position against vblank region. */
1589 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1590 in_vbl = false;
1591
1592 /* Check if inside vblank area and apply corrective offsets:
1593 * vpos will then be >=0 in video scanout area, but negative
1594 * within vblank area, counting down the number of lines until
1595 * start of scanout.
1596 */
1597
1598 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1599 if (in_vbl && (*vpos >= vbl_start)) {
1600 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1601 *vpos = *vpos - vtotal;
1602 }
1603
1604 /* Correct for shifted end of vbl at vbl_end. */
1605 *vpos = *vpos - vbl_end;
1606
1607 /* In vblank? */
1608 if (in_vbl)
1609 ret |= DRM_SCANOUTPOS_INVBL;
1610
1611 return ret;
1612 }