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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / gpu / drm / radeon / rv515.c
blob959bf4483beab43766d795ba75002f40c3d04558
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "rv515d.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "atom.h"
35 #include "rv515_reg_safe.h"
36
37 /* This files gather functions specifics to: rv515 */
38 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
42
43 void rv515_debugfs(struct radeon_device *rdev)
44 {
45 if (r100_debugfs_rbbm_init(rdev)) {
46 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
47 }
48 if (rv515_debugfs_pipes_info_init(rdev)) {
49 DRM_ERROR("Failed to register debugfs file for pipes !\n");
50 }
51 if (rv515_debugfs_ga_info_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for pipes !\n");
53 }
54 }
55
56 void rv515_ring_start(struct radeon_device *rdev)
57 {
58 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
59 int r;
60
61 r = radeon_ring_lock(rdev, ring, 64);
62 if (r) {
63 return;
64 }
65 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
66 radeon_ring_write(ring,
67 ISYNC_ANY2D_IDLE3D |
68 ISYNC_ANY3D_IDLE2D |
69 ISYNC_WAIT_IDLEGUI |
70 ISYNC_CPSCRATCH_IDLEGUI);
71 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
72 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
73 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
74 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
75 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
76 radeon_ring_write(ring, 0);
77 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
78 radeon_ring_write(ring, 0);
79 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
80 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
81 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
82 radeon_ring_write(ring, 0);
83 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
84 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
85 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
86 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
87 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
88 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
89 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
90 radeon_ring_write(ring, 0);
91 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
92 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
93 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
94 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
95 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
96 radeon_ring_write(ring,
97 ((6 << MS_X0_SHIFT) |
98 (6 << MS_Y0_SHIFT) |
99 (6 << MS_X1_SHIFT) |
100 (6 << MS_Y1_SHIFT) |
101 (6 << MS_X2_SHIFT) |
102 (6 << MS_Y2_SHIFT) |
103 (6 << MSBD0_Y_SHIFT) |
104 (6 << MSBD0_X_SHIFT)));
105 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
106 radeon_ring_write(ring,
107 ((6 << MS_X3_SHIFT) |
108 (6 << MS_Y3_SHIFT) |
109 (6 << MS_X4_SHIFT) |
110 (6 << MS_Y4_SHIFT) |
111 (6 << MS_X5_SHIFT) |
112 (6 << MS_Y5_SHIFT) |
113 (6 << MSBD1_SHIFT)));
114 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
115 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
116 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
117 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
118 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
119 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
120 radeon_ring_write(ring, PACKET0(0x20C8, 0));
121 radeon_ring_write(ring, 0);
122 radeon_ring_unlock_commit(rdev, ring);
123 }
124
125 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
126 {
127 unsigned i;
128 uint32_t tmp;
129
130 for (i = 0; i < rdev->usec_timeout; i++) {
131 /* read MC_STATUS */
132 tmp = RREG32_MC(MC_STATUS);
133 if (tmp & MC_STATUS_IDLE) {
134 return 0;
135 }
136 DRM_UDELAY(1);
137 }
138 return -1;
139 }
140
141 void rv515_vga_render_disable(struct radeon_device *rdev)
142 {
143 WREG32(R_000300_VGA_RENDER_CONTROL,
144 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
145 }
146
147 void rv515_gpu_init(struct radeon_device *rdev)
148 {
149 unsigned pipe_select_current, gb_pipe_select, tmp;
150
151 if (r100_gui_wait_for_idle(rdev)) {
152 printk(KERN_WARNING "Failed to wait GUI idle while "
153 "reseting GPU. Bad things might happen.\n");
154 }
155 rv515_vga_render_disable(rdev);
156 r420_pipes_init(rdev);
157 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
158 tmp = RREG32(R300_DST_PIPE_CONFIG);
159 pipe_select_current = (tmp >> 2) & 3;
160 tmp = (1 << pipe_select_current) |
161 (((gb_pipe_select >> 8) & 0xF) << 4);
162 WREG32_PLL(0x000D, tmp);
163 if (r100_gui_wait_for_idle(rdev)) {
164 printk(KERN_WARNING "Failed to wait GUI idle while "
165 "reseting GPU. Bad things might happen.\n");
166 }
167 if (rv515_mc_wait_for_idle(rdev)) {
168 printk(KERN_WARNING "Failed to wait MC idle while "
169 "programming pipes. Bad things might happen.\n");
170 }
171 }
172
173 static void rv515_vram_get_type(struct radeon_device *rdev)
174 {
175 uint32_t tmp;
176
177 rdev->mc.vram_width = 128;
178 rdev->mc.vram_is_ddr = true;
179 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
180 switch (tmp) {
181 case 0:
182 rdev->mc.vram_width = 64;
183 break;
184 case 1:
185 rdev->mc.vram_width = 128;
186 break;
187 default:
188 rdev->mc.vram_width = 128;
189 break;
190 }
191 }
192
193 void rv515_mc_init(struct radeon_device *rdev)
194 {
195
196 rv515_vram_get_type(rdev);
197 r100_vram_init_sizes(rdev);
198 radeon_vram_location(rdev, &rdev->mc, 0);
199 rdev->mc.gtt_base_align = 0;
200 if (!(rdev->flags & RADEON_IS_AGP))
201 radeon_gtt_location(rdev, &rdev->mc);
202 radeon_update_bandwidth_info(rdev);
203 }
204
205 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
206 {
207 uint32_t r;
208
209 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
210 r = RREG32(MC_IND_DATA);
211 WREG32(MC_IND_INDEX, 0);
212 return r;
213 }
214
215 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
216 {
217 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
218 WREG32(MC_IND_DATA, (v));
219 WREG32(MC_IND_INDEX, 0);
220 }
221
222 #if defined(CONFIG_DEBUG_FS)
223 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
224 {
225 struct drm_info_node *node = (struct drm_info_node *) m->private;
226 struct drm_device *dev = node->minor->dev;
227 struct radeon_device *rdev = dev->dev_private;
228 uint32_t tmp;
229
230 tmp = RREG32(GB_PIPE_SELECT);
231 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
232 tmp = RREG32(SU_REG_DEST);
233 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
234 tmp = RREG32(GB_TILE_CONFIG);
235 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
236 tmp = RREG32(DST_PIPE_CONFIG);
237 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
238 return 0;
239 }
240
241 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
242 {
243 struct drm_info_node *node = (struct drm_info_node *) m->private;
244 struct drm_device *dev = node->minor->dev;
245 struct radeon_device *rdev = dev->dev_private;
246 uint32_t tmp;
247
248 tmp = RREG32(0x2140);
249 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
250 radeon_asic_reset(rdev);
251 tmp = RREG32(0x425C);
252 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
253 return 0;
254 }
255
256 static struct drm_info_list rv515_pipes_info_list[] = {
257 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
258 };
259
260 static struct drm_info_list rv515_ga_info_list[] = {
261 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
262 };
263 #endif
264
265 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
266 {
267 #if defined(CONFIG_DEBUG_FS)
268 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
269 #else
270 return 0;
271 #endif
272 }
273
274 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
275 {
276 #if defined(CONFIG_DEBUG_FS)
277 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
278 #else
279 return 0;
280 #endif
281 }
282
283 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
284 {
285 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
286 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
287 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
288 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
289 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
290 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
291
292 /* Stop all video */
293 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
294 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
295 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
296 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
297 WREG32(R_006080_D1CRTC_CONTROL, 0);
298 WREG32(R_006880_D2CRTC_CONTROL, 0);
299 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
300 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
301 WREG32(R_000330_D1VGA_CONTROL, 0);
302 WREG32(R_000338_D2VGA_CONTROL, 0);
303 }
304
305 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
306 {
307 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
308 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
309 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
310 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
311 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
312 /* Unlock host access */
313 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
314 mdelay(1);
315 /* Restore video state */
316 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
317 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
318 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
319 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
320 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
321 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
322 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
323 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
324 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
325 }
326
327 void rv515_mc_program(struct radeon_device *rdev)
328 {
329 struct rv515_mc_save save;
330
331 /* Stops all mc clients */
332 rv515_mc_stop(rdev, &save);
333
334 /* Wait for mc idle */
335 if (rv515_mc_wait_for_idle(rdev))
336 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
337 /* Write VRAM size in case we are limiting it */
338 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
339 /* Program MC, should be a 32bits limited address space */
340 WREG32_MC(R_000001_MC_FB_LOCATION,
341 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
342 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
343 WREG32(R_000134_HDP_FB_LOCATION,
344 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
345 if (rdev->flags & RADEON_IS_AGP) {
346 WREG32_MC(R_000002_MC_AGP_LOCATION,
347 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
348 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
349 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
350 WREG32_MC(R_000004_MC_AGP_BASE_2,
351 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
352 } else {
353 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
354 WREG32_MC(R_000003_MC_AGP_BASE, 0);
355 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
356 }
357
358 rv515_mc_resume(rdev, &save);
359 }
360
361 void rv515_clock_startup(struct radeon_device *rdev)
362 {
363 if (radeon_dynclks != -1 && radeon_dynclks)
364 radeon_atom_set_clock_gating(rdev, 1);
365 /* We need to force on some of the block */
366 WREG32_PLL(R_00000F_CP_DYN_CNTL,
367 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
368 WREG32_PLL(R_000011_E2_DYN_CNTL,
369 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
370 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
371 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
372 }
373
374 static int rv515_startup(struct radeon_device *rdev)
375 {
376 int r;
377
378 rv515_mc_program(rdev);
379 /* Resume clock */
380 rv515_clock_startup(rdev);
381 /* Initialize GPU configuration (# pipes, ...) */
382 rv515_gpu_init(rdev);
383 /* Initialize GART (initialize after TTM so we can allocate
384 * memory through TTM but finalize after TTM) */
385 if (rdev->flags & RADEON_IS_PCIE) {
386 r = rv370_pcie_gart_enable(rdev);
387 if (r)
388 return r;
389 }
390
391 /* allocate wb buffer */
392 r = radeon_wb_init(rdev);
393 if (r)
394 return r;
395
396 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
397 if (r) {
398 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
399 return r;
400 }
401
402 /* Enable IRQ */
403 rs600_irq_set(rdev);
404 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
405 /* 1M ring buffer */
406 r = r100_cp_init(rdev, 1024 * 1024);
407 if (r) {
408 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
409 return r;
410 }
411
412 r = radeon_ib_pool_start(rdev);
413 if (r)
414 return r;
415
416 r = r100_ib_test(rdev);
417 if (r) {
418 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
419 rdev->accel_working = false;
420 return r;
421 }
422 return 0;
423 }
424
425 int rv515_resume(struct radeon_device *rdev)
426 {
427 int r;
428
429 /* Make sur GART are not working */
430 if (rdev->flags & RADEON_IS_PCIE)
431 rv370_pcie_gart_disable(rdev);
432 /* Resume clock before doing reset */
433 rv515_clock_startup(rdev);
434 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
435 if (radeon_asic_reset(rdev)) {
436 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
437 RREG32(R_000E40_RBBM_STATUS),
438 RREG32(R_0007C0_CP_STAT));
439 }
440 /* post */
441 atom_asic_init(rdev->mode_info.atom_context);
442 /* Resume clock after posting */
443 rv515_clock_startup(rdev);
444 /* Initialize surface registers */
445 radeon_surface_init(rdev);
446
447 rdev->accel_working = true;
448 r = rv515_startup(rdev);
449 if (r) {
450 rdev->accel_working = false;
451 }
452 return r;
453 }
454
455 int rv515_suspend(struct radeon_device *rdev)
456 {
457 r100_cp_disable(rdev);
458 radeon_wb_disable(rdev);
459 rs600_irq_disable(rdev);
460 if (rdev->flags & RADEON_IS_PCIE)
461 rv370_pcie_gart_disable(rdev);
462 return 0;
463 }
464
465 void rv515_set_safe_registers(struct radeon_device *rdev)
466 {
467 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
468 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
469 }
470
471 void rv515_fini(struct radeon_device *rdev)
472 {
473 r100_cp_fini(rdev);
474 radeon_wb_fini(rdev);
475 r100_ib_fini(rdev);
476 radeon_gem_fini(rdev);
477 rv370_pcie_gart_fini(rdev);
478 radeon_agp_fini(rdev);
479 radeon_irq_kms_fini(rdev);
480 radeon_fence_driver_fini(rdev);
481 radeon_bo_fini(rdev);
482 radeon_atombios_fini(rdev);
483 kfree(rdev->bios);
484 rdev->bios = NULL;
485 }
486
487 int rv515_init(struct radeon_device *rdev)
488 {
489 int r;
490
491 /* Initialize scratch registers */
492 radeon_scratch_init(rdev);
493 /* Initialize surface registers */
494 radeon_surface_init(rdev);
495 /* TODO: disable VGA need to use VGA request */
496 /* restore some register to sane defaults */
497 r100_restore_sanity(rdev);
498 /* BIOS*/
499 if (!radeon_get_bios(rdev)) {
500 if (ASIC_IS_AVIVO(rdev))
501 return -EINVAL;
502 }
503 if (rdev->is_atom_bios) {
504 r = radeon_atombios_init(rdev);
505 if (r)
506 return r;
507 } else {
508 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
509 return -EINVAL;
510 }
511 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
512 if (radeon_asic_reset(rdev)) {
513 dev_warn(rdev->dev,
514 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
515 RREG32(R_000E40_RBBM_STATUS),
516 RREG32(R_0007C0_CP_STAT));
517 }
518 /* check if cards are posted or not */
519 if (radeon_boot_test_post_card(rdev) == false)
520 return -EINVAL;
521 /* Initialize clocks */
522 radeon_get_clock_info(rdev->ddev);
523 /* initialize AGP */
524 if (rdev->flags & RADEON_IS_AGP) {
525 r = radeon_agp_init(rdev);
526 if (r) {
527 radeon_agp_disable(rdev);
528 }
529 }
530 /* initialize memory controller */
531 rv515_mc_init(rdev);
532 rv515_debugfs(rdev);
533 /* Fence driver */
534 r = radeon_fence_driver_init(rdev);
535 if (r)
536 return r;
537 r = radeon_irq_kms_init(rdev);
538 if (r)
539 return r;
540 /* Memory manager */
541 r = radeon_bo_init(rdev);
542 if (r)
543 return r;
544 r = rv370_pcie_gart_init(rdev);
545 if (r)
546 return r;
547 rv515_set_safe_registers(rdev);
548
549 r = radeon_ib_pool_init(rdev);
550 rdev->accel_working = true;
551 if (r) {
552 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
553 rdev->accel_working = false;
554 }
555
556 r = rv515_startup(rdev);
557 if (r) {
558 /* Somethings want wront with the accel init stop accel */
559 dev_err(rdev->dev, "Disabling GPU acceleration\n");
560 r100_cp_fini(rdev);
561 radeon_wb_fini(rdev);
562 r100_ib_fini(rdev);
563 radeon_irq_kms_fini(rdev);
564 rv370_pcie_gart_fini(rdev);
565 radeon_agp_fini(rdev);
566 rdev->accel_working = false;
567 }
568 return 0;
569 }
570
571 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
572 {
573 int index_reg = 0x6578 + crtc->crtc_offset;
574 int data_reg = 0x657c + crtc->crtc_offset;
575
576 WREG32(0x659C + crtc->crtc_offset, 0x0);
577 WREG32(0x6594 + crtc->crtc_offset, 0x705);
578 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
579 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
580 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
581 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
582 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
583 WREG32(index_reg, 0x0);
584 WREG32(data_reg, 0x841880A8);
585 WREG32(index_reg, 0x1);
586 WREG32(data_reg, 0x84208680);
587 WREG32(index_reg, 0x2);
588 WREG32(data_reg, 0xBFF880B0);
589 WREG32(index_reg, 0x100);
590 WREG32(data_reg, 0x83D88088);
591 WREG32(index_reg, 0x101);
592 WREG32(data_reg, 0x84608680);
593 WREG32(index_reg, 0x102);
594 WREG32(data_reg, 0xBFF080D0);
595 WREG32(index_reg, 0x200);
596 WREG32(data_reg, 0x83988068);
597 WREG32(index_reg, 0x201);
598 WREG32(data_reg, 0x84A08680);
599 WREG32(index_reg, 0x202);
600 WREG32(data_reg, 0xBFF080F8);
601 WREG32(index_reg, 0x300);
602 WREG32(data_reg, 0x83588058);
603 WREG32(index_reg, 0x301);
604 WREG32(data_reg, 0x84E08660);
605 WREG32(index_reg, 0x302);
606 WREG32(data_reg, 0xBFF88120);
607 WREG32(index_reg, 0x400);
608 WREG32(data_reg, 0x83188040);
609 WREG32(index_reg, 0x401);
610 WREG32(data_reg, 0x85008660);
611 WREG32(index_reg, 0x402);
612 WREG32(data_reg, 0xBFF88150);
613 WREG32(index_reg, 0x500);
614 WREG32(data_reg, 0x82D88030);
615 WREG32(index_reg, 0x501);
616 WREG32(data_reg, 0x85408640);
617 WREG32(index_reg, 0x502);
618 WREG32(data_reg, 0xBFF88180);
619 WREG32(index_reg, 0x600);
620 WREG32(data_reg, 0x82A08018);
621 WREG32(index_reg, 0x601);
622 WREG32(data_reg, 0x85808620);
623 WREG32(index_reg, 0x602);
624 WREG32(data_reg, 0xBFF081B8);
625 WREG32(index_reg, 0x700);
626 WREG32(data_reg, 0x82608010);
627 WREG32(index_reg, 0x701);
628 WREG32(data_reg, 0x85A08600);
629 WREG32(index_reg, 0x702);
630 WREG32(data_reg, 0x800081F0);
631 WREG32(index_reg, 0x800);
632 WREG32(data_reg, 0x8228BFF8);
633 WREG32(index_reg, 0x801);
634 WREG32(data_reg, 0x85E085E0);
635 WREG32(index_reg, 0x802);
636 WREG32(data_reg, 0xBFF88228);
637 WREG32(index_reg, 0x10000);
638 WREG32(data_reg, 0x82A8BF00);
639 WREG32(index_reg, 0x10001);
640 WREG32(data_reg, 0x82A08CC0);
641 WREG32(index_reg, 0x10002);
642 WREG32(data_reg, 0x8008BEF8);
643 WREG32(index_reg, 0x10100);
644 WREG32(data_reg, 0x81F0BF28);
645 WREG32(index_reg, 0x10101);
646 WREG32(data_reg, 0x83608CA0);
647 WREG32(index_reg, 0x10102);
648 WREG32(data_reg, 0x8018BED0);
649 WREG32(index_reg, 0x10200);
650 WREG32(data_reg, 0x8148BF38);
651 WREG32(index_reg, 0x10201);
652 WREG32(data_reg, 0x84408C80);
653 WREG32(index_reg, 0x10202);
654 WREG32(data_reg, 0x8008BEB8);
655 WREG32(index_reg, 0x10300);
656 WREG32(data_reg, 0x80B0BF78);
657 WREG32(index_reg, 0x10301);
658 WREG32(data_reg, 0x85008C20);
659 WREG32(index_reg, 0x10302);
660 WREG32(data_reg, 0x8020BEA0);
661 WREG32(index_reg, 0x10400);
662 WREG32(data_reg, 0x8028BF90);
663 WREG32(index_reg, 0x10401);
664 WREG32(data_reg, 0x85E08BC0);
665 WREG32(index_reg, 0x10402);
666 WREG32(data_reg, 0x8018BE90);
667 WREG32(index_reg, 0x10500);
668 WREG32(data_reg, 0xBFB8BFB0);
669 WREG32(index_reg, 0x10501);
670 WREG32(data_reg, 0x86C08B40);
671 WREG32(index_reg, 0x10502);
672 WREG32(data_reg, 0x8010BE90);
673 WREG32(index_reg, 0x10600);
674 WREG32(data_reg, 0xBF58BFC8);
675 WREG32(index_reg, 0x10601);
676 WREG32(data_reg, 0x87A08AA0);
677 WREG32(index_reg, 0x10602);
678 WREG32(data_reg, 0x8010BE98);
679 WREG32(index_reg, 0x10700);
680 WREG32(data_reg, 0xBF10BFF0);
681 WREG32(index_reg, 0x10701);
682 WREG32(data_reg, 0x886089E0);
683 WREG32(index_reg, 0x10702);
684 WREG32(data_reg, 0x8018BEB0);
685 WREG32(index_reg, 0x10800);
686 WREG32(data_reg, 0xBED8BFE8);
687 WREG32(index_reg, 0x10801);
688 WREG32(data_reg, 0x89408940);
689 WREG32(index_reg, 0x10802);
690 WREG32(data_reg, 0xBFE8BED8);
691 WREG32(index_reg, 0x20000);
692 WREG32(data_reg, 0x80008000);
693 WREG32(index_reg, 0x20001);
694 WREG32(data_reg, 0x90008000);
695 WREG32(index_reg, 0x20002);
696 WREG32(data_reg, 0x80008000);
697 WREG32(index_reg, 0x20003);
698 WREG32(data_reg, 0x80008000);
699 WREG32(index_reg, 0x20100);
700 WREG32(data_reg, 0x80108000);
701 WREG32(index_reg, 0x20101);
702 WREG32(data_reg, 0x8FE0BF70);
703 WREG32(index_reg, 0x20102);
704 WREG32(data_reg, 0xBFE880C0);
705 WREG32(index_reg, 0x20103);
706 WREG32(data_reg, 0x80008000);
707 WREG32(index_reg, 0x20200);
708 WREG32(data_reg, 0x8018BFF8);
709 WREG32(index_reg, 0x20201);
710 WREG32(data_reg, 0x8F80BF08);
711 WREG32(index_reg, 0x20202);
712 WREG32(data_reg, 0xBFD081A0);
713 WREG32(index_reg, 0x20203);
714 WREG32(data_reg, 0xBFF88000);
715 WREG32(index_reg, 0x20300);
716 WREG32(data_reg, 0x80188000);
717 WREG32(index_reg, 0x20301);
718 WREG32(data_reg, 0x8EE0BEC0);
719 WREG32(index_reg, 0x20302);
720 WREG32(data_reg, 0xBFB082A0);
721 WREG32(index_reg, 0x20303);
722 WREG32(data_reg, 0x80008000);
723 WREG32(index_reg, 0x20400);
724 WREG32(data_reg, 0x80188000);
725 WREG32(index_reg, 0x20401);
726 WREG32(data_reg, 0x8E00BEA0);
727 WREG32(index_reg, 0x20402);
728 WREG32(data_reg, 0xBF8883C0);
729 WREG32(index_reg, 0x20403);
730 WREG32(data_reg, 0x80008000);
731 WREG32(index_reg, 0x20500);
732 WREG32(data_reg, 0x80188000);
733 WREG32(index_reg, 0x20501);
734 WREG32(data_reg, 0x8D00BE90);
735 WREG32(index_reg, 0x20502);
736 WREG32(data_reg, 0xBF588500);
737 WREG32(index_reg, 0x20503);
738 WREG32(data_reg, 0x80008008);
739 WREG32(index_reg, 0x20600);
740 WREG32(data_reg, 0x80188000);
741 WREG32(index_reg, 0x20601);
742 WREG32(data_reg, 0x8BC0BE98);
743 WREG32(index_reg, 0x20602);
744 WREG32(data_reg, 0xBF308660);
745 WREG32(index_reg, 0x20603);
746 WREG32(data_reg, 0x80008008);
747 WREG32(index_reg, 0x20700);
748 WREG32(data_reg, 0x80108000);
749 WREG32(index_reg, 0x20701);
750 WREG32(data_reg, 0x8A80BEB0);
751 WREG32(index_reg, 0x20702);
752 WREG32(data_reg, 0xBF0087C0);
753 WREG32(index_reg, 0x20703);
754 WREG32(data_reg, 0x80008008);
755 WREG32(index_reg, 0x20800);
756 WREG32(data_reg, 0x80108000);
757 WREG32(index_reg, 0x20801);
758 WREG32(data_reg, 0x8920BED0);
759 WREG32(index_reg, 0x20802);
760 WREG32(data_reg, 0xBED08920);
761 WREG32(index_reg, 0x20803);
762 WREG32(data_reg, 0x80008010);
763 WREG32(index_reg, 0x30000);
764 WREG32(data_reg, 0x90008000);
765 WREG32(index_reg, 0x30001);
766 WREG32(data_reg, 0x80008000);
767 WREG32(index_reg, 0x30100);
768 WREG32(data_reg, 0x8FE0BF90);
769 WREG32(index_reg, 0x30101);
770 WREG32(data_reg, 0xBFF880A0);
771 WREG32(index_reg, 0x30200);
772 WREG32(data_reg, 0x8F60BF40);
773 WREG32(index_reg, 0x30201);
774 WREG32(data_reg, 0xBFE88180);
775 WREG32(index_reg, 0x30300);
776 WREG32(data_reg, 0x8EC0BF00);
777 WREG32(index_reg, 0x30301);
778 WREG32(data_reg, 0xBFC88280);
779 WREG32(index_reg, 0x30400);
780 WREG32(data_reg, 0x8DE0BEE0);
781 WREG32(index_reg, 0x30401);
782 WREG32(data_reg, 0xBFA083A0);
783 WREG32(index_reg, 0x30500);
784 WREG32(data_reg, 0x8CE0BED0);
785 WREG32(index_reg, 0x30501);
786 WREG32(data_reg, 0xBF7884E0);
787 WREG32(index_reg, 0x30600);
788 WREG32(data_reg, 0x8BA0BED8);
789 WREG32(index_reg, 0x30601);
790 WREG32(data_reg, 0xBF508640);
791 WREG32(index_reg, 0x30700);
792 WREG32(data_reg, 0x8A60BEE8);
793 WREG32(index_reg, 0x30701);
794 WREG32(data_reg, 0xBF2087A0);
795 WREG32(index_reg, 0x30800);
796 WREG32(data_reg, 0x8900BF00);
797 WREG32(index_reg, 0x30801);
798 WREG32(data_reg, 0xBF008900);
799 }
800
801 struct rv515_watermark {
802 u32 lb_request_fifo_depth;
803 fixed20_12 num_line_pair;
804 fixed20_12 estimated_width;
805 fixed20_12 worst_case_latency;
806 fixed20_12 consumption_rate;
807 fixed20_12 active_time;
808 fixed20_12 dbpp;
809 fixed20_12 priority_mark_max;
810 fixed20_12 priority_mark;
811 fixed20_12 sclk;
812 };
813
814 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
815 struct radeon_crtc *crtc,
816 struct rv515_watermark *wm)
817 {
818 struct drm_display_mode *mode = &crtc->base.mode;
819 fixed20_12 a, b, c;
820 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
821 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
822
823 if (!crtc->base.enabled) {
824 /* FIXME: wouldn't it better to set priority mark to maximum */
825 wm->lb_request_fifo_depth = 4;
826 return;
827 }
828
829 if (crtc->vsc.full > dfixed_const(2))
830 wm->num_line_pair.full = dfixed_const(2);
831 else
832 wm->num_line_pair.full = dfixed_const(1);
833
834 b.full = dfixed_const(mode->crtc_hdisplay);
835 c.full = dfixed_const(256);
836 a.full = dfixed_div(b, c);
837 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
838 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
839 if (a.full < dfixed_const(4)) {
840 wm->lb_request_fifo_depth = 4;
841 } else {
842 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
843 }
844
845 /* Determine consumption rate
846 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
847 * vtaps = number of vertical taps,
848 * vsc = vertical scaling ratio, defined as source/destination
849 * hsc = horizontal scaling ration, defined as source/destination
850 */
851 a.full = dfixed_const(mode->clock);
852 b.full = dfixed_const(1000);
853 a.full = dfixed_div(a, b);
854 pclk.full = dfixed_div(b, a);
855 if (crtc->rmx_type != RMX_OFF) {
856 b.full = dfixed_const(2);
857 if (crtc->vsc.full > b.full)
858 b.full = crtc->vsc.full;
859 b.full = dfixed_mul(b, crtc->hsc);
860 c.full = dfixed_const(2);
861 b.full = dfixed_div(b, c);
862 consumption_time.full = dfixed_div(pclk, b);
863 } else {
864 consumption_time.full = pclk.full;
865 }
866 a.full = dfixed_const(1);
867 wm->consumption_rate.full = dfixed_div(a, consumption_time);
868
869
870 /* Determine line time
871 * LineTime = total time for one line of displayhtotal
872 * LineTime = total number of horizontal pixels
873 * pclk = pixel clock period(ns)
874 */
875 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
876 line_time.full = dfixed_mul(a, pclk);
877
878 /* Determine active time
879 * ActiveTime = time of active region of display within one line,
880 * hactive = total number of horizontal active pixels
881 * htotal = total number of horizontal pixels
882 */
883 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
884 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
885 wm->active_time.full = dfixed_mul(line_time, b);
886 wm->active_time.full = dfixed_div(wm->active_time, a);
887
888 /* Determine chunk time
889 * ChunkTime = the time it takes the DCP to send one chunk of data
890 * to the LB which consists of pipeline delay and inter chunk gap
891 * sclk = system clock(Mhz)
892 */
893 a.full = dfixed_const(600 * 1000);
894 chunk_time.full = dfixed_div(a, rdev->pm.sclk);
895 read_delay_latency.full = dfixed_const(1000);
896
897 /* Determine the worst case latency
898 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
899 * WorstCaseLatency = worst case time from urgent to when the MC starts
900 * to return data
901 * READ_DELAY_IDLE_MAX = constant of 1us
902 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
903 * which consists of pipeline delay and inter chunk gap
904 */
905 if (dfixed_trunc(wm->num_line_pair) > 1) {
906 a.full = dfixed_const(3);
907 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
908 wm->worst_case_latency.full += read_delay_latency.full;
909 } else {
910 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
911 }
912
913 /* Determine the tolerable latency
914 * TolerableLatency = Any given request has only 1 line time
915 * for the data to be returned
916 * LBRequestFifoDepth = Number of chunk requests the LB can
917 * put into the request FIFO for a display
918 * LineTime = total time for one line of display
919 * ChunkTime = the time it takes the DCP to send one chunk
920 * of data to the LB which consists of
921 * pipeline delay and inter chunk gap
922 */
923 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
924 tolerable_latency.full = line_time.full;
925 } else {
926 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
927 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
928 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
929 tolerable_latency.full = line_time.full - tolerable_latency.full;
930 }
931 /* We assume worst case 32bits (4 bytes) */
932 wm->dbpp.full = dfixed_const(2 * 16);
933
934 /* Determine the maximum priority mark
935 * width = viewport width in pixels
936 */
937 a.full = dfixed_const(16);
938 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
939 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
940 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
941
942 /* Determine estimated width */
943 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
944 estimated_width.full = dfixed_div(estimated_width, consumption_time);
945 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
946 wm->priority_mark.full = wm->priority_mark_max.full;
947 } else {
948 a.full = dfixed_const(16);
949 wm->priority_mark.full = dfixed_div(estimated_width, a);
950 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
951 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
952 }
953 }
954
955 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
956 {
957 struct drm_display_mode *mode0 = NULL;
958 struct drm_display_mode *mode1 = NULL;
959 struct rv515_watermark wm0;
960 struct rv515_watermark wm1;
961 u32 tmp;
962 u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
963 u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
964 fixed20_12 priority_mark02, priority_mark12, fill_rate;
965 fixed20_12 a, b;
966
967 if (rdev->mode_info.crtcs[0]->base.enabled)
968 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
969 if (rdev->mode_info.crtcs[1]->base.enabled)
970 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
971 rs690_line_buffer_adjust(rdev, mode0, mode1);
972
973 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
974 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
975
976 tmp = wm0.lb_request_fifo_depth;
977 tmp |= wm1.lb_request_fifo_depth << 16;
978 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
979
980 if (mode0 && mode1) {
981 if (dfixed_trunc(wm0.dbpp) > 64)
982 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
983 else
984 a.full = wm0.num_line_pair.full;
985 if (dfixed_trunc(wm1.dbpp) > 64)
986 b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
987 else
988 b.full = wm1.num_line_pair.full;
989 a.full += b.full;
990 fill_rate.full = dfixed_div(wm0.sclk, a);
991 if (wm0.consumption_rate.full > fill_rate.full) {
992 b.full = wm0.consumption_rate.full - fill_rate.full;
993 b.full = dfixed_mul(b, wm0.active_time);
994 a.full = dfixed_const(16);
995 b.full = dfixed_div(b, a);
996 a.full = dfixed_mul(wm0.worst_case_latency,
997 wm0.consumption_rate);
998 priority_mark02.full = a.full + b.full;
999 } else {
1000 a.full = dfixed_mul(wm0.worst_case_latency,
1001 wm0.consumption_rate);
1002 b.full = dfixed_const(16 * 1000);
1003 priority_mark02.full = dfixed_div(a, b);
1004 }
1005 if (wm1.consumption_rate.full > fill_rate.full) {
1006 b.full = wm1.consumption_rate.full - fill_rate.full;
1007 b.full = dfixed_mul(b, wm1.active_time);
1008 a.full = dfixed_const(16);
1009 b.full = dfixed_div(b, a);
1010 a.full = dfixed_mul(wm1.worst_case_latency,
1011 wm1.consumption_rate);
1012 priority_mark12.full = a.full + b.full;
1013 } else {
1014 a.full = dfixed_mul(wm1.worst_case_latency,
1015 wm1.consumption_rate);
1016 b.full = dfixed_const(16 * 1000);
1017 priority_mark12.full = dfixed_div(a, b);
1018 }
1019 if (wm0.priority_mark.full > priority_mark02.full)
1020 priority_mark02.full = wm0.priority_mark.full;
1021 if (dfixed_trunc(priority_mark02) < 0)
1022 priority_mark02.full = 0;
1023 if (wm0.priority_mark_max.full > priority_mark02.full)
1024 priority_mark02.full = wm0.priority_mark_max.full;
1025 if (wm1.priority_mark.full > priority_mark12.full)
1026 priority_mark12.full = wm1.priority_mark.full;
1027 if (dfixed_trunc(priority_mark12) < 0)
1028 priority_mark12.full = 0;
1029 if (wm1.priority_mark_max.full > priority_mark12.full)
1030 priority_mark12.full = wm1.priority_mark_max.full;
1031 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1032 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1033 if (rdev->disp_priority == 2) {
1034 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1035 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1036 }
1037 } else if (mode0) {
1038 if (dfixed_trunc(wm0.dbpp) > 64)
1039 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1040 else
1041 a.full = wm0.num_line_pair.full;
1042 fill_rate.full = dfixed_div(wm0.sclk, a);
1043 if (wm0.consumption_rate.full > fill_rate.full) {
1044 b.full = wm0.consumption_rate.full - fill_rate.full;
1045 b.full = dfixed_mul(b, wm0.active_time);
1046 a.full = dfixed_const(16);
1047 b.full = dfixed_div(b, a);
1048 a.full = dfixed_mul(wm0.worst_case_latency,
1049 wm0.consumption_rate);
1050 priority_mark02.full = a.full + b.full;
1051 } else {
1052 a.full = dfixed_mul(wm0.worst_case_latency,
1053 wm0.consumption_rate);
1054 b.full = dfixed_const(16);
1055 priority_mark02.full = dfixed_div(a, b);
1056 }
1057 if (wm0.priority_mark.full > priority_mark02.full)
1058 priority_mark02.full = wm0.priority_mark.full;
1059 if (dfixed_trunc(priority_mark02) < 0)
1060 priority_mark02.full = 0;
1061 if (wm0.priority_mark_max.full > priority_mark02.full)
1062 priority_mark02.full = wm0.priority_mark_max.full;
1063 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1064 if (rdev->disp_priority == 2)
1065 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1066 } else if (mode1) {
1067 if (dfixed_trunc(wm1.dbpp) > 64)
1068 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1069 else
1070 a.full = wm1.num_line_pair.full;
1071 fill_rate.full = dfixed_div(wm1.sclk, a);
1072 if (wm1.consumption_rate.full > fill_rate.full) {
1073 b.full = wm1.consumption_rate.full - fill_rate.full;
1074 b.full = dfixed_mul(b, wm1.active_time);
1075 a.full = dfixed_const(16);
1076 b.full = dfixed_div(b, a);
1077 a.full = dfixed_mul(wm1.worst_case_latency,
1078 wm1.consumption_rate);
1079 priority_mark12.full = a.full + b.full;
1080 } else {
1081 a.full = dfixed_mul(wm1.worst_case_latency,
1082 wm1.consumption_rate);
1083 b.full = dfixed_const(16 * 1000);
1084 priority_mark12.full = dfixed_div(a, b);
1085 }
1086 if (wm1.priority_mark.full > priority_mark12.full)
1087 priority_mark12.full = wm1.priority_mark.full;
1088 if (dfixed_trunc(priority_mark12) < 0)
1089 priority_mark12.full = 0;
1090 if (wm1.priority_mark_max.full > priority_mark12.full)
1091 priority_mark12.full = wm1.priority_mark_max.full;
1092 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1093 if (rdev->disp_priority == 2)
1094 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1095 }
1096
1097 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1098 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1099 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1100 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1101 }
1102
1103 void rv515_bandwidth_update(struct radeon_device *rdev)
1104 {
1105 uint32_t tmp;
1106 struct drm_display_mode *mode0 = NULL;
1107 struct drm_display_mode *mode1 = NULL;
1108
1109 radeon_update_display_priority(rdev);
1110
1111 if (rdev->mode_info.crtcs[0]->base.enabled)
1112 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1113 if (rdev->mode_info.crtcs[1]->base.enabled)
1114 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1115 /*
1116 * Set display0/1 priority up in the memory controller for
1117 * modes if the user specifies HIGH for displaypriority
1118 * option.
1119 */
1120 if ((rdev->disp_priority == 2) &&
1121 (rdev->family == CHIP_RV515)) {
1122 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1123 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1124 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1125 if (mode1)
1126 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1127 if (mode0)
1128 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1129 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1130 }
1131 rv515_bandwidth_avivo_update(rdev);
1132 }