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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / infiniband / hw / cxgb4 / qp.c
blob5f940aeaab1e0086140df49d03a94b4c965b23f0
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34
35 #include "iw_cxgb4.h"
36
37 static int ocqp_support = 1;
38 module_param(ocqp_support, int, 0644);
39 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
40
41 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
42 {
43 unsigned long flag;
44 spin_lock_irqsave(&qhp->lock, flag);
45 qhp->attr.state = state;
46 spin_unlock_irqrestore(&qhp->lock, flag);
47 }
48
49 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
50 {
51 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
52 }
53
54 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
55 {
56 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
57 pci_unmap_addr(sq, mapping));
58 }
59
60 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
61 {
62 if (t4_sq_onchip(sq))
63 dealloc_oc_sq(rdev, sq);
64 else
65 dealloc_host_sq(rdev, sq);
66 }
67
68 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
69 {
70 if (!ocqp_support || !t4_ocqp_supported())
71 return -ENOSYS;
72 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
73 if (!sq->dma_addr)
74 return -ENOMEM;
75 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
76 rdev->lldi.vr->ocq.start;
77 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
78 rdev->lldi.vr->ocq.start);
79 sq->flags |= T4_SQ_ONCHIP;
80 return 0;
81 }
82
83 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
84 {
85 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
86 &(sq->dma_addr), GFP_KERNEL);
87 if (!sq->queue)
88 return -ENOMEM;
89 sq->phys_addr = virt_to_phys(sq->queue);
90 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
91 return 0;
92 }
93
94 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
95 struct c4iw_dev_ucontext *uctx)
96 {
97 /*
98 * uP clears EQ contexts when the connection exits rdma mode,
99 * so no need to post a RESET WR for these EQs.
100 */
101 dma_free_coherent(&(rdev->lldi.pdev->dev),
102 wq->rq.memsize, wq->rq.queue,
103 dma_unmap_addr(&wq->rq, mapping));
104 dealloc_sq(rdev, &wq->sq);
105 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
106 kfree(wq->rq.sw_rq);
107 kfree(wq->sq.sw_sq);
108 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
109 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
110 return 0;
111 }
112
113 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
114 struct t4_cq *rcq, struct t4_cq *scq,
115 struct c4iw_dev_ucontext *uctx)
116 {
117 int user = (uctx != &rdev->uctx);
118 struct fw_ri_res_wr *res_wr;
119 struct fw_ri_res *res;
120 int wr_len;
121 struct c4iw_wr_wait wr_wait;
122 struct sk_buff *skb;
123 int ret;
124 int eqsize;
125
126 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
127 if (!wq->sq.qid)
128 return -ENOMEM;
129
130 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
131 if (!wq->rq.qid)
132 goto err1;
133
134 if (!user) {
135 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
136 GFP_KERNEL);
137 if (!wq->sq.sw_sq)
138 goto err2;
139
140 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
141 GFP_KERNEL);
142 if (!wq->rq.sw_rq)
143 goto err3;
144 }
145
146 /*
147 * RQT must be a power of 2.
148 */
149 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
150 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
151 if (!wq->rq.rqt_hwaddr)
152 goto err4;
153
154 if (user) {
155 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
156 goto err5;
157 } else
158 if (alloc_host_sq(rdev, &wq->sq))
159 goto err5;
160 memset(wq->sq.queue, 0, wq->sq.memsize);
161 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
162
163 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
164 wq->rq.memsize, &(wq->rq.dma_addr),
165 GFP_KERNEL);
166 if (!wq->rq.queue)
167 goto err6;
168 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
169 __func__, wq->sq.queue,
170 (unsigned long long)virt_to_phys(wq->sq.queue),
171 wq->rq.queue,
172 (unsigned long long)virt_to_phys(wq->rq.queue));
173 memset(wq->rq.queue, 0, wq->rq.memsize);
174 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
175
176 wq->db = rdev->lldi.db_reg;
177 wq->gts = rdev->lldi.gts_reg;
178 if (user) {
179 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
180 (wq->sq.qid << rdev->qpshift);
181 wq->sq.udb &= PAGE_MASK;
182 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
183 (wq->rq.qid << rdev->qpshift);
184 wq->rq.udb &= PAGE_MASK;
185 }
186 wq->rdev = rdev;
187 wq->rq.msn = 1;
188
189 /* build fw_ri_res_wr */
190 wr_len = sizeof *res_wr + 2 * sizeof *res;
191
192 skb = alloc_skb(wr_len, GFP_KERNEL);
193 if (!skb) {
194 ret = -ENOMEM;
195 goto err7;
196 }
197 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
198
199 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
200 memset(res_wr, 0, wr_len);
201 res_wr->op_nres = cpu_to_be32(
202 FW_WR_OP(FW_RI_RES_WR) |
203 V_FW_RI_RES_WR_NRES(2) |
204 FW_WR_COMPL(1));
205 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
206 res_wr->cookie = (unsigned long) &wr_wait;
207 res = res_wr->res;
208 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
209 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
210
211 /*
212 * eqsize is the number of 64B entries plus the status page size.
213 */
214 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
215
216 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
217 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
218 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
219 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
220 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
221 V_FW_RI_RES_WR_IQID(scq->cqid));
222 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
223 V_FW_RI_RES_WR_DCAEN(0) |
224 V_FW_RI_RES_WR_DCACPU(0) |
225 V_FW_RI_RES_WR_FBMIN(2) |
226 V_FW_RI_RES_WR_FBMAX(2) |
227 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
228 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
229 V_FW_RI_RES_WR_EQSIZE(eqsize));
230 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
231 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
232 res++;
233 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
234 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
235
236 /*
237 * eqsize is the number of 64B entries plus the status page size.
238 */
239 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
240 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
241 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
242 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
243 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
244 V_FW_RI_RES_WR_IQID(rcq->cqid));
245 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
246 V_FW_RI_RES_WR_DCAEN(0) |
247 V_FW_RI_RES_WR_DCACPU(0) |
248 V_FW_RI_RES_WR_FBMIN(2) |
249 V_FW_RI_RES_WR_FBMAX(2) |
250 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
251 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
252 V_FW_RI_RES_WR_EQSIZE(eqsize));
253 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
254 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
255
256 c4iw_init_wr_wait(&wr_wait);
257
258 ret = c4iw_ofld_send(rdev, skb);
259 if (ret)
260 goto err7;
261 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
262 if (ret)
263 goto err7;
264
265 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
266 __func__, wq->sq.qid, wq->rq.qid, wq->db,
267 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
268
269 return 0;
270 err7:
271 dma_free_coherent(&(rdev->lldi.pdev->dev),
272 wq->rq.memsize, wq->rq.queue,
273 dma_unmap_addr(&wq->rq, mapping));
274 err6:
275 dealloc_sq(rdev, &wq->sq);
276 err5:
277 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
278 err4:
279 kfree(wq->rq.sw_rq);
280 err3:
281 kfree(wq->sq.sw_sq);
282 err2:
283 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
284 err1:
285 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
286 return -ENOMEM;
287 }
288
289 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
290 struct ib_send_wr *wr, int max, u32 *plenp)
291 {
292 u8 *dstp, *srcp;
293 u32 plen = 0;
294 int i;
295 int rem, len;
296
297 dstp = (u8 *)immdp->data;
298 for (i = 0; i < wr->num_sge; i++) {
299 if ((plen + wr->sg_list[i].length) > max)
300 return -EMSGSIZE;
301 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
302 plen += wr->sg_list[i].length;
303 rem = wr->sg_list[i].length;
304 while (rem) {
305 if (dstp == (u8 *)&sq->queue[sq->size])
306 dstp = (u8 *)sq->queue;
307 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
308 len = rem;
309 else
310 len = (u8 *)&sq->queue[sq->size] - dstp;
311 memcpy(dstp, srcp, len);
312 dstp += len;
313 srcp += len;
314 rem -= len;
315 }
316 }
317 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
318 if (len)
319 memset(dstp, 0, len);
320 immdp->op = FW_RI_DATA_IMMD;
321 immdp->r1 = 0;
322 immdp->r2 = 0;
323 immdp->immdlen = cpu_to_be32(plen);
324 *plenp = plen;
325 return 0;
326 }
327
328 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
329 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
330 int num_sge, u32 *plenp)
331
332 {
333 int i;
334 u32 plen = 0;
335 __be64 *flitp = (__be64 *)isglp->sge;
336
337 for (i = 0; i < num_sge; i++) {
338 if ((plen + sg_list[i].length) < plen)
339 return -EMSGSIZE;
340 plen += sg_list[i].length;
341 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
342 sg_list[i].length);
343 if (++flitp == queue_end)
344 flitp = queue_start;
345 *flitp = cpu_to_be64(sg_list[i].addr);
346 if (++flitp == queue_end)
347 flitp = queue_start;
348 }
349 *flitp = (__force __be64)0;
350 isglp->op = FW_RI_DATA_ISGL;
351 isglp->r1 = 0;
352 isglp->nsge = cpu_to_be16(num_sge);
353 isglp->r2 = 0;
354 if (plenp)
355 *plenp = plen;
356 return 0;
357 }
358
359 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
360 struct ib_send_wr *wr, u8 *len16)
361 {
362 u32 plen;
363 int size;
364 int ret;
365
366 if (wr->num_sge > T4_MAX_SEND_SGE)
367 return -EINVAL;
368 switch (wr->opcode) {
369 case IB_WR_SEND:
370 if (wr->send_flags & IB_SEND_SOLICITED)
371 wqe->send.sendop_pkd = cpu_to_be32(
372 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
373 else
374 wqe->send.sendop_pkd = cpu_to_be32(
375 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
376 wqe->send.stag_inv = 0;
377 break;
378 case IB_WR_SEND_WITH_INV:
379 if (wr->send_flags & IB_SEND_SOLICITED)
380 wqe->send.sendop_pkd = cpu_to_be32(
381 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
382 else
383 wqe->send.sendop_pkd = cpu_to_be32(
384 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
385 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
386 break;
387
388 default:
389 return -EINVAL;
390 }
391
392 plen = 0;
393 if (wr->num_sge) {
394 if (wr->send_flags & IB_SEND_INLINE) {
395 ret = build_immd(sq, wqe->send.u.immd_src, wr,
396 T4_MAX_SEND_INLINE, &plen);
397 if (ret)
398 return ret;
399 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
400 plen;
401 } else {
402 ret = build_isgl((__be64 *)sq->queue,
403 (__be64 *)&sq->queue[sq->size],
404 wqe->send.u.isgl_src,
405 wr->sg_list, wr->num_sge, &plen);
406 if (ret)
407 return ret;
408 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
409 wr->num_sge * sizeof(struct fw_ri_sge);
410 }
411 } else {
412 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
413 wqe->send.u.immd_src[0].r1 = 0;
414 wqe->send.u.immd_src[0].r2 = 0;
415 wqe->send.u.immd_src[0].immdlen = 0;
416 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
417 plen = 0;
418 }
419 *len16 = DIV_ROUND_UP(size, 16);
420 wqe->send.plen = cpu_to_be32(plen);
421 return 0;
422 }
423
424 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
425 struct ib_send_wr *wr, u8 *len16)
426 {
427 u32 plen;
428 int size;
429 int ret;
430
431 if (wr->num_sge > T4_MAX_SEND_SGE)
432 return -EINVAL;
433 wqe->write.r2 = 0;
434 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
435 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
436 if (wr->num_sge) {
437 if (wr->send_flags & IB_SEND_INLINE) {
438 ret = build_immd(sq, wqe->write.u.immd_src, wr,
439 T4_MAX_WRITE_INLINE, &plen);
440 if (ret)
441 return ret;
442 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
443 plen;
444 } else {
445 ret = build_isgl((__be64 *)sq->queue,
446 (__be64 *)&sq->queue[sq->size],
447 wqe->write.u.isgl_src,
448 wr->sg_list, wr->num_sge, &plen);
449 if (ret)
450 return ret;
451 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
452 wr->num_sge * sizeof(struct fw_ri_sge);
453 }
454 } else {
455 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
456 wqe->write.u.immd_src[0].r1 = 0;
457 wqe->write.u.immd_src[0].r2 = 0;
458 wqe->write.u.immd_src[0].immdlen = 0;
459 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
460 plen = 0;
461 }
462 *len16 = DIV_ROUND_UP(size, 16);
463 wqe->write.plen = cpu_to_be32(plen);
464 return 0;
465 }
466
467 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
468 {
469 if (wr->num_sge > 1)
470 return -EINVAL;
471 if (wr->num_sge) {
472 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
473 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
474 >> 32));
475 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
476 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
477 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
478 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
479 >> 32));
480 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
481 } else {
482 wqe->read.stag_src = cpu_to_be32(2);
483 wqe->read.to_src_hi = 0;
484 wqe->read.to_src_lo = 0;
485 wqe->read.stag_sink = cpu_to_be32(2);
486 wqe->read.plen = 0;
487 wqe->read.to_sink_hi = 0;
488 wqe->read.to_sink_lo = 0;
489 }
490 wqe->read.r2 = 0;
491 wqe->read.r5 = 0;
492 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
493 return 0;
494 }
495
496 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
497 struct ib_recv_wr *wr, u8 *len16)
498 {
499 int ret;
500
501 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
502 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
503 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
504 if (ret)
505 return ret;
506 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
507 wr->num_sge * sizeof(struct fw_ri_sge), 16);
508 return 0;
509 }
510
511 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
512 struct ib_send_wr *wr, u8 *len16)
513 {
514
515 struct fw_ri_immd *imdp;
516 __be64 *p;
517 int i;
518 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
519 int rem;
520
521 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
522 return -EINVAL;
523
524 wqe->fr.qpbinde_to_dcacpu = 0;
525 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
526 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
527 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
528 wqe->fr.len_hi = 0;
529 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
530 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
531 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
532 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
533 0xffffffff);
534 WARN_ON(pbllen > T4_MAX_FR_IMMD);
535 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
536 imdp->op = FW_RI_DATA_IMMD;
537 imdp->r1 = 0;
538 imdp->r2 = 0;
539 imdp->immdlen = cpu_to_be32(pbllen);
540 p = (__be64 *)(imdp + 1);
541 rem = pbllen;
542 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
543 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
544 rem -= sizeof *p;
545 if (++p == (__be64 *)&sq->queue[sq->size])
546 p = (__be64 *)sq->queue;
547 }
548 BUG_ON(rem < 0);
549 while (rem) {
550 *p = 0;
551 rem -= sizeof *p;
552 if (++p == (__be64 *)&sq->queue[sq->size])
553 p = (__be64 *)sq->queue;
554 }
555 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
556 return 0;
557 }
558
559 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
560 u8 *len16)
561 {
562 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
563 wqe->inv.r2 = 0;
564 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
565 return 0;
566 }
567
568 void c4iw_qp_add_ref(struct ib_qp *qp)
569 {
570 PDBG("%s ib_qp %p\n", __func__, qp);
571 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
572 }
573
574 void c4iw_qp_rem_ref(struct ib_qp *qp)
575 {
576 PDBG("%s ib_qp %p\n", __func__, qp);
577 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
578 wake_up(&(to_c4iw_qp(qp)->wait));
579 }
580
581 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
582 struct ib_send_wr **bad_wr)
583 {
584 int err = 0;
585 u8 len16 = 0;
586 enum fw_wr_opcodes fw_opcode = 0;
587 enum fw_ri_wr_flags fw_flags;
588 struct c4iw_qp *qhp;
589 union t4_wr *wqe;
590 u32 num_wrs;
591 struct t4_swsqe *swsqe;
592 unsigned long flag;
593 u16 idx = 0;
594
595 qhp = to_c4iw_qp(ibqp);
596 spin_lock_irqsave(&qhp->lock, flag);
597 if (t4_wq_in_error(&qhp->wq)) {
598 spin_unlock_irqrestore(&qhp->lock, flag);
599 return -EINVAL;
600 }
601 num_wrs = t4_sq_avail(&qhp->wq);
602 if (num_wrs == 0) {
603 spin_unlock_irqrestore(&qhp->lock, flag);
604 return -ENOMEM;
605 }
606 while (wr) {
607 if (num_wrs == 0) {
608 err = -ENOMEM;
609 *bad_wr = wr;
610 break;
611 }
612 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
613 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
614
615 fw_flags = 0;
616 if (wr->send_flags & IB_SEND_SOLICITED)
617 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
618 if (wr->send_flags & IB_SEND_SIGNALED)
619 fw_flags |= FW_RI_COMPLETION_FLAG;
620 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
621 switch (wr->opcode) {
622 case IB_WR_SEND_WITH_INV:
623 case IB_WR_SEND:
624 if (wr->send_flags & IB_SEND_FENCE)
625 fw_flags |= FW_RI_READ_FENCE_FLAG;
626 fw_opcode = FW_RI_SEND_WR;
627 if (wr->opcode == IB_WR_SEND)
628 swsqe->opcode = FW_RI_SEND;
629 else
630 swsqe->opcode = FW_RI_SEND_WITH_INV;
631 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
632 break;
633 case IB_WR_RDMA_WRITE:
634 fw_opcode = FW_RI_RDMA_WRITE_WR;
635 swsqe->opcode = FW_RI_RDMA_WRITE;
636 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
637 break;
638 case IB_WR_RDMA_READ:
639 case IB_WR_RDMA_READ_WITH_INV:
640 fw_opcode = FW_RI_RDMA_READ_WR;
641 swsqe->opcode = FW_RI_READ_REQ;
642 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
643 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
644 else
645 fw_flags = 0;
646 err = build_rdma_read(wqe, wr, &len16);
647 if (err)
648 break;
649 swsqe->read_len = wr->sg_list[0].length;
650 if (!qhp->wq.sq.oldest_read)
651 qhp->wq.sq.oldest_read = swsqe;
652 break;
653 case IB_WR_FAST_REG_MR:
654 fw_opcode = FW_RI_FR_NSMR_WR;
655 swsqe->opcode = FW_RI_FAST_REGISTER;
656 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
657 break;
658 case IB_WR_LOCAL_INV:
659 if (wr->send_flags & IB_SEND_FENCE)
660 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
661 fw_opcode = FW_RI_INV_LSTAG_WR;
662 swsqe->opcode = FW_RI_LOCAL_INV;
663 err = build_inv_stag(wqe, wr, &len16);
664 break;
665 default:
666 PDBG("%s post of type=%d TBD!\n", __func__,
667 wr->opcode);
668 err = -EINVAL;
669 }
670 if (err) {
671 *bad_wr = wr;
672 break;
673 }
674 swsqe->idx = qhp->wq.sq.pidx;
675 swsqe->complete = 0;
676 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
677 swsqe->wr_id = wr->wr_id;
678
679 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
680
681 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
682 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
683 swsqe->opcode, swsqe->read_len);
684 wr = wr->next;
685 num_wrs--;
686 t4_sq_produce(&qhp->wq, len16);
687 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
688 }
689 if (t4_wq_db_enabled(&qhp->wq))
690 t4_ring_sq_db(&qhp->wq, idx);
691 spin_unlock_irqrestore(&qhp->lock, flag);
692 return err;
693 }
694
695 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
696 struct ib_recv_wr **bad_wr)
697 {
698 int err = 0;
699 struct c4iw_qp *qhp;
700 union t4_recv_wr *wqe;
701 u32 num_wrs;
702 u8 len16 = 0;
703 unsigned long flag;
704 u16 idx = 0;
705
706 qhp = to_c4iw_qp(ibqp);
707 spin_lock_irqsave(&qhp->lock, flag);
708 if (t4_wq_in_error(&qhp->wq)) {
709 spin_unlock_irqrestore(&qhp->lock, flag);
710 return -EINVAL;
711 }
712 num_wrs = t4_rq_avail(&qhp->wq);
713 if (num_wrs == 0) {
714 spin_unlock_irqrestore(&qhp->lock, flag);
715 return -ENOMEM;
716 }
717 while (wr) {
718 if (wr->num_sge > T4_MAX_RECV_SGE) {
719 err = -EINVAL;
720 *bad_wr = wr;
721 break;
722 }
723 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
724 qhp->wq.rq.wq_pidx *
725 T4_EQ_ENTRY_SIZE);
726 if (num_wrs)
727 err = build_rdma_recv(qhp, wqe, wr, &len16);
728 else
729 err = -ENOMEM;
730 if (err) {
731 *bad_wr = wr;
732 break;
733 }
734
735 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
736
737 wqe->recv.opcode = FW_RI_RECV_WR;
738 wqe->recv.r1 = 0;
739 wqe->recv.wrid = qhp->wq.rq.pidx;
740 wqe->recv.r2[0] = 0;
741 wqe->recv.r2[1] = 0;
742 wqe->recv.r2[2] = 0;
743 wqe->recv.len16 = len16;
744 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
745 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
746 t4_rq_produce(&qhp->wq, len16);
747 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
748 wr = wr->next;
749 num_wrs--;
750 }
751 if (t4_wq_db_enabled(&qhp->wq))
752 t4_ring_rq_db(&qhp->wq, idx);
753 spin_unlock_irqrestore(&qhp->lock, flag);
754 return err;
755 }
756
757 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
758 {
759 return -ENOSYS;
760 }
761
762 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
763 u8 *ecode)
764 {
765 int status;
766 int tagged;
767 int opcode;
768 int rqtype;
769 int send_inv;
770
771 if (!err_cqe) {
772 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
773 *ecode = 0;
774 return;
775 }
776
777 status = CQE_STATUS(err_cqe);
778 opcode = CQE_OPCODE(err_cqe);
779 rqtype = RQ_TYPE(err_cqe);
780 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
781 (opcode == FW_RI_SEND_WITH_SE_INV);
782 tagged = (opcode == FW_RI_RDMA_WRITE) ||
783 (rqtype && (opcode == FW_RI_READ_RESP));
784
785 switch (status) {
786 case T4_ERR_STAG:
787 if (send_inv) {
788 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
789 *ecode = RDMAP_CANT_INV_STAG;
790 } else {
791 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
792 *ecode = RDMAP_INV_STAG;
793 }
794 break;
795 case T4_ERR_PDID:
796 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
797 if ((opcode == FW_RI_SEND_WITH_INV) ||
798 (opcode == FW_RI_SEND_WITH_SE_INV))
799 *ecode = RDMAP_CANT_INV_STAG;
800 else
801 *ecode = RDMAP_STAG_NOT_ASSOC;
802 break;
803 case T4_ERR_QPID:
804 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
805 *ecode = RDMAP_STAG_NOT_ASSOC;
806 break;
807 case T4_ERR_ACCESS:
808 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
809 *ecode = RDMAP_ACC_VIOL;
810 break;
811 case T4_ERR_WRAP:
812 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
813 *ecode = RDMAP_TO_WRAP;
814 break;
815 case T4_ERR_BOUND:
816 if (tagged) {
817 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
818 *ecode = DDPT_BASE_BOUNDS;
819 } else {
820 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
821 *ecode = RDMAP_BASE_BOUNDS;
822 }
823 break;
824 case T4_ERR_INVALIDATE_SHARED_MR:
825 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
826 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
827 *ecode = RDMAP_CANT_INV_STAG;
828 break;
829 case T4_ERR_ECC:
830 case T4_ERR_ECC_PSTAG:
831 case T4_ERR_INTERNAL_ERR:
832 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
833 *ecode = 0;
834 break;
835 case T4_ERR_OUT_OF_RQE:
836 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
837 *ecode = DDPU_INV_MSN_NOBUF;
838 break;
839 case T4_ERR_PBL_ADDR_BOUND:
840 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
841 *ecode = DDPT_BASE_BOUNDS;
842 break;
843 case T4_ERR_CRC:
844 *layer_type = LAYER_MPA|DDP_LLP;
845 *ecode = MPA_CRC_ERR;
846 break;
847 case T4_ERR_MARKER:
848 *layer_type = LAYER_MPA|DDP_LLP;
849 *ecode = MPA_MARKER_ERR;
850 break;
851 case T4_ERR_PDU_LEN_ERR:
852 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
853 *ecode = DDPU_MSG_TOOBIG;
854 break;
855 case T4_ERR_DDP_VERSION:
856 if (tagged) {
857 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
858 *ecode = DDPT_INV_VERS;
859 } else {
860 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
861 *ecode = DDPU_INV_VERS;
862 }
863 break;
864 case T4_ERR_RDMA_VERSION:
865 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
866 *ecode = RDMAP_INV_VERS;
867 break;
868 case T4_ERR_OPCODE:
869 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
870 *ecode = RDMAP_INV_OPCODE;
871 break;
872 case T4_ERR_DDP_QUEUE_NUM:
873 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
874 *ecode = DDPU_INV_QN;
875 break;
876 case T4_ERR_MSN:
877 case T4_ERR_MSN_GAP:
878 case T4_ERR_MSN_RANGE:
879 case T4_ERR_IRD_OVERFLOW:
880 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
881 *ecode = DDPU_INV_MSN_RANGE;
882 break;
883 case T4_ERR_TBIT:
884 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
885 *ecode = 0;
886 break;
887 case T4_ERR_MO:
888 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
889 *ecode = DDPU_INV_MO;
890 break;
891 default:
892 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
893 *ecode = 0;
894 break;
895 }
896 }
897
898 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
899 gfp_t gfp)
900 {
901 struct fw_ri_wr *wqe;
902 struct sk_buff *skb;
903 struct terminate_message *term;
904
905 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
906 qhp->ep->hwtid);
907
908 skb = alloc_skb(sizeof *wqe, gfp);
909 if (!skb)
910 return;
911 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
912
913 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
914 memset(wqe, 0, sizeof *wqe);
915 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
916 wqe->flowid_len16 = cpu_to_be32(
917 FW_WR_FLOWID(qhp->ep->hwtid) |
918 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
919
920 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
921 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
922 term = (struct terminate_message *)wqe->u.terminate.termmsg;
923 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
924 term->layer_etype = qhp->attr.layer_etype;
925 term->ecode = qhp->attr.ecode;
926 } else
927 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
928 c4iw_ofld_send(&qhp->rhp->rdev, skb);
929 }
930
931 /*
932 * Assumes qhp lock is held.
933 */
934 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
935 struct c4iw_cq *schp)
936 {
937 int count;
938 int flushed;
939 unsigned long flag;
940
941 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
942
943 /* locking hierarchy: cq lock first, then qp lock. */
944 spin_lock_irqsave(&rchp->lock, flag);
945 spin_lock(&qhp->lock);
946 c4iw_flush_hw_cq(&rchp->cq);
947 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
948 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
949 spin_unlock(&qhp->lock);
950 spin_unlock_irqrestore(&rchp->lock, flag);
951 if (flushed) {
952 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
953 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
954 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
955 }
956
957 /* locking hierarchy: cq lock first, then qp lock. */
958 spin_lock_irqsave(&schp->lock, flag);
959 spin_lock(&qhp->lock);
960 c4iw_flush_hw_cq(&schp->cq);
961 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
962 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
963 spin_unlock(&qhp->lock);
964 spin_unlock_irqrestore(&schp->lock, flag);
965 if (flushed) {
966 spin_lock_irqsave(&schp->comp_handler_lock, flag);
967 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
968 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
969 }
970 }
971
972 static void flush_qp(struct c4iw_qp *qhp)
973 {
974 struct c4iw_cq *rchp, *schp;
975 unsigned long flag;
976
977 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
978 schp = get_chp(qhp->rhp, qhp->attr.scq);
979
980 if (qhp->ibqp.uobject) {
981 t4_set_wq_in_error(&qhp->wq);
982 t4_set_cq_in_error(&rchp->cq);
983 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
984 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
985 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
986 if (schp != rchp) {
987 t4_set_cq_in_error(&schp->cq);
988 spin_lock_irqsave(&schp->comp_handler_lock, flag);
989 (*schp->ibcq.comp_handler)(&schp->ibcq,
990 schp->ibcq.cq_context);
991 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
992 }
993 return;
994 }
995 __flush_qp(qhp, rchp, schp);
996 }
997
998 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
999 struct c4iw_ep *ep)
1000 {
1001 struct fw_ri_wr *wqe;
1002 int ret;
1003 struct sk_buff *skb;
1004
1005 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1006 ep->hwtid);
1007
1008 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1009 if (!skb)
1010 return -ENOMEM;
1011 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1012
1013 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1014 memset(wqe, 0, sizeof *wqe);
1015 wqe->op_compl = cpu_to_be32(
1016 FW_WR_OP(FW_RI_INIT_WR) |
1017 FW_WR_COMPL(1));
1018 wqe->flowid_len16 = cpu_to_be32(
1019 FW_WR_FLOWID(ep->hwtid) |
1020 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1021 wqe->cookie = (unsigned long) &ep->com.wr_wait;
1022
1023 wqe->u.fini.type = FW_RI_TYPE_FINI;
1024 ret = c4iw_ofld_send(&rhp->rdev, skb);
1025 if (ret)
1026 goto out;
1027
1028 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1029 qhp->wq.sq.qid, __func__);
1030 out:
1031 PDBG("%s ret %d\n", __func__, ret);
1032 return ret;
1033 }
1034
1035 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1036 {
1037 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1038 memset(&init->u, 0, sizeof init->u);
1039 switch (p2p_type) {
1040 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1041 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1042 init->u.write.stag_sink = cpu_to_be32(1);
1043 init->u.write.to_sink = cpu_to_be64(1);
1044 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1045 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1046 sizeof(struct fw_ri_immd),
1047 16);
1048 break;
1049 case FW_RI_INIT_P2PTYPE_READ_REQ:
1050 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1051 init->u.read.stag_src = cpu_to_be32(1);
1052 init->u.read.to_src_lo = cpu_to_be32(1);
1053 init->u.read.stag_sink = cpu_to_be32(1);
1054 init->u.read.to_sink_lo = cpu_to_be32(1);
1055 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1056 break;
1057 }
1058 }
1059
1060 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1061 {
1062 struct fw_ri_wr *wqe;
1063 int ret;
1064 struct sk_buff *skb;
1065
1066 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1067 qhp->ep->hwtid);
1068
1069 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1070 if (!skb)
1071 return -ENOMEM;
1072 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1073
1074 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1075 memset(wqe, 0, sizeof *wqe);
1076 wqe->op_compl = cpu_to_be32(
1077 FW_WR_OP(FW_RI_INIT_WR) |
1078 FW_WR_COMPL(1));
1079 wqe->flowid_len16 = cpu_to_be32(
1080 FW_WR_FLOWID(qhp->ep->hwtid) |
1081 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1082
1083 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1084
1085 wqe->u.init.type = FW_RI_TYPE_INIT;
1086 wqe->u.init.mpareqbit_p2ptype =
1087 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1088 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1089 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1090 if (qhp->attr.mpa_attr.recv_marker_enabled)
1091 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1092 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1093 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1094 if (qhp->attr.mpa_attr.crc_enabled)
1095 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1096
1097 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1098 FW_RI_QP_RDMA_WRITE_ENABLE |
1099 FW_RI_QP_BIND_ENABLE;
1100 if (!qhp->ibqp.uobject)
1101 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1102 FW_RI_QP_STAG0_ENABLE;
1103 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1104 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1105 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1106 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1107 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1108 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1109 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1110 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1111 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1112 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1113 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1114 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1115 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1116 rhp->rdev.lldi.vr->rq.start);
1117 if (qhp->attr.mpa_attr.initiator)
1118 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1119
1120 ret = c4iw_ofld_send(&rhp->rdev, skb);
1121 if (ret)
1122 goto out;
1123
1124 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1125 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1126 out:
1127 PDBG("%s ret %d\n", __func__, ret);
1128 return ret;
1129 }
1130
1131 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1132 enum c4iw_qp_attr_mask mask,
1133 struct c4iw_qp_attributes *attrs,
1134 int internal)
1135 {
1136 int ret = 0;
1137 struct c4iw_qp_attributes newattr = qhp->attr;
1138 int disconnect = 0;
1139 int terminate = 0;
1140 int abort = 0;
1141 int free = 0;
1142 struct c4iw_ep *ep = NULL;
1143
1144 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1145 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1146 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1147
1148 mutex_lock(&qhp->mutex);
1149
1150 /* Process attr changes if in IDLE */
1151 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1152 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1153 ret = -EIO;
1154 goto out;
1155 }
1156 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1157 newattr.enable_rdma_read = attrs->enable_rdma_read;
1158 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1159 newattr.enable_rdma_write = attrs->enable_rdma_write;
1160 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1161 newattr.enable_bind = attrs->enable_bind;
1162 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1163 if (attrs->max_ord > c4iw_max_read_depth) {
1164 ret = -EINVAL;
1165 goto out;
1166 }
1167 newattr.max_ord = attrs->max_ord;
1168 }
1169 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1170 if (attrs->max_ird > c4iw_max_read_depth) {
1171 ret = -EINVAL;
1172 goto out;
1173 }
1174 newattr.max_ird = attrs->max_ird;
1175 }
1176 qhp->attr = newattr;
1177 }
1178
1179 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1180 goto out;
1181 if (qhp->attr.state == attrs->next_state)
1182 goto out;
1183
1184 switch (qhp->attr.state) {
1185 case C4IW_QP_STATE_IDLE:
1186 switch (attrs->next_state) {
1187 case C4IW_QP_STATE_RTS:
1188 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1189 ret = -EINVAL;
1190 goto out;
1191 }
1192 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1193 ret = -EINVAL;
1194 goto out;
1195 }
1196 qhp->attr.mpa_attr = attrs->mpa_attr;
1197 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1198 qhp->ep = qhp->attr.llp_stream_handle;
1199 set_state(qhp, C4IW_QP_STATE_RTS);
1200
1201 /*
1202 * Ref the endpoint here and deref when we
1203 * disassociate the endpoint from the QP. This
1204 * happens in CLOSING->IDLE transition or *->ERROR
1205 * transition.
1206 */
1207 c4iw_get_ep(&qhp->ep->com);
1208 ret = rdma_init(rhp, qhp);
1209 if (ret)
1210 goto err;
1211 break;
1212 case C4IW_QP_STATE_ERROR:
1213 set_state(qhp, C4IW_QP_STATE_ERROR);
1214 flush_qp(qhp);
1215 break;
1216 default:
1217 ret = -EINVAL;
1218 goto out;
1219 }
1220 break;
1221 case C4IW_QP_STATE_RTS:
1222 switch (attrs->next_state) {
1223 case C4IW_QP_STATE_CLOSING:
1224 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1225 set_state(qhp, C4IW_QP_STATE_CLOSING);
1226 ep = qhp->ep;
1227 if (!internal) {
1228 abort = 0;
1229 disconnect = 1;
1230 c4iw_get_ep(&qhp->ep->com);
1231 }
1232 if (qhp->ibqp.uobject)
1233 t4_set_wq_in_error(&qhp->wq);
1234 ret = rdma_fini(rhp, qhp, ep);
1235 if (ret)
1236 goto err;
1237 break;
1238 case C4IW_QP_STATE_TERMINATE:
1239 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1240 qhp->attr.layer_etype = attrs->layer_etype;
1241 qhp->attr.ecode = attrs->ecode;
1242 if (qhp->ibqp.uobject)
1243 t4_set_wq_in_error(&qhp->wq);
1244 ep = qhp->ep;
1245 if (!internal)
1246 terminate = 1;
1247 disconnect = 1;
1248 c4iw_get_ep(&qhp->ep->com);
1249 break;
1250 case C4IW_QP_STATE_ERROR:
1251 set_state(qhp, C4IW_QP_STATE_ERROR);
1252 if (qhp->ibqp.uobject)
1253 t4_set_wq_in_error(&qhp->wq);
1254 if (!internal) {
1255 abort = 1;
1256 disconnect = 1;
1257 ep = qhp->ep;
1258 c4iw_get_ep(&qhp->ep->com);
1259 }
1260 goto err;
1261 break;
1262 default:
1263 ret = -EINVAL;
1264 goto out;
1265 }
1266 break;
1267 case C4IW_QP_STATE_CLOSING:
1268 if (!internal) {
1269 ret = -EINVAL;
1270 goto out;
1271 }
1272 switch (attrs->next_state) {
1273 case C4IW_QP_STATE_IDLE:
1274 flush_qp(qhp);
1275 set_state(qhp, C4IW_QP_STATE_IDLE);
1276 qhp->attr.llp_stream_handle = NULL;
1277 c4iw_put_ep(&qhp->ep->com);
1278 qhp->ep = NULL;
1279 wake_up(&qhp->wait);
1280 break;
1281 case C4IW_QP_STATE_ERROR:
1282 goto err;
1283 default:
1284 ret = -EINVAL;
1285 goto err;
1286 }
1287 break;
1288 case C4IW_QP_STATE_ERROR:
1289 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1290 ret = -EINVAL;
1291 goto out;
1292 }
1293 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1294 ret = -EINVAL;
1295 goto out;
1296 }
1297 set_state(qhp, C4IW_QP_STATE_IDLE);
1298 break;
1299 case C4IW_QP_STATE_TERMINATE:
1300 if (!internal) {
1301 ret = -EINVAL;
1302 goto out;
1303 }
1304 goto err;
1305 break;
1306 default:
1307 printk(KERN_ERR "%s in a bad state %d\n",
1308 __func__, qhp->attr.state);
1309 ret = -EINVAL;
1310 goto err;
1311 break;
1312 }
1313 goto out;
1314 err:
1315 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1316 qhp->wq.sq.qid);
1317
1318 /* disassociate the LLP connection */
1319 qhp->attr.llp_stream_handle = NULL;
1320 if (!ep)
1321 ep = qhp->ep;
1322 qhp->ep = NULL;
1323 set_state(qhp, C4IW_QP_STATE_ERROR);
1324 free = 1;
1325 wake_up(&qhp->wait);
1326 BUG_ON(!ep);
1327 flush_qp(qhp);
1328 out:
1329 mutex_unlock(&qhp->mutex);
1330
1331 if (terminate)
1332 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1333
1334 /*
1335 * If disconnect is 1, then we need to initiate a disconnect
1336 * on the EP. This can be a normal close (RTS->CLOSING) or
1337 * an abnormal close (RTS/CLOSING->ERROR).
1338 */
1339 if (disconnect) {
1340 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1341 GFP_KERNEL);
1342 c4iw_put_ep(&ep->com);
1343 }
1344
1345 /*
1346 * If free is 1, then we've disassociated the EP from the QP
1347 * and we need to dereference the EP.
1348 */
1349 if (free)
1350 c4iw_put_ep(&ep->com);
1351 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1352 return ret;
1353 }
1354
1355 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1356 {
1357 struct c4iw_dev *rhp;
1358 struct c4iw_qp *qhp;
1359 struct c4iw_qp_attributes attrs;
1360 struct c4iw_ucontext *ucontext;
1361
1362 qhp = to_c4iw_qp(ib_qp);
1363 rhp = qhp->rhp;
1364
1365 attrs.next_state = C4IW_QP_STATE_ERROR;
1366 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1367 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1368 else
1369 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1370 wait_event(qhp->wait, !qhp->ep);
1371
1372 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1373 atomic_dec(&qhp->refcnt);
1374 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1375
1376 ucontext = ib_qp->uobject ?
1377 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1378 destroy_qp(&rhp->rdev, &qhp->wq,
1379 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1380
1381 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1382 kfree(qhp);
1383 return 0;
1384 }
1385
1386 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1387 struct ib_udata *udata)
1388 {
1389 struct c4iw_dev *rhp;
1390 struct c4iw_qp *qhp;
1391 struct c4iw_pd *php;
1392 struct c4iw_cq *schp;
1393 struct c4iw_cq *rchp;
1394 struct c4iw_create_qp_resp uresp;
1395 int sqsize, rqsize;
1396 struct c4iw_ucontext *ucontext;
1397 int ret;
1398 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1399
1400 PDBG("%s ib_pd %p\n", __func__, pd);
1401
1402 if (attrs->qp_type != IB_QPT_RC)
1403 return ERR_PTR(-EINVAL);
1404
1405 php = to_c4iw_pd(pd);
1406 rhp = php->rhp;
1407 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1408 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1409 if (!schp || !rchp)
1410 return ERR_PTR(-EINVAL);
1411
1412 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1413 return ERR_PTR(-EINVAL);
1414
1415 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1416 if (rqsize > T4_MAX_RQ_SIZE)
1417 return ERR_PTR(-E2BIG);
1418
1419 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1420 if (sqsize > T4_MAX_SQ_SIZE)
1421 return ERR_PTR(-E2BIG);
1422
1423 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1424
1425
1426 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1427 if (!qhp)
1428 return ERR_PTR(-ENOMEM);
1429 qhp->wq.sq.size = sqsize;
1430 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1431 qhp->wq.rq.size = rqsize;
1432 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1433
1434 if (ucontext) {
1435 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1436 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1437 }
1438
1439 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1440 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1441
1442 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1443 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1444 if (ret)
1445 goto err1;
1446
1447 attrs->cap.max_recv_wr = rqsize - 1;
1448 attrs->cap.max_send_wr = sqsize - 1;
1449 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1450
1451 qhp->rhp = rhp;
1452 qhp->attr.pd = php->pdid;
1453 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1454 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1455 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1456 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1457 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1458 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1459 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1460 qhp->attr.state = C4IW_QP_STATE_IDLE;
1461 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1462 qhp->attr.enable_rdma_read = 1;
1463 qhp->attr.enable_rdma_write = 1;
1464 qhp->attr.enable_bind = 1;
1465 qhp->attr.max_ord = 1;
1466 qhp->attr.max_ird = 1;
1467 spin_lock_init(&qhp->lock);
1468 mutex_init(&qhp->mutex);
1469 init_waitqueue_head(&qhp->wait);
1470 atomic_set(&qhp->refcnt, 1);
1471
1472 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1473 if (ret)
1474 goto err2;
1475
1476 if (udata) {
1477 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1478 if (!mm1) {
1479 ret = -ENOMEM;
1480 goto err3;
1481 }
1482 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1483 if (!mm2) {
1484 ret = -ENOMEM;
1485 goto err4;
1486 }
1487 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1488 if (!mm3) {
1489 ret = -ENOMEM;
1490 goto err5;
1491 }
1492 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1493 if (!mm4) {
1494 ret = -ENOMEM;
1495 goto err6;
1496 }
1497 if (t4_sq_onchip(&qhp->wq.sq)) {
1498 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1499 if (!mm5) {
1500 ret = -ENOMEM;
1501 goto err7;
1502 }
1503 uresp.flags = C4IW_QPF_ONCHIP;
1504 } else
1505 uresp.flags = 0;
1506 uresp.qid_mask = rhp->rdev.qpmask;
1507 uresp.sqid = qhp->wq.sq.qid;
1508 uresp.sq_size = qhp->wq.sq.size;
1509 uresp.sq_memsize = qhp->wq.sq.memsize;
1510 uresp.rqid = qhp->wq.rq.qid;
1511 uresp.rq_size = qhp->wq.rq.size;
1512 uresp.rq_memsize = qhp->wq.rq.memsize;
1513 spin_lock(&ucontext->mmap_lock);
1514 if (mm5) {
1515 uresp.ma_sync_key = ucontext->key;
1516 ucontext->key += PAGE_SIZE;
1517 }
1518 uresp.sq_key = ucontext->key;
1519 ucontext->key += PAGE_SIZE;
1520 uresp.rq_key = ucontext->key;
1521 ucontext->key += PAGE_SIZE;
1522 uresp.sq_db_gts_key = ucontext->key;
1523 ucontext->key += PAGE_SIZE;
1524 uresp.rq_db_gts_key = ucontext->key;
1525 ucontext->key += PAGE_SIZE;
1526 spin_unlock(&ucontext->mmap_lock);
1527 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1528 if (ret)
1529 goto err8;
1530 mm1->key = uresp.sq_key;
1531 mm1->addr = qhp->wq.sq.phys_addr;
1532 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1533 insert_mmap(ucontext, mm1);
1534 mm2->key = uresp.rq_key;
1535 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1536 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1537 insert_mmap(ucontext, mm2);
1538 mm3->key = uresp.sq_db_gts_key;
1539 mm3->addr = qhp->wq.sq.udb;
1540 mm3->len = PAGE_SIZE;
1541 insert_mmap(ucontext, mm3);
1542 mm4->key = uresp.rq_db_gts_key;
1543 mm4->addr = qhp->wq.rq.udb;
1544 mm4->len = PAGE_SIZE;
1545 insert_mmap(ucontext, mm4);
1546 if (mm5) {
1547 mm5->key = uresp.ma_sync_key;
1548 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1549 + A_PCIE_MA_SYNC) & PAGE_MASK;
1550 mm5->len = PAGE_SIZE;
1551 insert_mmap(ucontext, mm5);
1552 }
1553 }
1554 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1555 init_timer(&(qhp->timer));
1556 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1557 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1558 qhp->wq.sq.qid);
1559 return &qhp->ibqp;
1560 err8:
1561 kfree(mm5);
1562 err7:
1563 kfree(mm4);
1564 err6:
1565 kfree(mm3);
1566 err5:
1567 kfree(mm2);
1568 err4:
1569 kfree(mm1);
1570 err3:
1571 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1572 err2:
1573 destroy_qp(&rhp->rdev, &qhp->wq,
1574 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1575 err1:
1576 kfree(qhp);
1577 return ERR_PTR(ret);
1578 }
1579
1580 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1581 int attr_mask, struct ib_udata *udata)
1582 {
1583 struct c4iw_dev *rhp;
1584 struct c4iw_qp *qhp;
1585 enum c4iw_qp_attr_mask mask = 0;
1586 struct c4iw_qp_attributes attrs;
1587
1588 PDBG("%s ib_qp %p\n", __func__, ibqp);
1589
1590 /* iwarp does not support the RTR state */
1591 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1592 attr_mask &= ~IB_QP_STATE;
1593
1594 /* Make sure we still have something left to do */
1595 if (!attr_mask)
1596 return 0;
1597
1598 memset(&attrs, 0, sizeof attrs);
1599 qhp = to_c4iw_qp(ibqp);
1600 rhp = qhp->rhp;
1601
1602 attrs.next_state = c4iw_convert_state(attr->qp_state);
1603 attrs.enable_rdma_read = (attr->qp_access_flags &
1604 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1605 attrs.enable_rdma_write = (attr->qp_access_flags &
1606 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1607 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1608
1609
1610 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1611 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1612 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1613 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1614 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1615
1616 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1617 }
1618
1619 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1620 {
1621 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1622 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1623 }