4 ** (c) Copyright 1999 Red Hat Software
5 ** (c) Copyright 1999 SuSE GmbH
6 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** (c) Copyright 2000 Grant Grundler
8 ** (c) Copyright 2006 Helge Deller
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
15 ** This module provides access to Dino PCI bus (config/IOport spaces)
16 ** and helps manage Dino IRQ lines.
18 ** Dino interrupt handling is a bit complicated.
19 ** Dino always writes to the broadcast EIR via irr0 for now.
20 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
21 ** Only one processor interrupt is used for the 11 IRQ line
24 ** The different between Built-in Dino and Card-Mode
25 ** dino is in chip initialization and pci device initialization.
27 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port
28 ** BARs are configured and used by the driver. Programming MMIO address
29 ** requires substantial knowledge of available Host I/O address ranges
30 ** is currently not supported. Port/Config accessor functions are the
31 ** same. "BIOS" differences are handled within the existing routines.
35 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
36 ** - added support for the integrated RS232.
40 ** TODO: create a virtual address for each Dino HPA.
41 ** GSC code might be able to do this since IODC data tells us
42 ** how many pages are used. PCI subsystem could (must?) do this
43 ** for PCI drivers devices which implement/use MMIO registers.
46 #include <linux/delay.h>
47 #include <linux/types.h>
48 #include <linux/kernel.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/ioport.h>
52 #include <linux/slab.h>
53 #include <linux/interrupt.h> /* for struct irqaction */
54 #include <linux/spinlock.h> /* for spinlock_t and prototypes */
58 #include <asm/system.h>
60 #include <asm/hardware.h>
67 #define DBG(x...) printk(x)
73 ** Config accessor functions only pass in the 8-bit bus number
74 ** and not the 8-bit "PCI Segment" number. Each Dino will be
75 ** assigned a PCI bus number based on "when" it's discovered.
77 ** The "secondary" bus number is set to this before calling
78 ** pci_scan_bus(). If any PPB's are present, the scan will
79 ** discover them and update the "secondary" and "subordinate"
80 ** fields in Dino's pci_bus structure.
82 ** Changes in the configuration *will* result in a different
83 ** bus number for each dino.
86 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA)
87 #define is_cujo(id) ((id)->hversion == 0x682)
89 #define DINO_IAR0 0x004
90 #define DINO_IODC_ADDR 0x008
91 #define DINO_IODC_DATA_0 0x008
92 #define DINO_IODC_DATA_1 0x008
93 #define DINO_IRR0 0x00C
94 #define DINO_IAR1 0x010
95 #define DINO_IRR1 0x014
96 #define DINO_IMR 0x018
97 #define DINO_IPR 0x01C
98 #define DINO_TOC_ADDR 0x020
99 #define DINO_ICR 0x024
100 #define DINO_ILR 0x028
101 #define DINO_IO_COMMAND 0x030
102 #define DINO_IO_STATUS 0x034
103 #define DINO_IO_CONTROL 0x038
104 #define DINO_IO_GSC_ERR_RESP 0x040
105 #define DINO_IO_ERR_INFO 0x044
106 #define DINO_IO_PCI_ERR_RESP 0x048
107 #define DINO_IO_FBB_EN 0x05c
108 #define DINO_IO_ADDR_EN 0x060
109 #define DINO_PCI_ADDR 0x064
110 #define DINO_CONFIG_DATA 0x068
111 #define DINO_IO_DATA 0x06c
112 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */
113 #define DINO_GSC2X_CONFIG 0x7b4
114 #define DINO_GMASK 0x800
115 #define DINO_PAMR 0x804
116 #define DINO_PAPR 0x808
117 #define DINO_DAMODE 0x80c
118 #define DINO_PCICMD 0x810
119 #define DINO_PCISTS 0x814
120 #define DINO_MLTIM 0x81c
121 #define DINO_BRDG_FEAT 0x820
122 #define DINO_PCIROR 0x824
123 #define DINO_PCIWOR 0x828
124 #define DINO_TLTIM 0x830
126 #define DINO_IRQS 11 /* bits 0-10 are architected */
127 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
128 #define DINO_LOCAL_IRQS (DINO_IRQS+1)
130 #define DINO_MASK_IRQ(x) (1<<(x))
132 #define PCIINTA 0x001
133 #define PCIINTB 0x002
134 #define PCIINTC 0x004
135 #define PCIINTD 0x008
136 #define PCIINTE 0x010
137 #define PCIINTF 0x020
138 #define GSCEXTINT 0x040
139 /* #define xxx 0x080 - bit 7 is "default" */
140 /* #define xxx 0x100 - bit 8 not used */
141 /* #define xxx 0x200 - bit 9 not used */
142 #define RS232INT 0x400
146 struct pci_hba_data hba
; /* 'C' inheritance - must be first */
147 spinlock_t dinosaur_pen
;
148 unsigned long txn_addr
; /* EIR addr to generate interrupt */
149 u32 txn_data
; /* EIR data assign to each dino */
150 u32 imr
; /* IRQ's which are enabled */
151 int global_irq
[DINO_LOCAL_IRQS
]; /* map IMR bit to global irq */
153 unsigned int dino_irr0
; /* save most recent IRQ line stat */
157 /* Looks nice and keeps the compiler happy */
158 #define DINO_DEV(d) ((struct dino_device *) d)
162 * Dino Configuration Space Accessor Functions
165 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
168 * keep the current highest bus count to assist in allocating busses. This
169 * tries to keep a global bus count total so that when we discover an
170 * entirely new bus, it can be given a unique bus number.
172 static int dino_current_bus
= 0;
174 static int dino_cfg_read(struct pci_bus
*bus
, unsigned int devfn
, int where
,
177 struct dino_device
*d
= DINO_DEV(parisc_walk_tree(bus
->bridge
));
178 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->secondary
;
179 u32 v
= DINO_CFG_TOK(local_bus
, devfn
, where
& ~3);
180 void __iomem
*base_addr
= d
->hba
.base_addr
;
183 DBG("%s: %p, %d, %d, %d\n", __func__
, base_addr
, devfn
, where
,
185 spin_lock_irqsave(&d
->dinosaur_pen
, flags
);
187 /* tell HW which CFG address */
188 __raw_writel(v
, base_addr
+ DINO_PCI_ADDR
);
190 /* generate cfg read cycle */
192 *val
= readb(base_addr
+ DINO_CONFIG_DATA
+ (where
& 3));
193 } else if (size
== 2) {
194 *val
= readw(base_addr
+ DINO_CONFIG_DATA
+ (where
& 2));
195 } else if (size
== 4) {
196 *val
= readl(base_addr
+ DINO_CONFIG_DATA
);
199 spin_unlock_irqrestore(&d
->dinosaur_pen
, flags
);
204 * Dino address stepping "feature":
205 * When address stepping, Dino attempts to drive the bus one cycle too soon
206 * even though the type of cycle (config vs. MMIO) might be different.
207 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
209 static int dino_cfg_write(struct pci_bus
*bus
, unsigned int devfn
, int where
,
212 struct dino_device
*d
= DINO_DEV(parisc_walk_tree(bus
->bridge
));
213 u32 local_bus
= (bus
->parent
== NULL
) ? 0 : bus
->secondary
;
214 u32 v
= DINO_CFG_TOK(local_bus
, devfn
, where
& ~3);
215 void __iomem
*base_addr
= d
->hba
.base_addr
;
218 DBG("%s: %p, %d, %d, %d\n", __func__
, base_addr
, devfn
, where
,
220 spin_lock_irqsave(&d
->dinosaur_pen
, flags
);
222 /* avoid address stepping feature */
223 __raw_writel(v
& 0xffffff00, base_addr
+ DINO_PCI_ADDR
);
224 __raw_readl(base_addr
+ DINO_CONFIG_DATA
);
226 /* tell HW which CFG address */
227 __raw_writel(v
, base_addr
+ DINO_PCI_ADDR
);
228 /* generate cfg read cycle */
230 writeb(val
, base_addr
+ DINO_CONFIG_DATA
+ (where
& 3));
231 } else if (size
== 2) {
232 writew(val
, base_addr
+ DINO_CONFIG_DATA
+ (where
& 2));
233 } else if (size
== 4) {
234 writel(val
, base_addr
+ DINO_CONFIG_DATA
);
237 spin_unlock_irqrestore(&d
->dinosaur_pen
, flags
);
241 static struct pci_ops dino_cfg_ops
= {
242 .read
= dino_cfg_read
,
243 .write
= dino_cfg_write
,
248 * Dino "I/O Port" Space Accessor Functions
250 * Many PCI devices don't require use of I/O port space (eg Tulip,
251 * NCR720) since they export the same registers to both MMIO and
252 * I/O port space. Performance is going to stink if drivers use
253 * I/O port instead of MMIO.
256 #define DINO_PORT_IN(type, size, mask) \
257 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
260 unsigned long flags; \
261 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
262 /* tell HW which IO Port address */ \
263 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
264 /* generate I/O PORT read cycle */ \
265 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
266 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
270 DINO_PORT_IN(b
, 8, 3)
271 DINO_PORT_IN(w
, 16, 2)
272 DINO_PORT_IN(l
, 32, 0)
274 #define DINO_PORT_OUT(type, size, mask) \
275 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
277 unsigned long flags; \
278 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
279 /* tell HW which IO port address */ \
280 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
281 /* generate cfg write cycle */ \
282 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
283 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
286 DINO_PORT_OUT(b
, 8, 3)
287 DINO_PORT_OUT(w
, 16, 2)
288 DINO_PORT_OUT(l
, 32, 0)
290 static struct pci_port_ops dino_port_ops
= {
299 static void dino_mask_irq(struct irq_data
*d
)
301 struct dino_device
*dino_dev
= irq_data_get_irq_chip_data(d
);
302 int local_irq
= gsc_find_local_irq(d
->irq
, dino_dev
->global_irq
, DINO_LOCAL_IRQS
);
304 DBG(KERN_WARNING
"%s(0x%p, %d)\n", __func__
, dino_dev
, d
->irq
);
306 /* Clear the matching bit in the IMR register */
307 dino_dev
->imr
&= ~(DINO_MASK_IRQ(local_irq
));
308 __raw_writel(dino_dev
->imr
, dino_dev
->hba
.base_addr
+DINO_IMR
);
311 static void dino_unmask_irq(struct irq_data
*d
)
313 struct dino_device
*dino_dev
= irq_data_get_irq_chip_data(d
);
314 int local_irq
= gsc_find_local_irq(d
->irq
, dino_dev
->global_irq
, DINO_LOCAL_IRQS
);
317 DBG(KERN_WARNING
"%s(0x%p, %d)\n", __func__
, dino_dev
, d
->irq
);
320 ** clear pending IRQ bits
322 ** This does NOT change ILR state!
323 ** See comment below for ILR usage.
325 __raw_readl(dino_dev
->hba
.base_addr
+DINO_IPR
);
327 /* set the matching bit in the IMR register */
328 dino_dev
->imr
|= DINO_MASK_IRQ(local_irq
); /* used in dino_isr() */
329 __raw_writel( dino_dev
->imr
, dino_dev
->hba
.base_addr
+DINO_IMR
);
331 /* Emulate "Level Triggered" Interrupt
332 ** Basically, a driver is blowing it if the IRQ line is asserted
333 ** while the IRQ is disabled. But tulip.c seems to do that....
334 ** Give 'em a kluge award and a nice round of applause!
336 ** The gsc_write will generate an interrupt which invokes dino_isr().
337 ** dino_isr() will read IPR and find nothing. But then catch this
338 ** when it also checks ILR.
340 tmp
= __raw_readl(dino_dev
->hba
.base_addr
+DINO_ILR
);
341 if (tmp
& DINO_MASK_IRQ(local_irq
)) {
342 DBG(KERN_WARNING
"%s(): IRQ asserted! (ILR 0x%x)\n",
344 gsc_writel(dino_dev
->txn_data
, dino_dev
->txn_addr
);
348 static struct irq_chip dino_interrupt_type
= {
350 .irq_unmask
= dino_unmask_irq
,
351 .irq_mask
= dino_mask_irq
,
356 * Handle a Processor interrupt generated by Dino.
358 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
359 * wedging the CPU. Could be removed or made optional at some point.
361 static irqreturn_t
dino_isr(int irq
, void *intr_dev
)
363 struct dino_device
*dino_dev
= intr_dev
;
367 /* read and acknowledge pending interrupts */
369 dino_dev
->dino_irr0
=
371 mask
= __raw_readl(dino_dev
->hba
.base_addr
+DINO_IRR0
) & DINO_IRR_MASK
;
378 int local_irq
= __ffs(mask
);
379 int irq
= dino_dev
->global_irq
[local_irq
];
380 DBG(KERN_DEBUG
"%s(%d, %p) mask 0x%x\n",
381 __func__
, irq
, intr_dev
, mask
);
382 generic_handle_irq(irq
);
383 mask
&= ~(1 << local_irq
);
386 /* Support for level triggered IRQ lines.
388 ** Dropping this support would make this routine *much* faster.
389 ** But since PCI requires level triggered IRQ line to share lines...
390 ** device drivers may assume lines are level triggered (and not
391 ** edge triggered like EISA/ISA can be).
393 mask
= __raw_readl(dino_dev
->hba
.base_addr
+DINO_ILR
) & dino_dev
->imr
;
397 printk(KERN_ERR
"Dino 0x%p: stuck interrupt %d\n",
398 dino_dev
->hba
.base_addr
, mask
);
404 static void dino_assign_irq(struct dino_device
*dino
, int local_irq
, int *irqp
)
406 int irq
= gsc_assign_irq(&dino_interrupt_type
, dino
);
411 dino
->global_irq
[local_irq
] = irq
;
414 static void dino_choose_irq(struct parisc_device
*dev
, void *ctrl
)
417 struct dino_device
*dino
= ctrl
;
419 switch (dev
->id
.sversion
) {
420 case 0x00084: irq
= 8; break; /* PS/2 */
421 case 0x0008c: irq
= 10; break; /* RS232 */
422 case 0x00096: irq
= 8; break; /* PS/2 */
423 default: return; /* Unknown */
426 dino_assign_irq(dino
, irq
, &dev
->irq
);
431 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
432 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
434 static void __devinit
quirk_cirrus_cardbus(struct pci_dev
*dev
)
436 u8 new_irq
= dev
->irq
- 1;
437 printk(KERN_INFO
"PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
438 pci_name(dev
), dev
->irq
, new_irq
);
441 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS
, PCI_DEVICE_ID_CIRRUS_6832
, quirk_cirrus_cardbus
);
447 DBG("dino_bios_init\n");
451 * dino_card_setup - Set up the memory space for a Dino in card mode.
452 * @bus: the bus under this dino
454 * Claim an 8MB chunk of unused IO space and call the generic PCI routines
455 * to set up the addresses of the devices on this bus.
457 #define _8MB 0x00800000UL
459 dino_card_setup(struct pci_bus
*bus
, void __iomem
*base_addr
)
462 struct dino_device
*dino_dev
= DINO_DEV(parisc_walk_tree(bus
->bridge
));
463 struct resource
*res
;
467 res
= &dino_dev
->hba
.lmmio_space
;
468 res
->flags
= IORESOURCE_MEM
;
469 size
= scnprintf(name
, sizeof(name
), "Dino LMMIO (%s)",
470 dev_name(bus
->bridge
));
471 res
->name
= kmalloc(size
+1, GFP_KERNEL
);
473 strcpy((char *)res
->name
, name
);
475 res
->name
= dino_dev
->hba
.lmmio_space
.name
;
478 if (ccio_allocate_resource(dino_dev
->hba
.dev
, res
, _8MB
,
479 F_EXTEND(0xf0000000UL
) | _8MB
,
480 F_EXTEND(0xffffffffUL
) &~ _8MB
, _8MB
) < 0) {
481 struct list_head
*ln
, *tmp_ln
;
483 printk(KERN_ERR
"Dino: cannot attach bus %s\n",
484 dev_name(bus
->bridge
));
485 /* kill the bus, we can't do anything with it */
486 list_for_each_safe(ln
, tmp_ln
, &bus
->devices
) {
487 struct pci_dev
*dev
= pci_dev_b(ln
);
489 list_del(&dev
->bus_list
);
494 bus
->resource
[1] = res
;
495 bus
->resource
[0] = &(dino_dev
->hba
.io_space
);
497 /* Now tell dino what range it has */
498 for (i
= 1; i
< 31; i
++) {
499 if (res
->start
== F_EXTEND(0xf0000000UL
| (i
* _8MB
)))
502 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
503 i
, res
->start
, base_addr
+ DINO_IO_ADDR_EN
);
504 __raw_writel(1 << i
, base_addr
+ DINO_IO_ADDR_EN
);
508 dino_card_fixup(struct pci_dev
*dev
)
513 ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
514 ** Not sure they were ever productized.
515 ** Die here since we'll die later in dino_inb() anyway.
517 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
518 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
522 ** Set Latency Timer to 0xff (not a shared bus)
523 ** Set CACHELINE_SIZE.
525 dino_cfg_write(dev
->bus
, dev
->devfn
,
526 PCI_CACHE_LINE_SIZE
, 2, 0xff00 | L1_CACHE_BYTES
/4);
529 ** Program INT_LINE for card-mode devices.
530 ** The cards are hardwired according to this algorithm.
531 ** And it doesn't matter if PPB's are present or not since
532 ** the IRQ lines bypass the PPB.
534 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
535 ** The additional "-1" adjusts for skewing the IRQ<->slot.
537 dino_cfg_read(dev
->bus
, dev
->devfn
, PCI_INTERRUPT_PIN
, 1, &irq_pin
);
538 dev
->irq
= pci_swizzle_interrupt_pin(dev
, irq_pin
) - 1;
540 /* Shouldn't really need to do this but it's in case someone tries
541 ** to bypass PCI services and look at the card themselves.
543 dino_cfg_write(dev
->bus
, dev
->devfn
, PCI_INTERRUPT_LINE
, 1, dev
->irq
);
546 /* The alignment contraints for PCI bridges under dino */
547 #define DINO_BRIDGE_ALIGN 0x100000
551 dino_fixup_bus(struct pci_bus
*bus
)
553 struct list_head
*ln
;
555 struct dino_device
*dino_dev
= DINO_DEV(parisc_walk_tree(bus
->bridge
));
556 int port_base
= HBA_PORT_BASE(dino_dev
->hba
.hba_num
);
558 DBG(KERN_WARNING
"%s(0x%p) bus %d platform_data 0x%p\n",
559 __func__
, bus
, bus
->secondary
,
560 bus
->bridge
->platform_data
);
562 /* Firmware doesn't set up card-mode dino, so we have to */
563 if (is_card_dino(&dino_dev
->hba
.dev
->id
)) {
564 dino_card_setup(bus
, dino_dev
->hba
.base_addr
);
565 } else if (bus
->parent
) {
568 pci_read_bridge_bases(bus
);
571 for(i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
572 if((bus
->self
->resource
[i
].flags
&
573 (IORESOURCE_IO
| IORESOURCE_MEM
)) == 0)
576 if(bus
->self
->resource
[i
].flags
& IORESOURCE_MEM
) {
577 /* There's a quirk to alignment of
578 * bridge memory resources: the start
579 * is the alignment and start-end is
580 * the size. However, firmware will
581 * have assigned start and end, so we
582 * need to take this into account */
583 bus
->self
->resource
[i
].end
= bus
->self
->resource
[i
].end
- bus
->self
->resource
[i
].start
+ DINO_BRIDGE_ALIGN
;
584 bus
->self
->resource
[i
].start
= DINO_BRIDGE_ALIGN
;
588 DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n",
589 dev_name(&bus
->self
->dev
), i
,
590 bus
->self
->resource
[i
].start
,
591 bus
->self
->resource
[i
].end
);
592 WARN_ON(pci_assign_resource(bus
->self
, i
));
593 DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n",
594 dev_name(&bus
->self
->dev
), i
,
595 bus
->self
->resource
[i
].start
,
596 bus
->self
->resource
[i
].end
);
601 list_for_each(ln
, &bus
->devices
) {
605 if (is_card_dino(&dino_dev
->hba
.dev
->id
))
606 dino_card_fixup(dev
);
609 ** P2PB's only have 2 BARs, no IRQs.
610 ** I'd like to just ignore them for now.
612 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
)
615 /* Adjust the I/O Port space addresses */
616 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
617 struct resource
*res
= &dev
->resource
[i
];
618 if (res
->flags
& IORESOURCE_IO
) {
619 res
->start
|= port_base
;
620 res
->end
|= port_base
;
623 /* Sign Extend MMIO addresses */
624 else if (res
->flags
& IORESOURCE_MEM
) {
625 res
->start
|= F_EXTEND(0UL);
626 res
->end
|= F_EXTEND(0UL);
630 /* null out the ROM resource if there is one (we don't
631 * care about an expansion rom on parisc, since it
632 * usually contains (x86) bios code) */
633 dev
->resource
[PCI_ROM_RESOURCE
].flags
= 0;
635 if(dev
->irq
== 255) {
637 #define DINO_FIX_UNASSIGNED_INTERRUPTS
638 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
640 /* This code tries to assign an unassigned
641 * interrupt. Leave it disabled unless you
642 * *really* know what you're doing since the
643 * pin<->interrupt line mapping varies by bus
648 dino_cfg_read(dev
->bus
, dev
->devfn
,
649 PCI_INTERRUPT_PIN
, 1, &irq_pin
);
650 irq_pin
= pci_swizzle_interrupt_pin(dev
, irq_pin
) - 1;
651 printk(KERN_WARNING
"Device %s has undefined IRQ, "
652 "setting to %d\n", pci_name(dev
), irq_pin
);
653 dino_cfg_write(dev
->bus
, dev
->devfn
,
654 PCI_INTERRUPT_LINE
, 1, irq_pin
);
655 dino_assign_irq(dino_dev
, irq_pin
, &dev
->irq
);
658 printk(KERN_WARNING
"Device %s has unassigned IRQ\n", pci_name(dev
));
661 /* Adjust INT_LINE for that busses region */
662 dino_assign_irq(dino_dev
, dev
->irq
, &dev
->irq
);
668 static struct pci_bios_ops dino_bios_ops
= {
669 .init
= dino_bios_init
,
670 .fixup_bus
= dino_fixup_bus
675 * Initialise a DINO controller chip
678 dino_card_init(struct dino_device
*dino_dev
)
680 u32 brdg_feat
= 0x00784e05;
681 unsigned long status
;
683 status
= __raw_readl(dino_dev
->hba
.base_addr
+DINO_IO_STATUS
);
684 if (status
& 0x0000ff80) {
685 __raw_writel(0x00000005,
686 dino_dev
->hba
.base_addr
+DINO_IO_COMMAND
);
690 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_GMASK
);
691 __raw_writel(0x00000001, dino_dev
->hba
.base_addr
+DINO_IO_FBB_EN
);
692 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_ICR
);
695 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
697 ** PCX-L processors don't support XQL like Dino wants it.
698 ** PCX-L2 ignore XQL signal and it doesn't matter.
700 brdg_feat
&= ~0x4; /* UXQL */
702 __raw_writel( brdg_feat
, dino_dev
->hba
.base_addr
+DINO_BRDG_FEAT
);
705 ** Don't enable address decoding until we know which I/O range
706 ** currently is available from the host. Only affects MMIO
707 ** and not I/O port space.
709 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_IO_ADDR_EN
);
711 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_DAMODE
);
712 __raw_writel(0x00222222, dino_dev
->hba
.base_addr
+DINO_PCIROR
);
713 __raw_writel(0x00222222, dino_dev
->hba
.base_addr
+DINO_PCIWOR
);
715 __raw_writel(0x00000040, dino_dev
->hba
.base_addr
+DINO_MLTIM
);
716 __raw_writel(0x00000080, dino_dev
->hba
.base_addr
+DINO_IO_CONTROL
);
717 __raw_writel(0x0000008c, dino_dev
->hba
.base_addr
+DINO_TLTIM
);
719 /* Disable PAMR before writing PAPR */
720 __raw_writel(0x0000007e, dino_dev
->hba
.base_addr
+DINO_PAMR
);
721 __raw_writel(0x0000007f, dino_dev
->hba
.base_addr
+DINO_PAPR
);
722 __raw_writel(0x00000000, dino_dev
->hba
.base_addr
+DINO_PAMR
);
725 ** Dino ERS encourages enabling FBB (0x6f).
726 ** We can't until we know *all* devices below us can support it.
727 ** (Something in device configuration header tells us).
729 __raw_writel(0x0000004f, dino_dev
->hba
.base_addr
+DINO_PCICMD
);
731 /* Somewhere, the PCI spec says give devices 1 second
732 ** to recover from the #RESET being de-asserted.
733 ** Experience shows most devices only need 10ms.
734 ** This short-cut speeds up booting significantly.
736 mdelay(pci_post_reset_delay
);
740 dino_bridge_init(struct dino_device
*dino_dev
, const char *name
)
742 unsigned long io_addr
;
743 int result
, i
, count
=0;
744 struct resource
*res
, *prevres
= NULL
;
746 * Decoding IO_ADDR_EN only works for Built-in Dino
747 * since PDC has already initialized this.
750 io_addr
= __raw_readl(dino_dev
->hba
.base_addr
+ DINO_IO_ADDR_EN
);
752 printk(KERN_WARNING
"%s: No PCI devices enabled.\n", name
);
756 res
= &dino_dev
->hba
.lmmio_space
;
757 for (i
= 0; i
< 32; i
++) {
758 unsigned long start
, end
;
760 if((io_addr
& (1 << i
)) == 0)
763 start
= F_EXTEND(0xf0000000UL
) | (i
<< 23);
764 end
= start
+ 8 * 1024 * 1024 - 1;
766 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count
,
769 if(prevres
&& prevres
->end
+ 1 == start
) {
772 if(count
>= DINO_MAX_LMMIO_RESOURCES
) {
773 printk(KERN_ERR
"%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name
, count
, start
, end
);
779 res
->flags
= IORESOURCE_MEM
;
780 res
->name
= kmalloc(64, GFP_KERNEL
);
782 snprintf((char *)res
->name
, 64, "%s LMMIO %d",
789 res
= &dino_dev
->hba
.lmmio_space
;
791 for(i
= 0; i
< DINO_MAX_LMMIO_RESOURCES
; i
++) {
792 if(res
[i
].flags
== 0)
795 result
= ccio_request_resource(dino_dev
->hba
.dev
, &res
[i
]);
797 printk(KERN_ERR
"%s: failed to claim PCI Bus address "
798 "space %d (0x%lx-0x%lx)!\n", name
, i
,
799 (unsigned long)res
[i
].start
, (unsigned long)res
[i
].end
);
806 static int __init
dino_common_init(struct parisc_device
*dev
,
807 struct dino_device
*dino_dev
, const char *name
)
811 struct gsc_irq gsc_irq
;
812 struct resource
*res
;
814 pcibios_register_hba(&dino_dev
->hba
);
816 pci_bios
= &dino_bios_ops
; /* used by pci_scan_bus() */
817 pci_port
= &dino_port_ops
;
820 ** Note: SMP systems can make use of IRR1/IAR1 registers
821 ** But it won't buy much performance except in very
822 ** specific applications/configurations. Note Dino
823 ** still only has 11 IRQ input lines - just map some of them
824 ** to a different processor.
826 dev
->irq
= gsc_alloc_irq(&gsc_irq
);
827 dino_dev
->txn_addr
= gsc_irq
.txn_addr
;
828 dino_dev
->txn_data
= gsc_irq
.txn_data
;
829 eim
= ((u32
) gsc_irq
.txn_addr
) | gsc_irq
.txn_data
;
832 ** Dino needs a PA "IRQ" to get a processor's attention.
833 ** arch/parisc/kernel/irq.c returns an EIRR bit.
836 printk(KERN_WARNING
"%s: gsc_alloc_irq() failed\n", name
);
840 status
= request_irq(dev
->irq
, dino_isr
, 0, name
, dino_dev
);
842 printk(KERN_WARNING
"%s: request_irq() failed with %d\n",
847 /* Support the serial port which is sometimes attached on built-in
851 gsc_fixup_irqs(dev
, dino_dev
, dino_choose_irq
);
854 ** This enables DINO to generate interrupts when it sees
855 ** any of its inputs *change*. Just asserting an IRQ
856 ** before it's enabled (ie unmasked) isn't good enough.
858 __raw_writel(eim
, dino_dev
->hba
.base_addr
+DINO_IAR0
);
861 ** Some platforms don't clear Dino's IRR0 register at boot time.
862 ** Reading will clear it now.
864 __raw_readl(dino_dev
->hba
.base_addr
+DINO_IRR0
);
866 /* allocate I/O Port resource region */
867 res
= &dino_dev
->hba
.io_space
;
868 if (!is_cujo(&dev
->id
)) {
869 res
->name
= "Dino I/O Port";
871 res
->name
= "Cujo I/O Port";
873 res
->start
= HBA_PORT_BASE(dino_dev
->hba
.hba_num
);
874 res
->end
= res
->start
+ (HBA_PORT_SPACE_SIZE
- 1);
875 res
->flags
= IORESOURCE_IO
; /* do not mark it busy ! */
876 if (request_resource(&ioport_resource
, res
) < 0) {
877 printk(KERN_ERR
"%s: request I/O Port region failed "
878 "0x%lx/%lx (hpa 0x%p)\n",
879 name
, (unsigned long)res
->start
, (unsigned long)res
->end
,
880 dino_dev
->hba
.base_addr
);
887 #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL)
888 #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL)
889 #define CUJO_RAVEN_BADPAGE 0x01003000UL
890 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL
892 static const char *dino_vers
[] = {
899 static const char *cujo_vers
[] = {
904 void ccio_cujo20_fixup(struct parisc_device
*dev
, u32 iovp
);
907 ** Determine if dino should claim this chip (return 0) or not (return 1).
908 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
909 ** Much of the initialization is common though.
911 static int __init
dino_probe(struct parisc_device
*dev
)
913 struct dino_device
*dino_dev
; // Dino specific control struct
914 const char *version
= "unknown";
917 LIST_HEAD(resources
);
919 unsigned long hpa
= dev
->hpa
.start
;
922 if (is_card_dino(&dev
->id
)) {
923 version
= "3.x (card mode)";
925 if (!is_cujo(&dev
->id
)) {
926 if (dev
->id
.hversion_rev
< 4) {
927 version
= dino_vers
[dev
->id
.hversion_rev
];
932 if (dev
->id
.hversion_rev
< 2) {
933 version
= cujo_vers
[dev
->id
.hversion_rev
];
938 printk("%s version %s found at 0x%lx\n", name
, version
, hpa
);
940 if (!request_mem_region(hpa
, PAGE_SIZE
, name
)) {
941 printk(KERN_ERR
"DINO: Hey! Someone took my MMIO space (0x%ld)!\n",
947 if (is_cujo
&& dev
->id
.hversion_rev
== 1) {
948 #ifdef CONFIG_IOMMU_CCIO
949 printk(KERN_WARNING
"Enabling Cujo 2.0 bug workaround\n");
950 if (hpa
== (unsigned long)CUJO_RAVEN_ADDR
) {
951 ccio_cujo20_fixup(dev
, CUJO_RAVEN_BADPAGE
);
952 } else if (hpa
== (unsigned long)CUJO_FIREHAWK_ADDR
) {
953 ccio_cujo20_fixup(dev
, CUJO_FIREHAWK_BADPAGE
);
955 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa
);
958 } else if (!is_cujo
&& !is_card_dino(&dev
->id
) &&
959 dev
->id
.hversion_rev
< 3) {
961 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
962 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n"
963 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
964 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
965 dev
->id
.hversion_rev
);
966 /* REVISIT: why are C200/C240 listed in the README table but not
967 ** "Models affected"? Could be an omission in the original literature.
971 dino_dev
= kzalloc(sizeof(struct dino_device
), GFP_KERNEL
);
973 printk("dino_init_chip - couldn't alloc dino_device\n");
977 dino_dev
->hba
.dev
= dev
;
978 dino_dev
->hba
.base_addr
= ioremap_nocache(hpa
, 4096);
979 dino_dev
->hba
.lmmio_space_offset
= 0; /* CPU addrs == bus addrs */
980 spin_lock_init(&dino_dev
->dinosaur_pen
);
981 dino_dev
->hba
.iommu
= ccio_get_iommu(dev
);
983 if (is_card_dino(&dev
->id
)) {
984 dino_card_init(dino_dev
);
986 dino_bridge_init(dino_dev
, name
);
989 if (dino_common_init(dev
, dino_dev
, name
))
992 dev
->dev
.platform_data
= dino_dev
;
994 pci_add_resource(&resources
, &dino_dev
->hba
.io_space
);
995 if (dino_dev
->hba
.lmmio_space
.flags
)
996 pci_add_resource(&resources
, &dino_dev
->hba
.lmmio_space
);
997 if (dino_dev
->hba
.elmmio_space
.flags
)
998 pci_add_resource(&resources
, &dino_dev
->hba
.elmmio_space
);
999 if (dino_dev
->hba
.gmmio_space
.flags
)
1000 pci_add_resource(&resources
, &dino_dev
->hba
.gmmio_space
);
1003 ** It's not used to avoid chicken/egg problems
1004 ** with configuration accessor functions.
1006 dino_dev
->hba
.hba_bus
= bus
= pci_create_root_bus(&dev
->dev
,
1007 dino_current_bus
, &dino_cfg_ops
, NULL
, &resources
);
1009 printk(KERN_ERR
"ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
1010 dev_name(&dev
->dev
), dino_current_bus
);
1011 pci_free_resource_list(&resources
);
1012 /* increment the bus number in case of duplicates */
1017 bus
->subordinate
= pci_scan_child_bus(bus
);
1019 /* This code *depends* on scanning being single threaded
1020 * if it isn't, this global bus number count will fail
1022 dino_current_bus
= bus
->subordinate
+ 1;
1023 pci_bus_assign_resources(bus
);
1024 pci_bus_add_devices(bus
);
1029 * Normally, we would just test sversion. But the Elroy PCI adapter has
1030 * the same sversion as Dino, so we have to check hversion as well.
1031 * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1032 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1033 * For card-mode Dino, most machines report an sversion of 9D. But 715
1034 * and 725 firmware misreport it as 0x08080 for no adequately explained
1037 static struct parisc_device_id dino_tbl
[] = {
1038 { HPHW_A_DMA
, HVERSION_REV_ANY_ID
, 0x004, 0x0009D },/* Card-mode Dino */
1039 { HPHW_A_DMA
, HVERSION_REV_ANY_ID
, HVERSION_ANY_ID
, 0x08080 }, /* XXX */
1040 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, 0x680, 0xa }, /* Bridge-mode Dino */
1041 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, 0x682, 0xa }, /* Bridge-mode Cujo */
1042 { HPHW_BRIDGE
, HVERSION_REV_ANY_ID
, 0x05d, 0xa }, /* Dino in a J2240 */
1046 static struct parisc_driver dino_driver
= {
1048 .id_table
= dino_tbl
,
1049 .probe
= dino_probe
,
1053 * One time initialization to let the world know Dino is here.
1054 * This is the only routine which is NOT static.
1055 * Must be called exactly once before pci_init().
1057 int __init
dino_init(void)
1059 register_parisc_driver(&dino_driver
);