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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / scsi / mpt2sas / mpi / mpi2_ioc.h
blob9a925c07a9ec0c6e4f6c13b71b2654efc7099e95
1 /*
2 * Copyright (c) 2000-2011 LSI Corporation.
3 *
4 *
5 * Name: mpi2_ioc.h
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
8 *
9 * mpi2_ioc.h Version: 02.00.19
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
18 * MaxTargets.
19 * Added TotalImageSize field to FWDownload Request.
20 * Added reserved words to FWUpload Request.
21 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
22 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
23 * request and replaced it with
24 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
25 * Replaced the MinReplyQueueDepth field of the IOCFacts
26 * reply with MaxReplyDescriptorPostQueueDepth.
27 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
28 * depth for the Reply Descriptor Post Queue.
29 * Added SASAddress field to Initiator Device Table
30 * Overflow Event data.
31 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
32 * for SAS Initiator Device Status Change Event data.
33 * Modified Reason Code defines for SAS Topology Change
34 * List Event data, including adding a bit for PHY Vacant
35 * status, and adding a mask for the Reason Code.
36 * Added define for
37 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
38 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
39 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
40 * the IOCFacts Reply.
41 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
42 * Moved MPI2_VERSION_UNION to mpi2.h.
43 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
44 * instead of enables, and added SASBroadcastPrimitiveMasks
45 * field.
46 * Added Log Entry Added Event and related structure.
47 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
48 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
49 * Added MaxVolumes and MaxPersistentEntries fields to
50 * IOCFacts reply.
51 * Added ProtocalFlags and IOCCapabilities fields to
52 * MPI2_FW_IMAGE_HEADER.
53 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
54 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
55 * a U16 (from a U32).
56 * Removed extra 's' from EventMasks name.
57 * 06-27-08 02.00.08 Fixed an offset in a comment.
58 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
59 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
60 * renamed MinReplyFrameSize to ReplyFrameSize.
61 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
62 * Added two new RAIDOperation values for Integrated RAID
63 * Operations Status Event data.
64 * Added four new IR Configuration Change List Event data
65 * ReasonCode values.
66 * Added two new ReasonCode defines for SAS Device Status
67 * Change Event data.
68 * Added three new DiscoveryStatus bits for the SAS
69 * Discovery event data.
70 * Added Multiplexing Status Change bit to the PhyStatus
71 * field of the SAS Topology Change List event data.
72 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
73 * BootFlags are now product-specific.
74 * Added defines for the indivdual signature bytes
75 * for MPI2_INIT_IMAGE_FOOTER.
76 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
77 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
78 * define.
79 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
80 * define.
81 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
82 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
83 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
84 * Added two new reason codes for SAS Device Status Change
85 * Event.
86 * Added new event: SAS PHY Counter.
87 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
88 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
89 * Added new product id family for 2208.
90 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
91 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
92 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
93 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
94 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
95 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
96 * Added Host Based Discovery Phy Event data.
97 * Added defines for ProductID Product field
98 * (MPI2_FW_HEADER_PID_).
99 * Modified values for SAS ProductID Family
100 * (MPI2_FW_HEADER_PID_FAMILY_).
101 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
102 * Added PowerManagementControl Request structures and
103 * defines.
104 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
105 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
106 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
107 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
108 * SASNotifyPrimitiveMasks field to
109 * MPI2_EVENT_NOTIFICATION_REQUEST.
110 * Added Temperature Threshold Event.
111 * Added Host Message Event.
112 * Added Send Host Message request and reply.
113 * 05-25-11 02.00.18 For Extended Image Header, added
114 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
115 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
116 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
117 * 08-24-11 02.00.19 Added PhysicalPort field to
118 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
119 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
120 * --------------------------------------------------------------------------
121 */
122
123 #ifndef MPI2_IOC_H
124 #define MPI2_IOC_H
125
126 /*****************************************************************************
127 *
128 * IOC Messages
129 *
130 *****************************************************************************/
131
132 /****************************************************************************
133 * IOCInit message
134 ****************************************************************************/
135
136 /* IOCInit Request message */
137 typedef struct _MPI2_IOC_INIT_REQUEST
138 {
139 U8 WhoInit; /* 0x00 */
140 U8 Reserved1; /* 0x01 */
141 U8 ChainOffset; /* 0x02 */
142 U8 Function; /* 0x03 */
143 U16 Reserved2; /* 0x04 */
144 U8 Reserved3; /* 0x06 */
145 U8 MsgFlags; /* 0x07 */
146 U8 VP_ID; /* 0x08 */
147 U8 VF_ID; /* 0x09 */
148 U16 Reserved4; /* 0x0A */
149 U16 MsgVersion; /* 0x0C */
150 U16 HeaderVersion; /* 0x0E */
151 U32 Reserved5; /* 0x10 */
152 U16 Reserved6; /* 0x14 */
153 U8 Reserved7; /* 0x16 */
154 U8 HostMSIxVectors; /* 0x17 */
155 U16 Reserved8; /* 0x18 */
156 U16 SystemRequestFrameSize; /* 0x1A */
157 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
158 U16 ReplyFreeQueueDepth; /* 0x1E */
159 U32 SenseBufferAddressHigh; /* 0x20 */
160 U32 SystemReplyAddressHigh; /* 0x24 */
161 U64 SystemRequestFrameBaseAddress; /* 0x28 */
162 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
163 U64 ReplyFreeQueueAddress; /* 0x38 */
164 U64 TimeStamp; /* 0x40 */
165 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
166 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
167
168 /* WhoInit values */
169 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
170 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
171 #define MPI2_WHOINIT_ROM_BIOS (0x02)
172 #define MPI2_WHOINIT_PCI_PEER (0x03)
173 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
174 #define MPI2_WHOINIT_MANUFACTURER (0x05)
175
176 /* MsgVersion */
177 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
178 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
179 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
180 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
181
182 /* HeaderVersion */
183 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
184 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
185 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
186 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
187
188 /* minimum depth for the Reply Descriptor Post Queue */
189 #define MPI2_RDPQ_DEPTH_MIN (16)
190
191
192 /* IOCInit Reply message */
193 typedef struct _MPI2_IOC_INIT_REPLY
194 {
195 U8 WhoInit; /* 0x00 */
196 U8 Reserved1; /* 0x01 */
197 U8 MsgLength; /* 0x02 */
198 U8 Function; /* 0x03 */
199 U16 Reserved2; /* 0x04 */
200 U8 Reserved3; /* 0x06 */
201 U8 MsgFlags; /* 0x07 */
202 U8 VP_ID; /* 0x08 */
203 U8 VF_ID; /* 0x09 */
204 U16 Reserved4; /* 0x0A */
205 U16 Reserved5; /* 0x0C */
206 U16 IOCStatus; /* 0x0E */
207 U32 IOCLogInfo; /* 0x10 */
208 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
209 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
210
211
212 /****************************************************************************
213 * IOCFacts message
214 ****************************************************************************/
215
216 /* IOCFacts Request message */
217 typedef struct _MPI2_IOC_FACTS_REQUEST
218 {
219 U16 Reserved1; /* 0x00 */
220 U8 ChainOffset; /* 0x02 */
221 U8 Function; /* 0x03 */
222 U16 Reserved2; /* 0x04 */
223 U8 Reserved3; /* 0x06 */
224 U8 MsgFlags; /* 0x07 */
225 U8 VP_ID; /* 0x08 */
226 U8 VF_ID; /* 0x09 */
227 U16 Reserved4; /* 0x0A */
228 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
229 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
230
231
232 /* IOCFacts Reply message */
233 typedef struct _MPI2_IOC_FACTS_REPLY
234 {
235 U16 MsgVersion; /* 0x00 */
236 U8 MsgLength; /* 0x02 */
237 U8 Function; /* 0x03 */
238 U16 HeaderVersion; /* 0x04 */
239 U8 IOCNumber; /* 0x06 */
240 U8 MsgFlags; /* 0x07 */
241 U8 VP_ID; /* 0x08 */
242 U8 VF_ID; /* 0x09 */
243 U16 Reserved1; /* 0x0A */
244 U16 IOCExceptions; /* 0x0C */
245 U16 IOCStatus; /* 0x0E */
246 U32 IOCLogInfo; /* 0x10 */
247 U8 MaxChainDepth; /* 0x14 */
248 U8 WhoInit; /* 0x15 */
249 U8 NumberOfPorts; /* 0x16 */
250 U8 MaxMSIxVectors; /* 0x17 */
251 U16 RequestCredit; /* 0x18 */
252 U16 ProductID; /* 0x1A */
253 U32 IOCCapabilities; /* 0x1C */
254 MPI2_VERSION_UNION FWVersion; /* 0x20 */
255 U16 IOCRequestFrameSize; /* 0x24 */
256 U16 Reserved3; /* 0x26 */
257 U16 MaxInitiators; /* 0x28 */
258 U16 MaxTargets; /* 0x2A */
259 U16 MaxSasExpanders; /* 0x2C */
260 U16 MaxEnclosures; /* 0x2E */
261 U16 ProtocolFlags; /* 0x30 */
262 U16 HighPriorityCredit; /* 0x32 */
263 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
264 U8 ReplyFrameSize; /* 0x36 */
265 U8 MaxVolumes; /* 0x37 */
266 U16 MaxDevHandle; /* 0x38 */
267 U16 MaxPersistentEntries; /* 0x3A */
268 U16 MinDevHandle; /* 0x3C */
269 U16 Reserved4; /* 0x3E */
270 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
271 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
272
273 /* MsgVersion */
274 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
275 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
276 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
277 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
278
279 /* HeaderVersion */
280 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
281 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
282 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
283 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
284
285 /* IOCExceptions */
286 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
287
288 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
289 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
290 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
291 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
292 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
293
294 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
295 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
296 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
297 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
298 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
299
300 /* defines for WhoInit field are after the IOCInit Request */
301
302 /* ProductID field uses MPI2_FW_HEADER_PID_ */
303
304 /* IOCCapabilities */
305 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
306 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
307 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
308 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
309 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
310 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
311 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
312 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
313 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
314 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
315 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
316 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
317 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
318
319 /* ProtocolFlags */
320 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
321 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
322
323
324 /****************************************************************************
325 * PortFacts message
326 ****************************************************************************/
327
328 /* PortFacts Request message */
329 typedef struct _MPI2_PORT_FACTS_REQUEST
330 {
331 U16 Reserved1; /* 0x00 */
332 U8 ChainOffset; /* 0x02 */
333 U8 Function; /* 0x03 */
334 U16 Reserved2; /* 0x04 */
335 U8 PortNumber; /* 0x06 */
336 U8 MsgFlags; /* 0x07 */
337 U8 VP_ID; /* 0x08 */
338 U8 VF_ID; /* 0x09 */
339 U16 Reserved3; /* 0x0A */
340 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
341 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
342
343 /* PortFacts Reply message */
344 typedef struct _MPI2_PORT_FACTS_REPLY
345 {
346 U16 Reserved1; /* 0x00 */
347 U8 MsgLength; /* 0x02 */
348 U8 Function; /* 0x03 */
349 U16 Reserved2; /* 0x04 */
350 U8 PortNumber; /* 0x06 */
351 U8 MsgFlags; /* 0x07 */
352 U8 VP_ID; /* 0x08 */
353 U8 VF_ID; /* 0x09 */
354 U16 Reserved3; /* 0x0A */
355 U16 Reserved4; /* 0x0C */
356 U16 IOCStatus; /* 0x0E */
357 U32 IOCLogInfo; /* 0x10 */
358 U8 Reserved5; /* 0x14 */
359 U8 PortType; /* 0x15 */
360 U16 Reserved6; /* 0x16 */
361 U16 MaxPostedCmdBuffers; /* 0x18 */
362 U16 Reserved7; /* 0x1A */
363 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
364 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
365
366 /* PortType values */
367 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
368 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
369 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
370 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
371 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
372
373
374 /****************************************************************************
375 * PortEnable message
376 ****************************************************************************/
377
378 /* PortEnable Request message */
379 typedef struct _MPI2_PORT_ENABLE_REQUEST
380 {
381 U16 Reserved1; /* 0x00 */
382 U8 ChainOffset; /* 0x02 */
383 U8 Function; /* 0x03 */
384 U8 Reserved2; /* 0x04 */
385 U8 PortFlags; /* 0x05 */
386 U8 Reserved3; /* 0x06 */
387 U8 MsgFlags; /* 0x07 */
388 U8 VP_ID; /* 0x08 */
389 U8 VF_ID; /* 0x09 */
390 U16 Reserved4; /* 0x0A */
391 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
392 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
393
394
395 /* PortEnable Reply message */
396 typedef struct _MPI2_PORT_ENABLE_REPLY
397 {
398 U16 Reserved1; /* 0x00 */
399 U8 MsgLength; /* 0x02 */
400 U8 Function; /* 0x03 */
401 U8 Reserved2; /* 0x04 */
402 U8 PortFlags; /* 0x05 */
403 U8 Reserved3; /* 0x06 */
404 U8 MsgFlags; /* 0x07 */
405 U8 VP_ID; /* 0x08 */
406 U8 VF_ID; /* 0x09 */
407 U16 Reserved4; /* 0x0A */
408 U16 Reserved5; /* 0x0C */
409 U16 IOCStatus; /* 0x0E */
410 U32 IOCLogInfo; /* 0x10 */
411 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
412 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
413
414
415 /****************************************************************************
416 * EventNotification message
417 ****************************************************************************/
418
419 /* EventNotification Request message */
420 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
421
422 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
423 {
424 U16 Reserved1; /* 0x00 */
425 U8 ChainOffset; /* 0x02 */
426 U8 Function; /* 0x03 */
427 U16 Reserved2; /* 0x04 */
428 U8 Reserved3; /* 0x06 */
429 U8 MsgFlags; /* 0x07 */
430 U8 VP_ID; /* 0x08 */
431 U8 VF_ID; /* 0x09 */
432 U16 Reserved4; /* 0x0A */
433 U32 Reserved5; /* 0x0C */
434 U32 Reserved6; /* 0x10 */
435 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
436 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
437 U16 SASNotifyPrimitiveMasks; /* 0x26 */
438 U32 Reserved8; /* 0x28 */
439 } MPI2_EVENT_NOTIFICATION_REQUEST,
440 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
441 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
442
443
444 /* EventNotification Reply message */
445 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
446 {
447 U16 EventDataLength; /* 0x00 */
448 U8 MsgLength; /* 0x02 */
449 U8 Function; /* 0x03 */
450 U16 Reserved1; /* 0x04 */
451 U8 AckRequired; /* 0x06 */
452 U8 MsgFlags; /* 0x07 */
453 U8 VP_ID; /* 0x08 */
454 U8 VF_ID; /* 0x09 */
455 U16 Reserved2; /* 0x0A */
456 U16 Reserved3; /* 0x0C */
457 U16 IOCStatus; /* 0x0E */
458 U32 IOCLogInfo; /* 0x10 */
459 U16 Event; /* 0x14 */
460 U16 Reserved4; /* 0x16 */
461 U32 EventContext; /* 0x18 */
462 U32 EventData[1]; /* 0x1C */
463 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
464 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
465
466 /* AckRequired */
467 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
468 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
469
470 /* Event */
471 #define MPI2_EVENT_LOG_DATA (0x0001)
472 #define MPI2_EVENT_STATE_CHANGE (0x0002)
473 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
474 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
475 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
476 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
477 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
478 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
479 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
480 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
481 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
482 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
483 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
484 #define MPI2_EVENT_IR_VOLUME (0x001E)
485 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
486 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
487 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
488 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
489 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
490 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
491 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
492 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
493 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
494 #define MPI2_EVENT_HOST_MESSAGE (0x0028)
495
496
497 /* Log Entry Added Event data */
498
499 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
500 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
501
502 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
503 {
504 U64 TimeStamp; /* 0x00 */
505 U32 Reserved1; /* 0x08 */
506 U16 LogSequence; /* 0x0C */
507 U16 LogEntryQualifier; /* 0x0E */
508 U8 VP_ID; /* 0x10 */
509 U8 VF_ID; /* 0x11 */
510 U16 Reserved2; /* 0x12 */
511 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
512 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
513 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
514 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
515
516 /* GPIO Interrupt Event data */
517
518 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
519 U8 GPIONum; /* 0x00 */
520 U8 Reserved1; /* 0x01 */
521 U16 Reserved2; /* 0x02 */
522 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
523 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
524 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
525
526 /* Temperature Threshold Event data */
527
528 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
529 U16 Status; /* 0x00 */
530 U8 SensorNum; /* 0x02 */
531 U8 Reserved1; /* 0x03 */
532 U16 CurrentTemperature; /* 0x04 */
533 U16 Reserved2; /* 0x06 */
534 U32 Reserved3; /* 0x08 */
535 U32 Reserved4; /* 0x0C */
536 } MPI2_EVENT_DATA_TEMPERATURE,
537 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
538 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
539
540 /* Temperature Threshold Event data Status bits */
541 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
542 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
543 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
544 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
545
546
547 /* Host Message Event data */
548
549 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
550 U8 SourceVF_ID; /* 0x00 */
551 U8 Reserved1; /* 0x01 */
552 U16 Reserved2; /* 0x02 */
553 U32 Reserved3; /* 0x04 */
554 U32 HostData[1]; /* 0x08 */
555 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
556 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
557
558
559 /* Hard Reset Received Event data */
560
561 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
562 {
563 U8 Reserved1; /* 0x00 */
564 U8 Port; /* 0x01 */
565 U16 Reserved2; /* 0x02 */
566 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
567 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
568 Mpi2EventDataHardResetReceived_t,
569 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
570
571 /* Task Set Full Event data */
572 /* this event is obsolete */
573
574 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
575 {
576 U16 DevHandle; /* 0x00 */
577 U16 CurrentDepth; /* 0x02 */
578 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
579 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
580
581
582 /* SAS Device Status Change Event data */
583
584 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
585 {
586 U16 TaskTag; /* 0x00 */
587 U8 ReasonCode; /* 0x02 */
588 U8 PhysicalPort; /* 0x03 */
589 U8 ASC; /* 0x04 */
590 U8 ASCQ; /* 0x05 */
591 U16 DevHandle; /* 0x06 */
592 U32 Reserved2; /* 0x08 */
593 U64 SASAddress; /* 0x0C */
594 U8 LUN[8]; /* 0x14 */
595 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
596 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
597 Mpi2EventDataSasDeviceStatusChange_t,
598 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
599
600 /* SAS Device Status Change Event data ReasonCode values */
601 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
602 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
603 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
604 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
605 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
606 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
607 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
608 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
609 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
610 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
611 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
612 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
613 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
614
615
616 /* Integrated RAID Operation Status Event data */
617
618 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
619 {
620 U16 VolDevHandle; /* 0x00 */
621 U16 Reserved1; /* 0x02 */
622 U8 RAIDOperation; /* 0x04 */
623 U8 PercentComplete; /* 0x05 */
624 U16 Reserved2; /* 0x06 */
625 U32 Resereved3; /* 0x08 */
626 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
627 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
628 Mpi2EventDataIrOperationStatus_t,
629 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
630
631 /* Integrated RAID Operation Status Event data RAIDOperation values */
632 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
633 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
634 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
635 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
636 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
637
638
639 /* Integrated RAID Volume Event data */
640
641 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
642 {
643 U16 VolDevHandle; /* 0x00 */
644 U8 ReasonCode; /* 0x02 */
645 U8 Reserved1; /* 0x03 */
646 U32 NewValue; /* 0x04 */
647 U32 PreviousValue; /* 0x08 */
648 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
649 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
650
651 /* Integrated RAID Volume Event data ReasonCode values */
652 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
653 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
654 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
655
656
657 /* Integrated RAID Physical Disk Event data */
658
659 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
660 {
661 U16 Reserved1; /* 0x00 */
662 U8 ReasonCode; /* 0x02 */
663 U8 PhysDiskNum; /* 0x03 */
664 U16 PhysDiskDevHandle; /* 0x04 */
665 U16 Reserved2; /* 0x06 */
666 U16 Slot; /* 0x08 */
667 U16 EnclosureHandle; /* 0x0A */
668 U32 NewValue; /* 0x0C */
669 U32 PreviousValue; /* 0x10 */
670 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
671 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
672 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
673
674 /* Integrated RAID Physical Disk Event data ReasonCode values */
675 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
676 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
677 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
678
679
680 /* Integrated RAID Configuration Change List Event data */
681
682 /*
683 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
684 * one and check NumElements at runtime.
685 */
686 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
687 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
688 #endif
689
690 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
691 {
692 U16 ElementFlags; /* 0x00 */
693 U16 VolDevHandle; /* 0x02 */
694 U8 ReasonCode; /* 0x04 */
695 U8 PhysDiskNum; /* 0x05 */
696 U16 PhysDiskDevHandle; /* 0x06 */
697 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
698 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
699
700 /* IR Configuration Change List Event data ElementFlags values */
701 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
702 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
703 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
704 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
705
706 /* IR Configuration Change List Event data ReasonCode values */
707 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
708 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
709 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
710 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
711 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
712 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
713 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
714 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
715 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
716
717 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
718 {
719 U8 NumElements; /* 0x00 */
720 U8 Reserved1; /* 0x01 */
721 U8 Reserved2; /* 0x02 */
722 U8 ConfigNum; /* 0x03 */
723 U32 Flags; /* 0x04 */
724 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
725 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
726 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
727 Mpi2EventDataIrConfigChangeList_t,
728 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
729
730 /* IR Configuration Change List Event data Flags values */
731 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
732
733
734 /* SAS Discovery Event data */
735
736 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
737 {
738 U8 Flags; /* 0x00 */
739 U8 ReasonCode; /* 0x01 */
740 U8 PhysicalPort; /* 0x02 */
741 U8 Reserved1; /* 0x03 */
742 U32 DiscoveryStatus; /* 0x04 */
743 } MPI2_EVENT_DATA_SAS_DISCOVERY,
744 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
745 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
746
747 /* SAS Discovery Event data Flags values */
748 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
749 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
750
751 /* SAS Discovery Event data ReasonCode values */
752 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
753 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
754
755 /* SAS Discovery Event data DiscoveryStatus values */
756 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
757 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
758 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
759 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
760 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
761 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
762 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
763 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
764 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
765 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
766 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
767 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
768 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
769 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
770 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
771 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
772 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
773 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
774 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
775 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
776
777
778 /* SAS Broadcast Primitive Event data */
779
780 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
781 {
782 U8 PhyNum; /* 0x00 */
783 U8 Port; /* 0x01 */
784 U8 PortWidth; /* 0x02 */
785 U8 Primitive; /* 0x03 */
786 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
787 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
788 Mpi2EventDataSasBroadcastPrimitive_t,
789 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
790
791 /* defines for the Primitive field */
792 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
793 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
794 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
795 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
796 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
797 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
798 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
799 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
800
801 /* SAS Notify Primitive Event data */
802
803 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
804 U8 PhyNum; /* 0x00 */
805 U8 Port; /* 0x01 */
806 U8 Reserved1; /* 0x02 */
807 U8 Primitive; /* 0x03 */
808 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
809 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
810 Mpi2EventDataSasNotifyPrimitive_t,
811 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
812
813 /* defines for the Primitive field */
814 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
815 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
816 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
817 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
818
819
820 /* SAS Initiator Device Status Change Event data */
821
822 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
823 {
824 U8 ReasonCode; /* 0x00 */
825 U8 PhysicalPort; /* 0x01 */
826 U16 DevHandle; /* 0x02 */
827 U64 SASAddress; /* 0x04 */
828 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
829 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
830 Mpi2EventDataSasInitDevStatusChange_t,
831 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
832
833 /* SAS Initiator Device Status Change event ReasonCode values */
834 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
835 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
836
837
838 /* SAS Initiator Device Table Overflow Event data */
839
840 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
841 {
842 U16 MaxInit; /* 0x00 */
843 U16 CurrentInit; /* 0x02 */
844 U64 SASAddress; /* 0x04 */
845 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
846 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
847 Mpi2EventDataSasInitTableOverflow_t,
848 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
849
850
851 /* SAS Topology Change List Event data */
852
853 /*
854 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
855 * one and check NumEntries at runtime.
856 */
857 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
858 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
859 #endif
860
861 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
862 {
863 U16 AttachedDevHandle; /* 0x00 */
864 U8 LinkRate; /* 0x02 */
865 U8 PhyStatus; /* 0x03 */
866 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
867 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
868
869 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
870 {
871 U16 EnclosureHandle; /* 0x00 */
872 U16 ExpanderDevHandle; /* 0x02 */
873 U8 NumPhys; /* 0x04 */
874 U8 Reserved1; /* 0x05 */
875 U16 Reserved2; /* 0x06 */
876 U8 NumEntries; /* 0x08 */
877 U8 StartPhyNum; /* 0x09 */
878 U8 ExpStatus; /* 0x0A */
879 U8 PhysicalPort; /* 0x0B */
880 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
881 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
882 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
883 Mpi2EventDataSasTopologyChangeList_t,
884 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
885
886 /* values for the ExpStatus field */
887 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
888 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
889 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
890 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
891 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
892
893 /* defines for the LinkRate field */
894 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
895 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
896 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
897 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
898
899 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
900 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
901 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
902 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
903 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
904 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
905 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
906 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
907 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
908 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
909
910 /* values for the PhyStatus field */
911 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
912 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
913 /* values for the PhyStatus ReasonCode sub-field */
914 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
915 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
916 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
917 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
918 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
919 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
920
921
922 /* SAS Enclosure Device Status Change Event data */
923
924 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
925 {
926 U16 EnclosureHandle; /* 0x00 */
927 U8 ReasonCode; /* 0x02 */
928 U8 PhysicalPort; /* 0x03 */
929 U64 EnclosureLogicalID; /* 0x04 */
930 U16 NumSlots; /* 0x0C */
931 U16 StartSlot; /* 0x0E */
932 U32 PhyBits; /* 0x10 */
933 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
934 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
935 Mpi2EventDataSasEnclDevStatusChange_t,
936 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
937
938 /* SAS Enclosure Device Status Change event ReasonCode values */
939 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
940 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
941
942
943 /* SAS PHY Counter Event data */
944
945 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
946 U64 TimeStamp; /* 0x00 */
947 U32 Reserved1; /* 0x08 */
948 U8 PhyEventCode; /* 0x0C */
949 U8 PhyNum; /* 0x0D */
950 U16 Reserved2; /* 0x0E */
951 U32 PhyEventInfo; /* 0x10 */
952 U8 CounterType; /* 0x14 */
953 U8 ThresholdWindow; /* 0x15 */
954 U8 TimeUnits; /* 0x16 */
955 U8 Reserved3; /* 0x17 */
956 U32 EventThreshold; /* 0x18 */
957 U16 ThresholdFlags; /* 0x1C */
958 U16 Reserved4; /* 0x1E */
959 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
960 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
961 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
962
963 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
964 * PhyEventCode field
965 * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
966 * CounterType field
967 * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
968 * TimeUnits field
969 * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
970 * ThresholdFlags field
971 * */
972
973
974 /* SAS Quiesce Event data */
975
976 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
977 U8 ReasonCode; /* 0x00 */
978 U8 Reserved1; /* 0x01 */
979 U16 Reserved2; /* 0x02 */
980 U32 Reserved3; /* 0x04 */
981 } MPI2_EVENT_DATA_SAS_QUIESCE,
982 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
983 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
984
985 /* SAS Quiesce Event data ReasonCode values */
986 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
987 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
988
989
990 /* Host Based Discovery Phy Event data */
991
992 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
993 U8 Flags; /* 0x00 */
994 U8 NegotiatedLinkRate; /* 0x01 */
995 U8 PhyNum; /* 0x02 */
996 U8 PhysicalPort; /* 0x03 */
997 U32 Reserved1; /* 0x04 */
998 U8 InitialFrame[28]; /* 0x08 */
999 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
1000 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
1001
1002 /* values for the Flags field */
1003 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1004 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1005
1006 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
1007 * the NegotiatedLinkRate field */
1008
1009 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1010 MPI2_EVENT_HBD_PHY_SAS Sas;
1011 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1012 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1013
1014 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1015 U8 DescriptorType; /* 0x00 */
1016 U8 Reserved1; /* 0x01 */
1017 U16 Reserved2; /* 0x02 */
1018 U32 Reserved3; /* 0x04 */
1019 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1020 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1021 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1022
1023 /* values for the DescriptorType field */
1024 #define MPI2_EVENT_HBD_DT_SAS (0x01)
1025
1026
1027
1028 /****************************************************************************
1029 * EventAck message
1030 ****************************************************************************/
1031
1032 /* EventAck Request message */
1033 typedef struct _MPI2_EVENT_ACK_REQUEST
1034 {
1035 U16 Reserved1; /* 0x00 */
1036 U8 ChainOffset; /* 0x02 */
1037 U8 Function; /* 0x03 */
1038 U16 Reserved2; /* 0x04 */
1039 U8 Reserved3; /* 0x06 */
1040 U8 MsgFlags; /* 0x07 */
1041 U8 VP_ID; /* 0x08 */
1042 U8 VF_ID; /* 0x09 */
1043 U16 Reserved4; /* 0x0A */
1044 U16 Event; /* 0x0C */
1045 U16 Reserved5; /* 0x0E */
1046 U32 EventContext; /* 0x10 */
1047 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1048 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1049
1050
1051 /* EventAck Reply message */
1052 typedef struct _MPI2_EVENT_ACK_REPLY
1053 {
1054 U16 Reserved1; /* 0x00 */
1055 U8 MsgLength; /* 0x02 */
1056 U8 Function; /* 0x03 */
1057 U16 Reserved2; /* 0x04 */
1058 U8 Reserved3; /* 0x06 */
1059 U8 MsgFlags; /* 0x07 */
1060 U8 VP_ID; /* 0x08 */
1061 U8 VF_ID; /* 0x09 */
1062 U16 Reserved4; /* 0x0A */
1063 U16 Reserved5; /* 0x0C */
1064 U16 IOCStatus; /* 0x0E */
1065 U32 IOCLogInfo; /* 0x10 */
1066 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1067 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1068
1069
1070 /****************************************************************************
1071 * SendHostMessage message
1072 ****************************************************************************/
1073
1074 /* SendHostMessage Request message */
1075 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1076 U16 HostDataLength; /* 0x00 */
1077 U8 ChainOffset; /* 0x02 */
1078 U8 Function; /* 0x03 */
1079 U16 Reserved1; /* 0x04 */
1080 U8 Reserved2; /* 0x06 */
1081 U8 MsgFlags; /* 0x07 */
1082 U8 VP_ID; /* 0x08 */
1083 U8 VF_ID; /* 0x09 */
1084 U16 Reserved3; /* 0x0A */
1085 U8 Reserved4; /* 0x0C */
1086 U8 DestVF_ID; /* 0x0D */
1087 U16 Reserved5; /* 0x0E */
1088 U32 Reserved6; /* 0x10 */
1089 U32 Reserved7; /* 0x14 */
1090 U32 Reserved8; /* 0x18 */
1091 U32 Reserved9; /* 0x1C */
1092 U32 Reserved10; /* 0x20 */
1093 U32 HostData[1]; /* 0x24 */
1094 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1095 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1096 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1097
1098
1099 /* SendHostMessage Reply message */
1100 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1101 U16 HostDataLength; /* 0x00 */
1102 U8 MsgLength; /* 0x02 */
1103 U8 Function; /* 0x03 */
1104 U16 Reserved1; /* 0x04 */
1105 U8 Reserved2; /* 0x06 */
1106 U8 MsgFlags; /* 0x07 */
1107 U8 VP_ID; /* 0x08 */
1108 U8 VF_ID; /* 0x09 */
1109 U16 Reserved3; /* 0x0A */
1110 U16 Reserved4; /* 0x0C */
1111 U16 IOCStatus; /* 0x0E */
1112 U32 IOCLogInfo; /* 0x10 */
1113 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1114 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1115
1116
1117 /****************************************************************************
1118 * FWDownload message
1119 ****************************************************************************/
1120
1121 /* FWDownload Request message */
1122 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1123 {
1124 U8 ImageType; /* 0x00 */
1125 U8 Reserved1; /* 0x01 */
1126 U8 ChainOffset; /* 0x02 */
1127 U8 Function; /* 0x03 */
1128 U16 Reserved2; /* 0x04 */
1129 U8 Reserved3; /* 0x06 */
1130 U8 MsgFlags; /* 0x07 */
1131 U8 VP_ID; /* 0x08 */
1132 U8 VF_ID; /* 0x09 */
1133 U16 Reserved4; /* 0x0A */
1134 U32 TotalImageSize; /* 0x0C */
1135 U32 Reserved5; /* 0x10 */
1136 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1137 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1138 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1139
1140 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1141
1142 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1143 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1144 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1145 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1146 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1147 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1148 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1149 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1150 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1151
1152 /* FWDownload TransactionContext Element */
1153 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1154 {
1155 U8 Reserved1; /* 0x00 */
1156 U8 ContextSize; /* 0x01 */
1157 U8 DetailsLength; /* 0x02 */
1158 U8 Flags; /* 0x03 */
1159 U32 Reserved2; /* 0x04 */
1160 U32 ImageOffset; /* 0x08 */
1161 U32 ImageSize; /* 0x0C */
1162 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1163 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1164
1165 /* FWDownload Reply message */
1166 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1167 {
1168 U8 ImageType; /* 0x00 */
1169 U8 Reserved1; /* 0x01 */
1170 U8 MsgLength; /* 0x02 */
1171 U8 Function; /* 0x03 */
1172 U16 Reserved2; /* 0x04 */
1173 U8 Reserved3; /* 0x06 */
1174 U8 MsgFlags; /* 0x07 */
1175 U8 VP_ID; /* 0x08 */
1176 U8 VF_ID; /* 0x09 */
1177 U16 Reserved4; /* 0x0A */
1178 U16 Reserved5; /* 0x0C */
1179 U16 IOCStatus; /* 0x0E */
1180 U32 IOCLogInfo; /* 0x10 */
1181 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1182 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1183
1184
1185 /****************************************************************************
1186 * FWUpload message
1187 ****************************************************************************/
1188
1189 /* FWUpload Request message */
1190 typedef struct _MPI2_FW_UPLOAD_REQUEST
1191 {
1192 U8 ImageType; /* 0x00 */
1193 U8 Reserved1; /* 0x01 */
1194 U8 ChainOffset; /* 0x02 */
1195 U8 Function; /* 0x03 */
1196 U16 Reserved2; /* 0x04 */
1197 U8 Reserved3; /* 0x06 */
1198 U8 MsgFlags; /* 0x07 */
1199 U8 VP_ID; /* 0x08 */
1200 U8 VF_ID; /* 0x09 */
1201 U16 Reserved4; /* 0x0A */
1202 U32 Reserved5; /* 0x0C */
1203 U32 Reserved6; /* 0x10 */
1204 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1205 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1206 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1207
1208 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1209 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1210 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1211 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1212 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1213 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1214 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1215 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1216 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1217 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1218
1219 typedef struct _MPI2_FW_UPLOAD_TCSGE
1220 {
1221 U8 Reserved1; /* 0x00 */
1222 U8 ContextSize; /* 0x01 */
1223 U8 DetailsLength; /* 0x02 */
1224 U8 Flags; /* 0x03 */
1225 U32 Reserved2; /* 0x04 */
1226 U32 ImageOffset; /* 0x08 */
1227 U32 ImageSize; /* 0x0C */
1228 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1229 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1230
1231 /* FWUpload Reply message */
1232 typedef struct _MPI2_FW_UPLOAD_REPLY
1233 {
1234 U8 ImageType; /* 0x00 */
1235 U8 Reserved1; /* 0x01 */
1236 U8 MsgLength; /* 0x02 */
1237 U8 Function; /* 0x03 */
1238 U16 Reserved2; /* 0x04 */
1239 U8 Reserved3; /* 0x06 */
1240 U8 MsgFlags; /* 0x07 */
1241 U8 VP_ID; /* 0x08 */
1242 U8 VF_ID; /* 0x09 */
1243 U16 Reserved4; /* 0x0A */
1244 U16 Reserved5; /* 0x0C */
1245 U16 IOCStatus; /* 0x0E */
1246 U32 IOCLogInfo; /* 0x10 */
1247 U32 ActualImageSize; /* 0x14 */
1248 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1249 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1250
1251
1252 /* FW Image Header */
1253 typedef struct _MPI2_FW_IMAGE_HEADER
1254 {
1255 U32 Signature; /* 0x00 */
1256 U32 Signature0; /* 0x04 */
1257 U32 Signature1; /* 0x08 */
1258 U32 Signature2; /* 0x0C */
1259 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1260 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1261 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1262 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1263 U16 VendorID; /* 0x20 */
1264 U16 ProductID; /* 0x22 */
1265 U16 ProtocolFlags; /* 0x24 */
1266 U16 Reserved26; /* 0x26 */
1267 U32 IOCCapabilities; /* 0x28 */
1268 U32 ImageSize; /* 0x2C */
1269 U32 NextImageHeaderOffset; /* 0x30 */
1270 U32 Checksum; /* 0x34 */
1271 U32 Reserved38; /* 0x38 */
1272 U32 Reserved3C; /* 0x3C */
1273 U32 Reserved40; /* 0x40 */
1274 U32 Reserved44; /* 0x44 */
1275 U32 Reserved48; /* 0x48 */
1276 U32 Reserved4C; /* 0x4C */
1277 U32 Reserved50; /* 0x50 */
1278 U32 Reserved54; /* 0x54 */
1279 U32 Reserved58; /* 0x58 */
1280 U32 Reserved5C; /* 0x5C */
1281 U32 Reserved60; /* 0x60 */
1282 U32 FirmwareVersionNameWhat; /* 0x64 */
1283 U8 FirmwareVersionName[32]; /* 0x68 */
1284 U32 VendorNameWhat; /* 0x88 */
1285 U8 VendorName[32]; /* 0x8C */
1286 U32 PackageNameWhat; /* 0x88 */
1287 U8 PackageName[32]; /* 0x8C */
1288 U32 ReservedD0; /* 0xD0 */
1289 U32 ReservedD4; /* 0xD4 */
1290 U32 ReservedD8; /* 0xD8 */
1291 U32 ReservedDC; /* 0xDC */
1292 U32 ReservedE0; /* 0xE0 */
1293 U32 ReservedE4; /* 0xE4 */
1294 U32 ReservedE8; /* 0xE8 */
1295 U32 ReservedEC; /* 0xEC */
1296 U32 ReservedF0; /* 0xF0 */
1297 U32 ReservedF4; /* 0xF4 */
1298 U32 ReservedF8; /* 0xF8 */
1299 U32 ReservedFC; /* 0xFC */
1300 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1301 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1302
1303 /* Signature field */
1304 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1305 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1306 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1307
1308 /* Signature0 field */
1309 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1310 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1311
1312 /* Signature1 field */
1313 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1314 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1315
1316 /* Signature2 field */
1317 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1318 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1319
1320
1321 /* defines for using the ProductID field */
1322 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1323 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1324
1325 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1326 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1327 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1328 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1329
1330
1331 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1332 /* SAS */
1333 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1334 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1335
1336 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1337
1338 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1339
1340
1341 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1342 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1343 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1344
1345 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1346
1347 #define MPI2_FW_HEADER_SIZE (0x100)
1348
1349
1350 /* Extended Image Header */
1351 typedef struct _MPI2_EXT_IMAGE_HEADER
1352
1353 {
1354 U8 ImageType; /* 0x00 */
1355 U8 Reserved1; /* 0x01 */
1356 U16 Reserved2; /* 0x02 */
1357 U32 Checksum; /* 0x04 */
1358 U32 ImageSize; /* 0x08 */
1359 U32 NextImageHeaderOffset; /* 0x0C */
1360 U32 PackageVersion; /* 0x10 */
1361 U32 Reserved3; /* 0x14 */
1362 U32 Reserved4; /* 0x18 */
1363 U32 Reserved5; /* 0x1C */
1364 U8 IdentifyString[32]; /* 0x20 */
1365 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1366 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1367
1368 /* useful offsets */
1369 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1370 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1371 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1372
1373 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1374
1375 /* defines for the ImageType field */
1376 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1377 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1378 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1379 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1380 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1381 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1382 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1383 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1384 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1385 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1386 #define MPI2_EXT_IMAGE_TYPE_MAX \
1387 (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */
1388
1389
1390
1391 /* FLASH Layout Extended Image Data */
1392
1393 /*
1394 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1395 * one and check RegionsPerLayout at runtime.
1396 */
1397 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1398 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1399 #endif
1400
1401 /*
1402 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1403 * one and check NumberOfLayouts at runtime.
1404 */
1405 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1406 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1407 #endif
1408
1409 typedef struct _MPI2_FLASH_REGION
1410 {
1411 U8 RegionType; /* 0x00 */
1412 U8 Reserved1; /* 0x01 */
1413 U16 Reserved2; /* 0x02 */
1414 U32 RegionOffset; /* 0x04 */
1415 U32 RegionSize; /* 0x08 */
1416 U32 Reserved3; /* 0x0C */
1417 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1418 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1419
1420 typedef struct _MPI2_FLASH_LAYOUT
1421 {
1422 U32 FlashSize; /* 0x00 */
1423 U32 Reserved1; /* 0x04 */
1424 U32 Reserved2; /* 0x08 */
1425 U32 Reserved3; /* 0x0C */
1426 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1427 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1428 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1429
1430 typedef struct _MPI2_FLASH_LAYOUT_DATA
1431 {
1432 U8 ImageRevision; /* 0x00 */
1433 U8 Reserved1; /* 0x01 */
1434 U8 SizeOfRegion; /* 0x02 */
1435 U8 Reserved2; /* 0x03 */
1436 U16 NumberOfLayouts; /* 0x04 */
1437 U16 RegionsPerLayout; /* 0x06 */
1438 U16 MinimumSectorAlignment; /* 0x08 */
1439 U16 Reserved3; /* 0x0A */
1440 U32 Reserved4; /* 0x0C */
1441 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1442 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1443 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1444
1445 /* defines for the RegionType field */
1446 #define MPI2_FLASH_REGION_UNUSED (0x00)
1447 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1448 #define MPI2_FLASH_REGION_BIOS (0x02)
1449 #define MPI2_FLASH_REGION_NVDATA (0x03)
1450 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1451 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1452 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1453 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1454 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1455 #define MPI2_FLASH_REGION_INIT (0x0A)
1456
1457 /* ImageRevision */
1458 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1459
1460
1461
1462 /* Supported Devices Extended Image Data */
1463
1464 /*
1465 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1466 * one and check NumberOfDevices at runtime.
1467 */
1468 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1469 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1470 #endif
1471
1472 typedef struct _MPI2_SUPPORTED_DEVICE
1473 {
1474 U16 DeviceID; /* 0x00 */
1475 U16 VendorID; /* 0x02 */
1476 U16 DeviceIDMask; /* 0x04 */
1477 U16 Reserved1; /* 0x06 */
1478 U8 LowPCIRev; /* 0x08 */
1479 U8 HighPCIRev; /* 0x09 */
1480 U16 Reserved2; /* 0x0A */
1481 U32 Reserved3; /* 0x0C */
1482 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1483 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1484
1485 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1486 {
1487 U8 ImageRevision; /* 0x00 */
1488 U8 Reserved1; /* 0x01 */
1489 U8 NumberOfDevices; /* 0x02 */
1490 U8 Reserved2; /* 0x03 */
1491 U32 Reserved3; /* 0x04 */
1492 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1493 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1494 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1495
1496 /* ImageRevision */
1497 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1498
1499
1500 /* Init Extended Image Data */
1501
1502 typedef struct _MPI2_INIT_IMAGE_FOOTER
1503
1504 {
1505 U32 BootFlags; /* 0x00 */
1506 U32 ImageSize; /* 0x04 */
1507 U32 Signature0; /* 0x08 */
1508 U32 Signature1; /* 0x0C */
1509 U32 Signature2; /* 0x10 */
1510 U32 ResetVector; /* 0x14 */
1511 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1512 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1513
1514 /* defines for the BootFlags field */
1515 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1516
1517 /* defines for the ImageSize field */
1518 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1519
1520 /* defines for the Signature0 field */
1521 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1522 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1523
1524 /* defines for the Signature1 field */
1525 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1526 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1527
1528 /* defines for the Signature2 field */
1529 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1530 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1531
1532 /* Signature fields as individual bytes */
1533 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1534 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1535 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1536 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1537
1538 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1539 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1540 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1541 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1542
1543 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1544 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1545 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1546 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1547
1548 /* defines for the ResetVector field */
1549 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1550
1551
1552 /****************************************************************************
1553 * PowerManagementControl message
1554 ****************************************************************************/
1555
1556 /* PowerManagementControl Request message */
1557 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1558 U8 Feature; /* 0x00 */
1559 U8 Reserved1; /* 0x01 */
1560 U8 ChainOffset; /* 0x02 */
1561 U8 Function; /* 0x03 */
1562 U16 Reserved2; /* 0x04 */
1563 U8 Reserved3; /* 0x06 */
1564 U8 MsgFlags; /* 0x07 */
1565 U8 VP_ID; /* 0x08 */
1566 U8 VF_ID; /* 0x09 */
1567 U16 Reserved4; /* 0x0A */
1568 U8 Parameter1; /* 0x0C */
1569 U8 Parameter2; /* 0x0D */
1570 U8 Parameter3; /* 0x0E */
1571 U8 Parameter4; /* 0x0F */
1572 U32 Reserved5; /* 0x10 */
1573 U32 Reserved6; /* 0x14 */
1574 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1575 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1576
1577 /* defines for the Feature field */
1578 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1579 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1580 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */
1581 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1582 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1583 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1584
1585 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1586 /* Parameter1 contains a PHY number */
1587 /* Parameter2 indicates power condition action using these defines */
1588 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1589 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1590 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1591 /* Parameter3 and Parameter4 are reserved */
1592
1593 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1594 * Feature */
1595 /* Parameter1 contains SAS port width modulation group number */
1596 /* Parameter2 indicates IOC action using these defines */
1597 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1598 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1599 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1600 /* Parameter3 indicates desired modulation level using these defines */
1601 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1602 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1603 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1604 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1605 /* Parameter4 is reserved */
1606
1607 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1608 /* Parameter1 indicates desired PCIe link speed using these defines */
1609 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */
1610 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */
1611 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */
1612 /* Parameter2 indicates desired PCIe link width using these defines */
1613 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */
1614 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */
1615 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */
1616 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */
1617 /* Parameter3 and Parameter4 are reserved */
1618
1619 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1620 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1621 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1622 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1623 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1624 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1625 /* Parameter2, Parameter3, and Parameter4 are reserved */
1626
1627
1628 /* PowerManagementControl Reply message */
1629 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1630 U8 Feature; /* 0x00 */
1631 U8 Reserved1; /* 0x01 */
1632 U8 MsgLength; /* 0x02 */
1633 U8 Function; /* 0x03 */
1634 U16 Reserved2; /* 0x04 */
1635 U8 Reserved3; /* 0x06 */
1636 U8 MsgFlags; /* 0x07 */
1637 U8 VP_ID; /* 0x08 */
1638 U8 VF_ID; /* 0x09 */
1639 U16 Reserved4; /* 0x0A */
1640 U16 Reserved5; /* 0x0C */
1641 U16 IOCStatus; /* 0x0E */
1642 U32 IOCLogInfo; /* 0x10 */
1643 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1644 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1645
1646
1647 #endif
1648