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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / scsi / qla2xxx / qla_def.h
blobaf1003f9de1e44debaf0dda711e36f6d834b663c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35
36 #include "qla_bsg.h"
37 #include "qla_nx.h"
38 #define QLA2XXX_DRIVER_NAME "qla2xxx"
39 #define QLA2XXX_APIDEV "ql2xapidev"
40
41 /*
42 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
43 * but that's fine as we don't look at the last 24 ones for
44 * ISP2100 HBAs.
45 */
46 #define MAILBOX_REGISTER_COUNT_2100 8
47 #define MAILBOX_REGISTER_COUNT_2200 24
48 #define MAILBOX_REGISTER_COUNT 32
49
50 #define QLA2200A_RISC_ROM_VER 4
51 #define FPM_2300 6
52 #define FPM_2310 7
53
54 #include "qla_settings.h"
55
56 /*
57 * Data bit definitions
58 */
59 #define BIT_0 0x1
60 #define BIT_1 0x2
61 #define BIT_2 0x4
62 #define BIT_3 0x8
63 #define BIT_4 0x10
64 #define BIT_5 0x20
65 #define BIT_6 0x40
66 #define BIT_7 0x80
67 #define BIT_8 0x100
68 #define BIT_9 0x200
69 #define BIT_10 0x400
70 #define BIT_11 0x800
71 #define BIT_12 0x1000
72 #define BIT_13 0x2000
73 #define BIT_14 0x4000
74 #define BIT_15 0x8000
75 #define BIT_16 0x10000
76 #define BIT_17 0x20000
77 #define BIT_18 0x40000
78 #define BIT_19 0x80000
79 #define BIT_20 0x100000
80 #define BIT_21 0x200000
81 #define BIT_22 0x400000
82 #define BIT_23 0x800000
83 #define BIT_24 0x1000000
84 #define BIT_25 0x2000000
85 #define BIT_26 0x4000000
86 #define BIT_27 0x8000000
87 #define BIT_28 0x10000000
88 #define BIT_29 0x20000000
89 #define BIT_30 0x40000000
90 #define BIT_31 0x80000000
91
92 #define LSB(x) ((uint8_t)(x))
93 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
94
95 #define LSW(x) ((uint16_t)(x))
96 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
97
98 #define LSD(x) ((uint32_t)((uint64_t)(x)))
99 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
100
101 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
102
103 /*
104 * I/O register
105 */
106
107 #define RD_REG_BYTE(addr) readb(addr)
108 #define RD_REG_WORD(addr) readw(addr)
109 #define RD_REG_DWORD(addr) readl(addr)
110 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
111 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
112 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
113 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
114 #define WRT_REG_WORD(addr, data) writew(data,addr)
115 #define WRT_REG_DWORD(addr, data) writel(data,addr)
116
117 /*
118 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
119 * 133Mhz slot.
120 */
121 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
122 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
123
124 /*
125 * Fibre Channel device definitions.
126 */
127 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
128 #define MAX_FIBRE_DEVICES 512
129 #define MAX_FIBRE_LUNS 0xFFFF
130 #define MAX_RSCN_COUNT 32
131 #define MAX_HOST_COUNT 16
132
133 /*
134 * Host adapter default definitions.
135 */
136 #define MAX_BUSES 1 /* We only have one bus today */
137 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
138 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
139 #define MIN_LUNS 8
140 #define MAX_LUNS MAX_FIBRE_LUNS
141 #define MAX_CMDS_PER_LUN 255
142
143 /*
144 * Fibre Channel device definitions.
145 */
146 #define SNS_LAST_LOOP_ID_2100 0xfe
147 #define SNS_LAST_LOOP_ID_2300 0x7ff
148
149 #define LAST_LOCAL_LOOP_ID 0x7d
150 #define SNS_FL_PORT 0x7e
151 #define FABRIC_CONTROLLER 0x7f
152 #define SIMPLE_NAME_SERVER 0x80
153 #define SNS_FIRST_LOOP_ID 0x81
154 #define MANAGEMENT_SERVER 0xfe
155 #define BROADCAST 0xff
156
157 /*
158 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
159 * valid range of an N-PORT id is 0 through 0x7ef.
160 */
161 #define NPH_LAST_HANDLE 0x7ef
162 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
163 #define NPH_SNS 0x7fc /* FFFFFC */
164 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
165 #define NPH_F_PORT 0x7fe /* FFFFFE */
166 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
167
168 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
169 #include "qla_fw.h"
170
171 /*
172 * Timeout timer counts in seconds
173 */
174 #define PORT_RETRY_TIME 1
175 #define LOOP_DOWN_TIMEOUT 60
176 #define LOOP_DOWN_TIME 255 /* 240 */
177 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
178
179 /* Maximum outstanding commands in ISP queues (1-65535) */
180 #define MAX_OUTSTANDING_COMMANDS 1024
181
182 /* ISP request and response entry counts (37-65535) */
183 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
184 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
185 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
186 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
187 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
188 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
189
190 struct req_que;
191
192 /*
193 * (sd.h is not exported, hence local inclusion)
194 * Data Integrity Field tuple.
195 */
196 struct sd_dif_tuple {
197 __be16 guard_tag; /* Checksum */
198 __be16 app_tag; /* Opaque storage */
199 __be32 ref_tag; /* Target LBA or indirect LBA */
200 };
201
202 /*
203 * SCSI Request Block
204 */
205 typedef struct srb {
206 atomic_t ref_count;
207 struct fc_port *fcport;
208 uint32_t handle;
209
210 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
211
212 uint16_t flags;
213
214 uint32_t request_sense_length;
215 uint8_t *request_sense_ptr;
216
217 void *ctx;
218 } srb_t;
219
220 /*
221 * SRB flag definitions
222 */
223 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
224 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
225 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
226 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
227 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
228
229 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
230 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
231
232 /*
233 * SRB extensions.
234 */
235 struct srb_iocb {
236 union {
237 struct {
238 uint16_t flags;
239 #define SRB_LOGIN_RETRIED BIT_0
240 #define SRB_LOGIN_COND_PLOGI BIT_1
241 #define SRB_LOGIN_SKIP_PRLI BIT_2
242 uint16_t data[2];
243 } logio;
244 struct {
245 /*
246 * Values for flags field below are as
247 * defined in tsk_mgmt_entry struct
248 * for control_flags field in qla_fw.h.
249 */
250 uint32_t flags;
251 uint32_t lun;
252 uint32_t data;
253 } tmf;
254 } u;
255
256 struct timer_list timer;
257
258 void (*done)(srb_t *);
259 void (*free)(srb_t *);
260 void (*timeout)(srb_t *);
261 };
262
263 /* Values for srb_ctx type */
264 #define SRB_LOGIN_CMD 1
265 #define SRB_LOGOUT_CMD 2
266 #define SRB_ELS_CMD_RPT 3
267 #define SRB_ELS_CMD_HST 4
268 #define SRB_CT_CMD 5
269 #define SRB_ADISC_CMD 6
270 #define SRB_TM_CMD 7
271
272 struct srb_ctx {
273 uint16_t type;
274 char *name;
275 int iocbs;
276 union {
277 struct srb_iocb *iocb_cmd;
278 struct fc_bsg_job *bsg_job;
279 } u;
280 };
281
282 struct msg_echo_lb {
283 dma_addr_t send_dma;
284 dma_addr_t rcv_dma;
285 uint16_t req_sg_cnt;
286 uint16_t rsp_sg_cnt;
287 uint16_t options;
288 uint32_t transfer_size;
289 };
290
291 /*
292 * ISP I/O Register Set structure definitions.
293 */
294 struct device_reg_2xxx {
295 uint16_t flash_address; /* Flash BIOS address */
296 uint16_t flash_data; /* Flash BIOS data */
297 uint16_t unused_1[1]; /* Gap */
298 uint16_t ctrl_status; /* Control/Status */
299 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
300 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
301 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
302
303 uint16_t ictrl; /* Interrupt control */
304 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
305 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
306
307 uint16_t istatus; /* Interrupt status */
308 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
309
310 uint16_t semaphore; /* Semaphore */
311 uint16_t nvram; /* NVRAM register. */
312 #define NVR_DESELECT 0
313 #define NVR_BUSY BIT_15
314 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
315 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
316 #define NVR_DATA_IN BIT_3
317 #define NVR_DATA_OUT BIT_2
318 #define NVR_SELECT BIT_1
319 #define NVR_CLOCK BIT_0
320
321 #define NVR_WAIT_CNT 20000
322
323 union {
324 struct {
325 uint16_t mailbox0;
326 uint16_t mailbox1;
327 uint16_t mailbox2;
328 uint16_t mailbox3;
329 uint16_t mailbox4;
330 uint16_t mailbox5;
331 uint16_t mailbox6;
332 uint16_t mailbox7;
333 uint16_t unused_2[59]; /* Gap */
334 } __attribute__((packed)) isp2100;
335 struct {
336 /* Request Queue */
337 uint16_t req_q_in; /* In-Pointer */
338 uint16_t req_q_out; /* Out-Pointer */
339 /* Response Queue */
340 uint16_t rsp_q_in; /* In-Pointer */
341 uint16_t rsp_q_out; /* Out-Pointer */
342
343 /* RISC to Host Status */
344 uint32_t host_status;
345 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
346 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
347
348 /* Host to Host Semaphore */
349 uint16_t host_semaphore;
350 uint16_t unused_3[17]; /* Gap */
351 uint16_t mailbox0;
352 uint16_t mailbox1;
353 uint16_t mailbox2;
354 uint16_t mailbox3;
355 uint16_t mailbox4;
356 uint16_t mailbox5;
357 uint16_t mailbox6;
358 uint16_t mailbox7;
359 uint16_t mailbox8;
360 uint16_t mailbox9;
361 uint16_t mailbox10;
362 uint16_t mailbox11;
363 uint16_t mailbox12;
364 uint16_t mailbox13;
365 uint16_t mailbox14;
366 uint16_t mailbox15;
367 uint16_t mailbox16;
368 uint16_t mailbox17;
369 uint16_t mailbox18;
370 uint16_t mailbox19;
371 uint16_t mailbox20;
372 uint16_t mailbox21;
373 uint16_t mailbox22;
374 uint16_t mailbox23;
375 uint16_t mailbox24;
376 uint16_t mailbox25;
377 uint16_t mailbox26;
378 uint16_t mailbox27;
379 uint16_t mailbox28;
380 uint16_t mailbox29;
381 uint16_t mailbox30;
382 uint16_t mailbox31;
383 uint16_t fb_cmd;
384 uint16_t unused_4[10]; /* Gap */
385 } __attribute__((packed)) isp2300;
386 } u;
387
388 uint16_t fpm_diag_config;
389 uint16_t unused_5[0x4]; /* Gap */
390 uint16_t risc_hw;
391 uint16_t unused_5_1; /* Gap */
392 uint16_t pcr; /* Processor Control Register. */
393 uint16_t unused_6[0x5]; /* Gap */
394 uint16_t mctr; /* Memory Configuration and Timing. */
395 uint16_t unused_7[0x3]; /* Gap */
396 uint16_t fb_cmd_2100; /* Unused on 23XX */
397 uint16_t unused_8[0x3]; /* Gap */
398 uint16_t hccr; /* Host command & control register. */
399 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
400 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
401 /* HCCR commands */
402 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
403 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
404 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
405 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
406 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
407 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
408 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
409 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
410
411 uint16_t unused_9[5]; /* Gap */
412 uint16_t gpiod; /* GPIO Data register. */
413 uint16_t gpioe; /* GPIO Enable register. */
414 #define GPIO_LED_MASK 0x00C0
415 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
416 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
417 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
418 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
419 #define GPIO_LED_ALL_OFF 0x0000
420 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
421 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
422
423 union {
424 struct {
425 uint16_t unused_10[8]; /* Gap */
426 uint16_t mailbox8;
427 uint16_t mailbox9;
428 uint16_t mailbox10;
429 uint16_t mailbox11;
430 uint16_t mailbox12;
431 uint16_t mailbox13;
432 uint16_t mailbox14;
433 uint16_t mailbox15;
434 uint16_t mailbox16;
435 uint16_t mailbox17;
436 uint16_t mailbox18;
437 uint16_t mailbox19;
438 uint16_t mailbox20;
439 uint16_t mailbox21;
440 uint16_t mailbox22;
441 uint16_t mailbox23; /* Also probe reg. */
442 } __attribute__((packed)) isp2200;
443 } u_end;
444 };
445
446 struct device_reg_25xxmq {
447 uint32_t req_q_in;
448 uint32_t req_q_out;
449 uint32_t rsp_q_in;
450 uint32_t rsp_q_out;
451 };
452
453 typedef union {
454 struct device_reg_2xxx isp;
455 struct device_reg_24xx isp24;
456 struct device_reg_25xxmq isp25mq;
457 struct device_reg_82xx isp82;
458 } device_reg_t;
459
460 #define ISP_REQ_Q_IN(ha, reg) \
461 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
462 &(reg)->u.isp2100.mailbox4 : \
463 &(reg)->u.isp2300.req_q_in)
464 #define ISP_REQ_Q_OUT(ha, reg) \
465 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
466 &(reg)->u.isp2100.mailbox4 : \
467 &(reg)->u.isp2300.req_q_out)
468 #define ISP_RSP_Q_IN(ha, reg) \
469 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
470 &(reg)->u.isp2100.mailbox5 : \
471 &(reg)->u.isp2300.rsp_q_in)
472 #define ISP_RSP_Q_OUT(ha, reg) \
473 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
474 &(reg)->u.isp2100.mailbox5 : \
475 &(reg)->u.isp2300.rsp_q_out)
476
477 #define MAILBOX_REG(ha, reg, num) \
478 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
479 (num < 8 ? \
480 &(reg)->u.isp2100.mailbox0 + (num) : \
481 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
482 &(reg)->u.isp2300.mailbox0 + (num))
483 #define RD_MAILBOX_REG(ha, reg, num) \
484 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
485 #define WRT_MAILBOX_REG(ha, reg, num, data) \
486 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
487
488 #define FB_CMD_REG(ha, reg) \
489 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
490 &(reg)->fb_cmd_2100 : \
491 &(reg)->u.isp2300.fb_cmd)
492 #define RD_FB_CMD_REG(ha, reg) \
493 RD_REG_WORD(FB_CMD_REG(ha, reg))
494 #define WRT_FB_CMD_REG(ha, reg, data) \
495 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
496
497 typedef struct {
498 uint32_t out_mb; /* outbound from driver */
499 uint32_t in_mb; /* Incoming from RISC */
500 uint16_t mb[MAILBOX_REGISTER_COUNT];
501 long buf_size;
502 void *bufp;
503 uint32_t tov;
504 uint8_t flags;
505 #define MBX_DMA_IN BIT_0
506 #define MBX_DMA_OUT BIT_1
507 #define IOCTL_CMD BIT_2
508 } mbx_cmd_t;
509
510 #define MBX_TOV_SECONDS 30
511
512 /*
513 * ISP product identification definitions in mailboxes after reset.
514 */
515 #define PROD_ID_1 0x4953
516 #define PROD_ID_2 0x0000
517 #define PROD_ID_2a 0x5020
518 #define PROD_ID_3 0x2020
519
520 /*
521 * ISP mailbox Self-Test status codes
522 */
523 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
524 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
525 #define MBS_BUSY 4 /* Busy. */
526
527 /*
528 * ISP mailbox command complete status codes
529 */
530 #define MBS_COMMAND_COMPLETE 0x4000
531 #define MBS_INVALID_COMMAND 0x4001
532 #define MBS_HOST_INTERFACE_ERROR 0x4002
533 #define MBS_TEST_FAILED 0x4003
534 #define MBS_COMMAND_ERROR 0x4005
535 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
536 #define MBS_PORT_ID_USED 0x4007
537 #define MBS_LOOP_ID_USED 0x4008
538 #define MBS_ALL_IDS_IN_USE 0x4009
539 #define MBS_NOT_LOGGED_IN 0x400A
540 #define MBS_LINK_DOWN_ERROR 0x400B
541 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
542
543 /*
544 * ISP mailbox asynchronous event status codes
545 */
546 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
547 #define MBA_RESET 0x8001 /* Reset Detected. */
548 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
549 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
550 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
551 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
552 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
553 /* occurred. */
554 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
555 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
556 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
557 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
558 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
559 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
560 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
561 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
562 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
563 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
564 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
565 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
566 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
567 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
568 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
569 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
570 /* used. */
571 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
572 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
573 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
574 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
575 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
576 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
577 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
578 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
579 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
580 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
581 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
582 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
583 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
584 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
585
586 /* ISP mailbox loopback echo diagnostic error code */
587 #define MBS_LB_RESET 0x17
588 /*
589 * Firmware options 1, 2, 3.
590 */
591 #define FO1_AE_ON_LIPF8 BIT_0
592 #define FO1_AE_ALL_LIP_RESET BIT_1
593 #define FO1_CTIO_RETRY BIT_3
594 #define FO1_DISABLE_LIP_F7_SW BIT_4
595 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
596 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
597 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
598 #define FO1_SET_EMPHASIS_SWING BIT_8
599 #define FO1_AE_AUTO_BYPASS BIT_9
600 #define FO1_ENABLE_PURE_IOCB BIT_10
601 #define FO1_AE_PLOGI_RJT BIT_11
602 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
603 #define FO1_AE_QUEUE_FULL BIT_13
604
605 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
606 #define FO2_REV_LOOPBACK BIT_1
607
608 #define FO3_ENABLE_EMERG_IOCB BIT_0
609 #define FO3_AE_RND_ERROR BIT_1
610
611 /* 24XX additional firmware options */
612 #define ADD_FO_COUNT 3
613 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
614 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
615
616 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
617
618 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
619
620 /*
621 * ISP mailbox commands
622 */
623 #define MBC_LOAD_RAM 1 /* Load RAM. */
624 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
625 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
626 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
627 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
628 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
629 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
630 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
631 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
632 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
633 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
634 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
635 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
636 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
637 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
638 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
639 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
640 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
641 #define MBC_RESET 0x18 /* Reset. */
642 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
643 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
644 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
645 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
646 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
647 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
648 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
649 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
650 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
651 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
652 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
653 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
654 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
655 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
656 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
657 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
658 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
659 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
660 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
661 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
662 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
663 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
664 /* Initialization Procedure */
665 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
666 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
667 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
668 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
669 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
670 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
671 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
672 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
673 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
674 #define MBC_LIP_RESET 0x6c /* LIP reset. */
675 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
676 /* commandd. */
677 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
678 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
679 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
680 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
681 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
682 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
683 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
684 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
685 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
686 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
687 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
688
689 /*
690 * ISP24xx mailbox commands
691 */
692 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
693 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
694 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
695 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
696 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
697 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
698 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
699 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
700 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
701 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
702 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
703 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
704 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
705 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
706 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
707 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
708 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
709 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
710
711 /*
712 * ISP81xx mailbox commands
713 */
714 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
715
716 /* Firmware return data sizes */
717 #define FCAL_MAP_SIZE 128
718
719 /* Mailbox bit definitions for out_mb and in_mb */
720 #define MBX_31 BIT_31
721 #define MBX_30 BIT_30
722 #define MBX_29 BIT_29
723 #define MBX_28 BIT_28
724 #define MBX_27 BIT_27
725 #define MBX_26 BIT_26
726 #define MBX_25 BIT_25
727 #define MBX_24 BIT_24
728 #define MBX_23 BIT_23
729 #define MBX_22 BIT_22
730 #define MBX_21 BIT_21
731 #define MBX_20 BIT_20
732 #define MBX_19 BIT_19
733 #define MBX_18 BIT_18
734 #define MBX_17 BIT_17
735 #define MBX_16 BIT_16
736 #define MBX_15 BIT_15
737 #define MBX_14 BIT_14
738 #define MBX_13 BIT_13
739 #define MBX_12 BIT_12
740 #define MBX_11 BIT_11
741 #define MBX_10 BIT_10
742 #define MBX_9 BIT_9
743 #define MBX_8 BIT_8
744 #define MBX_7 BIT_7
745 #define MBX_6 BIT_6
746 #define MBX_5 BIT_5
747 #define MBX_4 BIT_4
748 #define MBX_3 BIT_3
749 #define MBX_2 BIT_2
750 #define MBX_1 BIT_1
751 #define MBX_0 BIT_0
752
753 /*
754 * Firmware state codes from get firmware state mailbox command
755 */
756 #define FSTATE_CONFIG_WAIT 0
757 #define FSTATE_WAIT_AL_PA 1
758 #define FSTATE_WAIT_LOGIN 2
759 #define FSTATE_READY 3
760 #define FSTATE_LOSS_OF_SYNC 4
761 #define FSTATE_ERROR 5
762 #define FSTATE_REINIT 6
763 #define FSTATE_NON_PART 7
764
765 #define FSTATE_CONFIG_CORRECT 0
766 #define FSTATE_P2P_RCV_LIP 1
767 #define FSTATE_P2P_CHOOSE_LOOP 2
768 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
769 #define FSTATE_FATAL_ERROR 4
770 #define FSTATE_LOOP_BACK_CONN 5
771
772 /*
773 * Port Database structure definition
774 * Little endian except where noted.
775 */
776 #define PORT_DATABASE_SIZE 128 /* bytes */
777 typedef struct {
778 uint8_t options;
779 uint8_t control;
780 uint8_t master_state;
781 uint8_t slave_state;
782 uint8_t reserved[2];
783 uint8_t hard_address;
784 uint8_t reserved_1;
785 uint8_t port_id[4];
786 uint8_t node_name[WWN_SIZE];
787 uint8_t port_name[WWN_SIZE];
788 uint16_t execution_throttle;
789 uint16_t execution_count;
790 uint8_t reset_count;
791 uint8_t reserved_2;
792 uint16_t resource_allocation;
793 uint16_t current_allocation;
794 uint16_t queue_head;
795 uint16_t queue_tail;
796 uint16_t transmit_execution_list_next;
797 uint16_t transmit_execution_list_previous;
798 uint16_t common_features;
799 uint16_t total_concurrent_sequences;
800 uint16_t RO_by_information_category;
801 uint8_t recipient;
802 uint8_t initiator;
803 uint16_t receive_data_size;
804 uint16_t concurrent_sequences;
805 uint16_t open_sequences_per_exchange;
806 uint16_t lun_abort_flags;
807 uint16_t lun_stop_flags;
808 uint16_t stop_queue_head;
809 uint16_t stop_queue_tail;
810 uint16_t port_retry_timer;
811 uint16_t next_sequence_id;
812 uint16_t frame_count;
813 uint16_t PRLI_payload_length;
814 uint8_t prli_svc_param_word_0[2]; /* Big endian */
815 /* Bits 15-0 of word 0 */
816 uint8_t prli_svc_param_word_3[2]; /* Big endian */
817 /* Bits 15-0 of word 3 */
818 uint16_t loop_id;
819 uint16_t extended_lun_info_list_pointer;
820 uint16_t extended_lun_stop_list_pointer;
821 } port_database_t;
822
823 /*
824 * Port database slave/master states
825 */
826 #define PD_STATE_DISCOVERY 0
827 #define PD_STATE_WAIT_DISCOVERY_ACK 1
828 #define PD_STATE_PORT_LOGIN 2
829 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
830 #define PD_STATE_PROCESS_LOGIN 4
831 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
832 #define PD_STATE_PORT_LOGGED_IN 6
833 #define PD_STATE_PORT_UNAVAILABLE 7
834 #define PD_STATE_PROCESS_LOGOUT 8
835 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
836 #define PD_STATE_PORT_LOGOUT 10
837 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
838
839
840 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
841 #define QLA_ZIO_DISABLED 0
842 #define QLA_ZIO_DEFAULT_TIMER 2
843
844 /*
845 * ISP Initialization Control Block.
846 * Little endian except where noted.
847 */
848 #define ICB_VERSION 1
849 typedef struct {
850 uint8_t version;
851 uint8_t reserved_1;
852
853 /*
854 * LSB BIT 0 = Enable Hard Loop Id
855 * LSB BIT 1 = Enable Fairness
856 * LSB BIT 2 = Enable Full-Duplex
857 * LSB BIT 3 = Enable Fast Posting
858 * LSB BIT 4 = Enable Target Mode
859 * LSB BIT 5 = Disable Initiator Mode
860 * LSB BIT 6 = Enable ADISC
861 * LSB BIT 7 = Enable Target Inquiry Data
862 *
863 * MSB BIT 0 = Enable PDBC Notify
864 * MSB BIT 1 = Non Participating LIP
865 * MSB BIT 2 = Descending Loop ID Search
866 * MSB BIT 3 = Acquire Loop ID in LIPA
867 * MSB BIT 4 = Stop PortQ on Full Status
868 * MSB BIT 5 = Full Login after LIP
869 * MSB BIT 6 = Node Name Option
870 * MSB BIT 7 = Ext IFWCB enable bit
871 */
872 uint8_t firmware_options[2];
873
874 uint16_t frame_payload_size;
875 uint16_t max_iocb_allocation;
876 uint16_t execution_throttle;
877 uint8_t retry_count;
878 uint8_t retry_delay; /* unused */
879 uint8_t port_name[WWN_SIZE]; /* Big endian. */
880 uint16_t hard_address;
881 uint8_t inquiry_data;
882 uint8_t login_timeout;
883 uint8_t node_name[WWN_SIZE]; /* Big endian. */
884
885 uint16_t request_q_outpointer;
886 uint16_t response_q_inpointer;
887 uint16_t request_q_length;
888 uint16_t response_q_length;
889 uint32_t request_q_address[2];
890 uint32_t response_q_address[2];
891
892 uint16_t lun_enables;
893 uint8_t command_resource_count;
894 uint8_t immediate_notify_resource_count;
895 uint16_t timeout;
896 uint8_t reserved_2[2];
897
898 /*
899 * LSB BIT 0 = Timer Operation mode bit 0
900 * LSB BIT 1 = Timer Operation mode bit 1
901 * LSB BIT 2 = Timer Operation mode bit 2
902 * LSB BIT 3 = Timer Operation mode bit 3
903 * LSB BIT 4 = Init Config Mode bit 0
904 * LSB BIT 5 = Init Config Mode bit 1
905 * LSB BIT 6 = Init Config Mode bit 2
906 * LSB BIT 7 = Enable Non part on LIHA failure
907 *
908 * MSB BIT 0 = Enable class 2
909 * MSB BIT 1 = Enable ACK0
910 * MSB BIT 2 =
911 * MSB BIT 3 =
912 * MSB BIT 4 = FC Tape Enable
913 * MSB BIT 5 = Enable FC Confirm
914 * MSB BIT 6 = Enable command queuing in target mode
915 * MSB BIT 7 = No Logo On Link Down
916 */
917 uint8_t add_firmware_options[2];
918
919 uint8_t response_accumulation_timer;
920 uint8_t interrupt_delay_timer;
921
922 /*
923 * LSB BIT 0 = Enable Read xfr_rdy
924 * LSB BIT 1 = Soft ID only
925 * LSB BIT 2 =
926 * LSB BIT 3 =
927 * LSB BIT 4 = FCP RSP Payload [0]
928 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
929 * LSB BIT 6 = Enable Out-of-Order frame handling
930 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
931 *
932 * MSB BIT 0 = Sbus enable - 2300
933 * MSB BIT 1 =
934 * MSB BIT 2 =
935 * MSB BIT 3 =
936 * MSB BIT 4 = LED mode
937 * MSB BIT 5 = enable 50 ohm termination
938 * MSB BIT 6 = Data Rate (2300 only)
939 * MSB BIT 7 = Data Rate (2300 only)
940 */
941 uint8_t special_options[2];
942
943 uint8_t reserved_3[26];
944 } init_cb_t;
945
946 /*
947 * Get Link Status mailbox command return buffer.
948 */
949 #define GLSO_SEND_RPS BIT_0
950 #define GLSO_USE_DID BIT_3
951
952 struct link_statistics {
953 uint32_t link_fail_cnt;
954 uint32_t loss_sync_cnt;
955 uint32_t loss_sig_cnt;
956 uint32_t prim_seq_err_cnt;
957 uint32_t inval_xmit_word_cnt;
958 uint32_t inval_crc_cnt;
959 uint32_t lip_cnt;
960 uint32_t unused1[0x1a];
961 uint32_t tx_frames;
962 uint32_t rx_frames;
963 uint32_t dumped_frames;
964 uint32_t unused2[2];
965 uint32_t nos_rcvd;
966 };
967
968 /*
969 * NVRAM Command values.
970 */
971 #define NV_START_BIT BIT_2
972 #define NV_WRITE_OP (BIT_26+BIT_24)
973 #define NV_READ_OP (BIT_26+BIT_25)
974 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
975 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
976 #define NV_DELAY_COUNT 10
977
978 /*
979 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
980 */
981 typedef struct {
982 /*
983 * NVRAM header
984 */
985 uint8_t id[4];
986 uint8_t nvram_version;
987 uint8_t reserved_0;
988
989 /*
990 * NVRAM RISC parameter block
991 */
992 uint8_t parameter_block_version;
993 uint8_t reserved_1;
994
995 /*
996 * LSB BIT 0 = Enable Hard Loop Id
997 * LSB BIT 1 = Enable Fairness
998 * LSB BIT 2 = Enable Full-Duplex
999 * LSB BIT 3 = Enable Fast Posting
1000 * LSB BIT 4 = Enable Target Mode
1001 * LSB BIT 5 = Disable Initiator Mode
1002 * LSB BIT 6 = Enable ADISC
1003 * LSB BIT 7 = Enable Target Inquiry Data
1004 *
1005 * MSB BIT 0 = Enable PDBC Notify
1006 * MSB BIT 1 = Non Participating LIP
1007 * MSB BIT 2 = Descending Loop ID Search
1008 * MSB BIT 3 = Acquire Loop ID in LIPA
1009 * MSB BIT 4 = Stop PortQ on Full Status
1010 * MSB BIT 5 = Full Login after LIP
1011 * MSB BIT 6 = Node Name Option
1012 * MSB BIT 7 = Ext IFWCB enable bit
1013 */
1014 uint8_t firmware_options[2];
1015
1016 uint16_t frame_payload_size;
1017 uint16_t max_iocb_allocation;
1018 uint16_t execution_throttle;
1019 uint8_t retry_count;
1020 uint8_t retry_delay; /* unused */
1021 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1022 uint16_t hard_address;
1023 uint8_t inquiry_data;
1024 uint8_t login_timeout;
1025 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1026
1027 /*
1028 * LSB BIT 0 = Timer Operation mode bit 0
1029 * LSB BIT 1 = Timer Operation mode bit 1
1030 * LSB BIT 2 = Timer Operation mode bit 2
1031 * LSB BIT 3 = Timer Operation mode bit 3
1032 * LSB BIT 4 = Init Config Mode bit 0
1033 * LSB BIT 5 = Init Config Mode bit 1
1034 * LSB BIT 6 = Init Config Mode bit 2
1035 * LSB BIT 7 = Enable Non part on LIHA failure
1036 *
1037 * MSB BIT 0 = Enable class 2
1038 * MSB BIT 1 = Enable ACK0
1039 * MSB BIT 2 =
1040 * MSB BIT 3 =
1041 * MSB BIT 4 = FC Tape Enable
1042 * MSB BIT 5 = Enable FC Confirm
1043 * MSB BIT 6 = Enable command queuing in target mode
1044 * MSB BIT 7 = No Logo On Link Down
1045 */
1046 uint8_t add_firmware_options[2];
1047
1048 uint8_t response_accumulation_timer;
1049 uint8_t interrupt_delay_timer;
1050
1051 /*
1052 * LSB BIT 0 = Enable Read xfr_rdy
1053 * LSB BIT 1 = Soft ID only
1054 * LSB BIT 2 =
1055 * LSB BIT 3 =
1056 * LSB BIT 4 = FCP RSP Payload [0]
1057 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1058 * LSB BIT 6 = Enable Out-of-Order frame handling
1059 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1060 *
1061 * MSB BIT 0 = Sbus enable - 2300
1062 * MSB BIT 1 =
1063 * MSB BIT 2 =
1064 * MSB BIT 3 =
1065 * MSB BIT 4 = LED mode
1066 * MSB BIT 5 = enable 50 ohm termination
1067 * MSB BIT 6 = Data Rate (2300 only)
1068 * MSB BIT 7 = Data Rate (2300 only)
1069 */
1070 uint8_t special_options[2];
1071
1072 /* Reserved for expanded RISC parameter block */
1073 uint8_t reserved_2[22];
1074
1075 /*
1076 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1077 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1078 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1079 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1080 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1081 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1082 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1083 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1084 *
1085 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1086 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1087 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1088 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1089 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1090 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1091 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1092 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1093 *
1094 * LSB BIT 0 = Output Swing 1G bit 0
1095 * LSB BIT 1 = Output Swing 1G bit 1
1096 * LSB BIT 2 = Output Swing 1G bit 2
1097 * LSB BIT 3 = Output Emphasis 1G bit 0
1098 * LSB BIT 4 = Output Emphasis 1G bit 1
1099 * LSB BIT 5 = Output Swing 2G bit 0
1100 * LSB BIT 6 = Output Swing 2G bit 1
1101 * LSB BIT 7 = Output Swing 2G bit 2
1102 *
1103 * MSB BIT 0 = Output Emphasis 2G bit 0
1104 * MSB BIT 1 = Output Emphasis 2G bit 1
1105 * MSB BIT 2 = Output Enable
1106 * MSB BIT 3 =
1107 * MSB BIT 4 =
1108 * MSB BIT 5 =
1109 * MSB BIT 6 =
1110 * MSB BIT 7 =
1111 */
1112 uint8_t seriallink_options[4];
1113
1114 /*
1115 * NVRAM host parameter block
1116 *
1117 * LSB BIT 0 = Enable spinup delay
1118 * LSB BIT 1 = Disable BIOS
1119 * LSB BIT 2 = Enable Memory Map BIOS
1120 * LSB BIT 3 = Enable Selectable Boot
1121 * LSB BIT 4 = Disable RISC code load
1122 * LSB BIT 5 = Set cache line size 1
1123 * LSB BIT 6 = PCI Parity Disable
1124 * LSB BIT 7 = Enable extended logging
1125 *
1126 * MSB BIT 0 = Enable 64bit addressing
1127 * MSB BIT 1 = Enable lip reset
1128 * MSB BIT 2 = Enable lip full login
1129 * MSB BIT 3 = Enable target reset
1130 * MSB BIT 4 = Enable database storage
1131 * MSB BIT 5 = Enable cache flush read
1132 * MSB BIT 6 = Enable database load
1133 * MSB BIT 7 = Enable alternate WWN
1134 */
1135 uint8_t host_p[2];
1136
1137 uint8_t boot_node_name[WWN_SIZE];
1138 uint8_t boot_lun_number;
1139 uint8_t reset_delay;
1140 uint8_t port_down_retry_count;
1141 uint8_t boot_id_number;
1142 uint16_t max_luns_per_target;
1143 uint8_t fcode_boot_port_name[WWN_SIZE];
1144 uint8_t alternate_port_name[WWN_SIZE];
1145 uint8_t alternate_node_name[WWN_SIZE];
1146
1147 /*
1148 * BIT 0 = Selective Login
1149 * BIT 1 = Alt-Boot Enable
1150 * BIT 2 =
1151 * BIT 3 = Boot Order List
1152 * BIT 4 =
1153 * BIT 5 = Selective LUN
1154 * BIT 6 =
1155 * BIT 7 = unused
1156 */
1157 uint8_t efi_parameters;
1158
1159 uint8_t link_down_timeout;
1160
1161 uint8_t adapter_id[16];
1162
1163 uint8_t alt1_boot_node_name[WWN_SIZE];
1164 uint16_t alt1_boot_lun_number;
1165 uint8_t alt2_boot_node_name[WWN_SIZE];
1166 uint16_t alt2_boot_lun_number;
1167 uint8_t alt3_boot_node_name[WWN_SIZE];
1168 uint16_t alt3_boot_lun_number;
1169 uint8_t alt4_boot_node_name[WWN_SIZE];
1170 uint16_t alt4_boot_lun_number;
1171 uint8_t alt5_boot_node_name[WWN_SIZE];
1172 uint16_t alt5_boot_lun_number;
1173 uint8_t alt6_boot_node_name[WWN_SIZE];
1174 uint16_t alt6_boot_lun_number;
1175 uint8_t alt7_boot_node_name[WWN_SIZE];
1176 uint16_t alt7_boot_lun_number;
1177
1178 uint8_t reserved_3[2];
1179
1180 /* Offset 200-215 : Model Number */
1181 uint8_t model_number[16];
1182
1183 /* OEM related items */
1184 uint8_t oem_specific[16];
1185
1186 /*
1187 * NVRAM Adapter Features offset 232-239
1188 *
1189 * LSB BIT 0 = External GBIC
1190 * LSB BIT 1 = Risc RAM parity
1191 * LSB BIT 2 = Buffer Plus Module
1192 * LSB BIT 3 = Multi Chip Adapter
1193 * LSB BIT 4 = Internal connector
1194 * LSB BIT 5 =
1195 * LSB BIT 6 =
1196 * LSB BIT 7 =
1197 *
1198 * MSB BIT 0 =
1199 * MSB BIT 1 =
1200 * MSB BIT 2 =
1201 * MSB BIT 3 =
1202 * MSB BIT 4 =
1203 * MSB BIT 5 =
1204 * MSB BIT 6 =
1205 * MSB BIT 7 =
1206 */
1207 uint8_t adapter_features[2];
1208
1209 uint8_t reserved_4[16];
1210
1211 /* Subsystem vendor ID for ISP2200 */
1212 uint16_t subsystem_vendor_id_2200;
1213
1214 /* Subsystem device ID for ISP2200 */
1215 uint16_t subsystem_device_id_2200;
1216
1217 uint8_t reserved_5;
1218 uint8_t checksum;
1219 } nvram_t;
1220
1221 /*
1222 * ISP queue - response queue entry definition.
1223 */
1224 typedef struct {
1225 uint8_t data[60];
1226 uint32_t signature;
1227 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1228 } response_t;
1229
1230 typedef union {
1231 uint16_t extended;
1232 struct {
1233 uint8_t reserved;
1234 uint8_t standard;
1235 } id;
1236 } target_id_t;
1237
1238 #define SET_TARGET_ID(ha, to, from) \
1239 do { \
1240 if (HAS_EXTENDED_IDS(ha)) \
1241 to.extended = cpu_to_le16(from); \
1242 else \
1243 to.id.standard = (uint8_t)from; \
1244 } while (0)
1245
1246 /*
1247 * ISP queue - command entry structure definition.
1248 */
1249 #define COMMAND_TYPE 0x11 /* Command entry */
1250 typedef struct {
1251 uint8_t entry_type; /* Entry type. */
1252 uint8_t entry_count; /* Entry count. */
1253 uint8_t sys_define; /* System defined. */
1254 uint8_t entry_status; /* Entry Status. */
1255 uint32_t handle; /* System handle. */
1256 target_id_t target; /* SCSI ID */
1257 uint16_t lun; /* SCSI LUN */
1258 uint16_t control_flags; /* Control flags. */
1259 #define CF_WRITE BIT_6
1260 #define CF_READ BIT_5
1261 #define CF_SIMPLE_TAG BIT_3
1262 #define CF_ORDERED_TAG BIT_2
1263 #define CF_HEAD_TAG BIT_1
1264 uint16_t reserved_1;
1265 uint16_t timeout; /* Command timeout. */
1266 uint16_t dseg_count; /* Data segment count. */
1267 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1268 uint32_t byte_count; /* Total byte count. */
1269 uint32_t dseg_0_address; /* Data segment 0 address. */
1270 uint32_t dseg_0_length; /* Data segment 0 length. */
1271 uint32_t dseg_1_address; /* Data segment 1 address. */
1272 uint32_t dseg_1_length; /* Data segment 1 length. */
1273 uint32_t dseg_2_address; /* Data segment 2 address. */
1274 uint32_t dseg_2_length; /* Data segment 2 length. */
1275 } cmd_entry_t;
1276
1277 /*
1278 * ISP queue - 64-Bit addressing, command entry structure definition.
1279 */
1280 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1281 typedef struct {
1282 uint8_t entry_type; /* Entry type. */
1283 uint8_t entry_count; /* Entry count. */
1284 uint8_t sys_define; /* System defined. */
1285 uint8_t entry_status; /* Entry Status. */
1286 uint32_t handle; /* System handle. */
1287 target_id_t target; /* SCSI ID */
1288 uint16_t lun; /* SCSI LUN */
1289 uint16_t control_flags; /* Control flags. */
1290 uint16_t reserved_1;
1291 uint16_t timeout; /* Command timeout. */
1292 uint16_t dseg_count; /* Data segment count. */
1293 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1294 uint32_t byte_count; /* Total byte count. */
1295 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1296 uint32_t dseg_0_length; /* Data segment 0 length. */
1297 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1298 uint32_t dseg_1_length; /* Data segment 1 length. */
1299 } cmd_a64_entry_t, request_t;
1300
1301 /*
1302 * ISP queue - continuation entry structure definition.
1303 */
1304 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1305 typedef struct {
1306 uint8_t entry_type; /* Entry type. */
1307 uint8_t entry_count; /* Entry count. */
1308 uint8_t sys_define; /* System defined. */
1309 uint8_t entry_status; /* Entry Status. */
1310 uint32_t reserved;
1311 uint32_t dseg_0_address; /* Data segment 0 address. */
1312 uint32_t dseg_0_length; /* Data segment 0 length. */
1313 uint32_t dseg_1_address; /* Data segment 1 address. */
1314 uint32_t dseg_1_length; /* Data segment 1 length. */
1315 uint32_t dseg_2_address; /* Data segment 2 address. */
1316 uint32_t dseg_2_length; /* Data segment 2 length. */
1317 uint32_t dseg_3_address; /* Data segment 3 address. */
1318 uint32_t dseg_3_length; /* Data segment 3 length. */
1319 uint32_t dseg_4_address; /* Data segment 4 address. */
1320 uint32_t dseg_4_length; /* Data segment 4 length. */
1321 uint32_t dseg_5_address; /* Data segment 5 address. */
1322 uint32_t dseg_5_length; /* Data segment 5 length. */
1323 uint32_t dseg_6_address; /* Data segment 6 address. */
1324 uint32_t dseg_6_length; /* Data segment 6 length. */
1325 } cont_entry_t;
1326
1327 /*
1328 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1329 */
1330 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1331 typedef struct {
1332 uint8_t entry_type; /* Entry type. */
1333 uint8_t entry_count; /* Entry count. */
1334 uint8_t sys_define; /* System defined. */
1335 uint8_t entry_status; /* Entry Status. */
1336 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1337 uint32_t dseg_0_length; /* Data segment 0 length. */
1338 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1339 uint32_t dseg_1_length; /* Data segment 1 length. */
1340 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1341 uint32_t dseg_2_length; /* Data segment 2 length. */
1342 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1343 uint32_t dseg_3_length; /* Data segment 3 length. */
1344 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1345 uint32_t dseg_4_length; /* Data segment 4 length. */
1346 } cont_a64_entry_t;
1347
1348 #define PO_MODE_DIF_INSERT 0
1349 #define PO_MODE_DIF_REMOVE BIT_0
1350 #define PO_MODE_DIF_PASS BIT_1
1351 #define PO_MODE_DIF_REPLACE (BIT_0 + BIT_1)
1352 #define PO_ENABLE_DIF_BUNDLING BIT_8
1353 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1354 #define PO_DISABLE_INCR_REF_TAG BIT_5
1355 #define PO_DISABLE_GUARD_CHECK BIT_4
1356 /*
1357 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1358 */
1359 struct crc_context {
1360 uint32_t handle; /* System handle. */
1361 uint32_t ref_tag;
1362 uint16_t app_tag;
1363 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1364 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1365 uint16_t guard_seed; /* Initial Guard Seed */
1366 uint16_t prot_opts; /* Requested Data Protection Mode */
1367 uint16_t blk_size; /* Data size in bytes */
1368 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1369 * only) */
1370 uint32_t byte_count; /* Total byte count/ total data
1371 * transfer count */
1372 union {
1373 struct {
1374 uint32_t reserved_1;
1375 uint16_t reserved_2;
1376 uint16_t reserved_3;
1377 uint32_t reserved_4;
1378 uint32_t data_address[2];
1379 uint32_t data_length;
1380 uint32_t reserved_5[2];
1381 uint32_t reserved_6;
1382 } nobundling;
1383 struct {
1384 uint32_t dif_byte_count; /* Total DIF byte
1385 * count */
1386 uint16_t reserved_1;
1387 uint16_t dseg_count; /* Data segment count */
1388 uint32_t reserved_2;
1389 uint32_t data_address[2];
1390 uint32_t data_length;
1391 uint32_t dif_address[2];
1392 uint32_t dif_length; /* Data segment 0
1393 * length */
1394 } bundling;
1395 } u;
1396
1397 struct fcp_cmnd fcp_cmnd;
1398 dma_addr_t crc_ctx_dma;
1399 /* List of DMA context transfers */
1400 struct list_head dsd_list;
1401
1402 /* This structure should not exceed 512 bytes */
1403 };
1404
1405 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1406 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1407
1408 /*
1409 * ISP queue - status entry structure definition.
1410 */
1411 #define STATUS_TYPE 0x03 /* Status entry. */
1412 typedef struct {
1413 uint8_t entry_type; /* Entry type. */
1414 uint8_t entry_count; /* Entry count. */
1415 uint8_t sys_define; /* System defined. */
1416 uint8_t entry_status; /* Entry Status. */
1417 uint32_t handle; /* System handle. */
1418 uint16_t scsi_status; /* SCSI status. */
1419 uint16_t comp_status; /* Completion status. */
1420 uint16_t state_flags; /* State flags. */
1421 uint16_t status_flags; /* Status flags. */
1422 uint16_t rsp_info_len; /* Response Info Length. */
1423 uint16_t req_sense_length; /* Request sense data length. */
1424 uint32_t residual_length; /* Residual transfer length. */
1425 uint8_t rsp_info[8]; /* FCP response information. */
1426 uint8_t req_sense_data[32]; /* Request sense data. */
1427 } sts_entry_t;
1428
1429 /*
1430 * Status entry entry status
1431 */
1432 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1433 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1434 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1435 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1436 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1437 #define RF_BUSY BIT_1 /* Busy */
1438 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1439 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1440 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1441 RF_INV_E_TYPE)
1442
1443 /*
1444 * Status entry SCSI status bit definitions.
1445 */
1446 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1447 #define SS_RESIDUAL_UNDER BIT_11
1448 #define SS_RESIDUAL_OVER BIT_10
1449 #define SS_SENSE_LEN_VALID BIT_9
1450 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1451
1452 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1453 #define SS_BUSY_CONDITION BIT_3
1454 #define SS_CONDITION_MET BIT_2
1455 #define SS_CHECK_CONDITION BIT_1
1456
1457 /*
1458 * Status entry completion status
1459 */
1460 #define CS_COMPLETE 0x0 /* No errors */
1461 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1462 #define CS_DMA 0x2 /* A DMA direction error. */
1463 #define CS_TRANSPORT 0x3 /* Transport error. */
1464 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1465 #define CS_ABORTED 0x5 /* System aborted command. */
1466 #define CS_TIMEOUT 0x6 /* Timeout error. */
1467 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1468 #define CS_DIF_ERROR 0xC /* DIF error detected */
1469
1470 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1471 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1472 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1473 /* (selection timeout) */
1474 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1475 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1476 #define CS_PORT_BUSY 0x2B /* Port Busy */
1477 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1478 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1479 #define CS_UNKNOWN 0x81 /* Driver defined */
1480 #define CS_RETRY 0x82 /* Driver defined */
1481 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1482
1483 /*
1484 * Status entry status flags
1485 */
1486 #define SF_ABTS_TERMINATED BIT_10
1487 #define SF_LOGOUT_SENT BIT_13
1488
1489 /*
1490 * ISP queue - status continuation entry structure definition.
1491 */
1492 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1493 typedef struct {
1494 uint8_t entry_type; /* Entry type. */
1495 uint8_t entry_count; /* Entry count. */
1496 uint8_t sys_define; /* System defined. */
1497 uint8_t entry_status; /* Entry Status. */
1498 uint8_t data[60]; /* data */
1499 } sts_cont_entry_t;
1500
1501 /*
1502 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1503 * structure definition.
1504 */
1505 #define STATUS_TYPE_21 0x21 /* Status entry. */
1506 typedef struct {
1507 uint8_t entry_type; /* Entry type. */
1508 uint8_t entry_count; /* Entry count. */
1509 uint8_t handle_count; /* Handle count. */
1510 uint8_t entry_status; /* Entry Status. */
1511 uint32_t handle[15]; /* System handles. */
1512 } sts21_entry_t;
1513
1514 /*
1515 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1516 * structure definition.
1517 */
1518 #define STATUS_TYPE_22 0x22 /* Status entry. */
1519 typedef struct {
1520 uint8_t entry_type; /* Entry type. */
1521 uint8_t entry_count; /* Entry count. */
1522 uint8_t handle_count; /* Handle count. */
1523 uint8_t entry_status; /* Entry Status. */
1524 uint16_t handle[30]; /* System handles. */
1525 } sts22_entry_t;
1526
1527 /*
1528 * ISP queue - marker entry structure definition.
1529 */
1530 #define MARKER_TYPE 0x04 /* Marker entry. */
1531 typedef struct {
1532 uint8_t entry_type; /* Entry type. */
1533 uint8_t entry_count; /* Entry count. */
1534 uint8_t handle_count; /* Handle count. */
1535 uint8_t entry_status; /* Entry Status. */
1536 uint32_t sys_define_2; /* System defined. */
1537 target_id_t target; /* SCSI ID */
1538 uint8_t modifier; /* Modifier (7-0). */
1539 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1540 #define MK_SYNC_ID 1 /* Synchronize ID */
1541 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1542 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1543 /* clear port changed, */
1544 /* use sequence number. */
1545 uint8_t reserved_1;
1546 uint16_t sequence_number; /* Sequence number of event */
1547 uint16_t lun; /* SCSI LUN */
1548 uint8_t reserved_2[48];
1549 } mrk_entry_t;
1550
1551 /*
1552 * ISP queue - Management Server entry structure definition.
1553 */
1554 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1555 typedef struct {
1556 uint8_t entry_type; /* Entry type. */
1557 uint8_t entry_count; /* Entry count. */
1558 uint8_t handle_count; /* Handle count. */
1559 uint8_t entry_status; /* Entry Status. */
1560 uint32_t handle1; /* System handle. */
1561 target_id_t loop_id;
1562 uint16_t status;
1563 uint16_t control_flags; /* Control flags. */
1564 uint16_t reserved2;
1565 uint16_t timeout;
1566 uint16_t cmd_dsd_count;
1567 uint16_t total_dsd_count;
1568 uint8_t type;
1569 uint8_t r_ctl;
1570 uint16_t rx_id;
1571 uint16_t reserved3;
1572 uint32_t handle2;
1573 uint32_t rsp_bytecount;
1574 uint32_t req_bytecount;
1575 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1576 uint32_t dseg_req_length; /* Data segment 0 length. */
1577 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1578 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1579 } ms_iocb_entry_t;
1580
1581
1582 /*
1583 * ISP queue - Mailbox Command entry structure definition.
1584 */
1585 #define MBX_IOCB_TYPE 0x39
1586 struct mbx_entry {
1587 uint8_t entry_type;
1588 uint8_t entry_count;
1589 uint8_t sys_define1;
1590 /* Use sys_define1 for source type */
1591 #define SOURCE_SCSI 0x00
1592 #define SOURCE_IP 0x01
1593 #define SOURCE_VI 0x02
1594 #define SOURCE_SCTP 0x03
1595 #define SOURCE_MP 0x04
1596 #define SOURCE_MPIOCTL 0x05
1597 #define SOURCE_ASYNC_IOCB 0x07
1598
1599 uint8_t entry_status;
1600
1601 uint32_t handle;
1602 target_id_t loop_id;
1603
1604 uint16_t status;
1605 uint16_t state_flags;
1606 uint16_t status_flags;
1607
1608 uint32_t sys_define2[2];
1609
1610 uint16_t mb0;
1611 uint16_t mb1;
1612 uint16_t mb2;
1613 uint16_t mb3;
1614 uint16_t mb6;
1615 uint16_t mb7;
1616 uint16_t mb9;
1617 uint16_t mb10;
1618 uint32_t reserved_2[2];
1619 uint8_t node_name[WWN_SIZE];
1620 uint8_t port_name[WWN_SIZE];
1621 };
1622
1623 /*
1624 * ISP request and response queue entry sizes
1625 */
1626 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1627 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1628
1629
1630 /*
1631 * 24 bit port ID type definition.
1632 */
1633 typedef union {
1634 uint32_t b24 : 24;
1635
1636 struct {
1637 #ifdef __BIG_ENDIAN
1638 uint8_t domain;
1639 uint8_t area;
1640 uint8_t al_pa;
1641 #elif defined(__LITTLE_ENDIAN)
1642 uint8_t al_pa;
1643 uint8_t area;
1644 uint8_t domain;
1645 #else
1646 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1647 #endif
1648 uint8_t rsvd_1;
1649 } b;
1650 } port_id_t;
1651 #define INVALID_PORT_ID 0xFFFFFF
1652
1653 /*
1654 * Switch info gathering structure.
1655 */
1656 typedef struct {
1657 port_id_t d_id;
1658 uint8_t node_name[WWN_SIZE];
1659 uint8_t port_name[WWN_SIZE];
1660 uint8_t fabric_port_name[WWN_SIZE];
1661 uint16_t fp_speed;
1662 uint8_t fc4_type;
1663 } sw_info_t;
1664
1665 /* FCP-4 types */
1666 #define FC4_TYPE_FCP_SCSI 0x08
1667 #define FC4_TYPE_OTHER 0x0
1668 #define FC4_TYPE_UNKNOWN 0xff
1669
1670 /*
1671 * Fibre channel port type.
1672 */
1673 typedef enum {
1674 FCT_UNKNOWN,
1675 FCT_RSCN,
1676 FCT_SWITCH,
1677 FCT_BROADCAST,
1678 FCT_INITIATOR,
1679 FCT_TARGET
1680 } fc_port_type_t;
1681
1682 /*
1683 * Fibre channel port structure.
1684 */
1685 typedef struct fc_port {
1686 struct list_head list;
1687 struct scsi_qla_host *vha;
1688
1689 uint8_t node_name[WWN_SIZE];
1690 uint8_t port_name[WWN_SIZE];
1691 port_id_t d_id;
1692 uint16_t loop_id;
1693 uint16_t old_loop_id;
1694
1695 uint8_t fcp_prio;
1696
1697 uint8_t fabric_port_name[WWN_SIZE];
1698 uint16_t fp_speed;
1699
1700 fc_port_type_t port_type;
1701
1702 atomic_t state;
1703 uint32_t flags;
1704
1705 int login_retry;
1706
1707 struct fc_rport *rport, *drport;
1708 u32 supported_classes;
1709
1710 uint16_t vp_idx;
1711 uint8_t fc4_type;
1712 } fc_port_t;
1713
1714 /*
1715 * Fibre channel port/lun states.
1716 */
1717 #define FCS_UNCONFIGURED 1
1718 #define FCS_DEVICE_DEAD 2
1719 #define FCS_DEVICE_LOST 3
1720 #define FCS_ONLINE 4
1721
1722 static const char * const port_state_str[] = {
1723 "Unknown",
1724 "UNCONFIGURED",
1725 "DEAD",
1726 "LOST",
1727 "ONLINE"
1728 };
1729
1730 /*
1731 * FC port flags.
1732 */
1733 #define FCF_FABRIC_DEVICE BIT_0
1734 #define FCF_LOGIN_NEEDED BIT_1
1735 #define FCF_FCP2_DEVICE BIT_2
1736 #define FCF_ASYNC_SENT BIT_3
1737
1738 /* No loop ID flag. */
1739 #define FC_NO_LOOP_ID 0x1000
1740
1741 /*
1742 * FC-CT interface
1743 *
1744 * NOTE: All structures are big-endian in form.
1745 */
1746
1747 #define CT_REJECT_RESPONSE 0x8001
1748 #define CT_ACCEPT_RESPONSE 0x8002
1749 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1750 #define CT_REASON_CANNOT_PERFORM 0x09
1751 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1752 #define CT_EXPL_ALREADY_REGISTERED 0x10
1753
1754 #define NS_N_PORT_TYPE 0x01
1755 #define NS_NL_PORT_TYPE 0x02
1756 #define NS_NX_PORT_TYPE 0x7F
1757
1758 #define GA_NXT_CMD 0x100
1759 #define GA_NXT_REQ_SIZE (16 + 4)
1760 #define GA_NXT_RSP_SIZE (16 + 620)
1761
1762 #define GID_PT_CMD 0x1A1
1763 #define GID_PT_REQ_SIZE (16 + 4)
1764 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1765
1766 #define GPN_ID_CMD 0x112
1767 #define GPN_ID_REQ_SIZE (16 + 4)
1768 #define GPN_ID_RSP_SIZE (16 + 8)
1769
1770 #define GNN_ID_CMD 0x113
1771 #define GNN_ID_REQ_SIZE (16 + 4)
1772 #define GNN_ID_RSP_SIZE (16 + 8)
1773
1774 #define GFT_ID_CMD 0x117
1775 #define GFT_ID_REQ_SIZE (16 + 4)
1776 #define GFT_ID_RSP_SIZE (16 + 32)
1777
1778 #define RFT_ID_CMD 0x217
1779 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1780 #define RFT_ID_RSP_SIZE 16
1781
1782 #define RFF_ID_CMD 0x21F
1783 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1784 #define RFF_ID_RSP_SIZE 16
1785
1786 #define RNN_ID_CMD 0x213
1787 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1788 #define RNN_ID_RSP_SIZE 16
1789
1790 #define RSNN_NN_CMD 0x239
1791 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1792 #define RSNN_NN_RSP_SIZE 16
1793
1794 #define GFPN_ID_CMD 0x11C
1795 #define GFPN_ID_REQ_SIZE (16 + 4)
1796 #define GFPN_ID_RSP_SIZE (16 + 8)
1797
1798 #define GPSC_CMD 0x127
1799 #define GPSC_REQ_SIZE (16 + 8)
1800 #define GPSC_RSP_SIZE (16 + 2 + 2)
1801
1802 #define GFF_ID_CMD 0x011F
1803 #define GFF_ID_REQ_SIZE (16 + 4)
1804 #define GFF_ID_RSP_SIZE (16 + 128)
1805
1806 /*
1807 * HBA attribute types.
1808 */
1809 #define FDMI_HBA_ATTR_COUNT 9
1810 #define FDMI_HBA_NODE_NAME 1
1811 #define FDMI_HBA_MANUFACTURER 2
1812 #define FDMI_HBA_SERIAL_NUMBER 3
1813 #define FDMI_HBA_MODEL 4
1814 #define FDMI_HBA_MODEL_DESCRIPTION 5
1815 #define FDMI_HBA_HARDWARE_VERSION 6
1816 #define FDMI_HBA_DRIVER_VERSION 7
1817 #define FDMI_HBA_OPTION_ROM_VERSION 8
1818 #define FDMI_HBA_FIRMWARE_VERSION 9
1819 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1820 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1821
1822 struct ct_fdmi_hba_attr {
1823 uint16_t type;
1824 uint16_t len;
1825 union {
1826 uint8_t node_name[WWN_SIZE];
1827 uint8_t manufacturer[32];
1828 uint8_t serial_num[8];
1829 uint8_t model[16];
1830 uint8_t model_desc[80];
1831 uint8_t hw_version[16];
1832 uint8_t driver_version[32];
1833 uint8_t orom_version[16];
1834 uint8_t fw_version[16];
1835 uint8_t os_version[128];
1836 uint8_t max_ct_len[4];
1837 } a;
1838 };
1839
1840 struct ct_fdmi_hba_attributes {
1841 uint32_t count;
1842 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1843 };
1844
1845 /*
1846 * Port attribute types.
1847 */
1848 #define FDMI_PORT_ATTR_COUNT 6
1849 #define FDMI_PORT_FC4_TYPES 1
1850 #define FDMI_PORT_SUPPORT_SPEED 2
1851 #define FDMI_PORT_CURRENT_SPEED 3
1852 #define FDMI_PORT_MAX_FRAME_SIZE 4
1853 #define FDMI_PORT_OS_DEVICE_NAME 5
1854 #define FDMI_PORT_HOST_NAME 6
1855
1856 #define FDMI_PORT_SPEED_1GB 0x1
1857 #define FDMI_PORT_SPEED_2GB 0x2
1858 #define FDMI_PORT_SPEED_10GB 0x4
1859 #define FDMI_PORT_SPEED_4GB 0x8
1860 #define FDMI_PORT_SPEED_8GB 0x10
1861 #define FDMI_PORT_SPEED_16GB 0x20
1862 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1863
1864 struct ct_fdmi_port_attr {
1865 uint16_t type;
1866 uint16_t len;
1867 union {
1868 uint8_t fc4_types[32];
1869 uint32_t sup_speed;
1870 uint32_t cur_speed;
1871 uint32_t max_frame_size;
1872 uint8_t os_dev_name[32];
1873 uint8_t host_name[32];
1874 } a;
1875 };
1876
1877 /*
1878 * Port Attribute Block.
1879 */
1880 struct ct_fdmi_port_attributes {
1881 uint32_t count;
1882 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1883 };
1884
1885 /* FDMI definitions. */
1886 #define GRHL_CMD 0x100
1887 #define GHAT_CMD 0x101
1888 #define GRPL_CMD 0x102
1889 #define GPAT_CMD 0x110
1890
1891 #define RHBA_CMD 0x200
1892 #define RHBA_RSP_SIZE 16
1893
1894 #define RHAT_CMD 0x201
1895 #define RPRT_CMD 0x210
1896
1897 #define RPA_CMD 0x211
1898 #define RPA_RSP_SIZE 16
1899
1900 #define DHBA_CMD 0x300
1901 #define DHBA_REQ_SIZE (16 + 8)
1902 #define DHBA_RSP_SIZE 16
1903
1904 #define DHAT_CMD 0x301
1905 #define DPRT_CMD 0x310
1906 #define DPA_CMD 0x311
1907
1908 /* CT command header -- request/response common fields */
1909 struct ct_cmd_hdr {
1910 uint8_t revision;
1911 uint8_t in_id[3];
1912 uint8_t gs_type;
1913 uint8_t gs_subtype;
1914 uint8_t options;
1915 uint8_t reserved;
1916 };
1917
1918 /* CT command request */
1919 struct ct_sns_req {
1920 struct ct_cmd_hdr header;
1921 uint16_t command;
1922 uint16_t max_rsp_size;
1923 uint8_t fragment_id;
1924 uint8_t reserved[3];
1925
1926 union {
1927 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1928 struct {
1929 uint8_t reserved;
1930 uint8_t port_id[3];
1931 } port_id;
1932
1933 struct {
1934 uint8_t port_type;
1935 uint8_t domain;
1936 uint8_t area;
1937 uint8_t reserved;
1938 } gid_pt;
1939
1940 struct {
1941 uint8_t reserved;
1942 uint8_t port_id[3];
1943 uint8_t fc4_types[32];
1944 } rft_id;
1945
1946 struct {
1947 uint8_t reserved;
1948 uint8_t port_id[3];
1949 uint16_t reserved2;
1950 uint8_t fc4_feature;
1951 uint8_t fc4_type;
1952 } rff_id;
1953
1954 struct {
1955 uint8_t reserved;
1956 uint8_t port_id[3];
1957 uint8_t node_name[8];
1958 } rnn_id;
1959
1960 struct {
1961 uint8_t node_name[8];
1962 uint8_t name_len;
1963 uint8_t sym_node_name[255];
1964 } rsnn_nn;
1965
1966 struct {
1967 uint8_t hba_indentifier[8];
1968 } ghat;
1969
1970 struct {
1971 uint8_t hba_identifier[8];
1972 uint32_t entry_count;
1973 uint8_t port_name[8];
1974 struct ct_fdmi_hba_attributes attrs;
1975 } rhba;
1976
1977 struct {
1978 uint8_t hba_identifier[8];
1979 struct ct_fdmi_hba_attributes attrs;
1980 } rhat;
1981
1982 struct {
1983 uint8_t port_name[8];
1984 struct ct_fdmi_port_attributes attrs;
1985 } rpa;
1986
1987 struct {
1988 uint8_t port_name[8];
1989 } dhba;
1990
1991 struct {
1992 uint8_t port_name[8];
1993 } dhat;
1994
1995 struct {
1996 uint8_t port_name[8];
1997 } dprt;
1998
1999 struct {
2000 uint8_t port_name[8];
2001 } dpa;
2002
2003 struct {
2004 uint8_t port_name[8];
2005 } gpsc;
2006
2007 struct {
2008 uint8_t reserved;
2009 uint8_t port_name[3];
2010 } gff_id;
2011 } req;
2012 };
2013
2014 /* CT command response header */
2015 struct ct_rsp_hdr {
2016 struct ct_cmd_hdr header;
2017 uint16_t response;
2018 uint16_t residual;
2019 uint8_t fragment_id;
2020 uint8_t reason_code;
2021 uint8_t explanation_code;
2022 uint8_t vendor_unique;
2023 };
2024
2025 struct ct_sns_gid_pt_data {
2026 uint8_t control_byte;
2027 uint8_t port_id[3];
2028 };
2029
2030 struct ct_sns_rsp {
2031 struct ct_rsp_hdr header;
2032
2033 union {
2034 struct {
2035 uint8_t port_type;
2036 uint8_t port_id[3];
2037 uint8_t port_name[8];
2038 uint8_t sym_port_name_len;
2039 uint8_t sym_port_name[255];
2040 uint8_t node_name[8];
2041 uint8_t sym_node_name_len;
2042 uint8_t sym_node_name[255];
2043 uint8_t init_proc_assoc[8];
2044 uint8_t node_ip_addr[16];
2045 uint8_t class_of_service[4];
2046 uint8_t fc4_types[32];
2047 uint8_t ip_address[16];
2048 uint8_t fabric_port_name[8];
2049 uint8_t reserved;
2050 uint8_t hard_address[3];
2051 } ga_nxt;
2052
2053 struct {
2054 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2055 } gid_pt;
2056
2057 struct {
2058 uint8_t port_name[8];
2059 } gpn_id;
2060
2061 struct {
2062 uint8_t node_name[8];
2063 } gnn_id;
2064
2065 struct {
2066 uint8_t fc4_types[32];
2067 } gft_id;
2068
2069 struct {
2070 uint32_t entry_count;
2071 uint8_t port_name[8];
2072 struct ct_fdmi_hba_attributes attrs;
2073 } ghat;
2074
2075 struct {
2076 uint8_t port_name[8];
2077 } gfpn_id;
2078
2079 struct {
2080 uint16_t speeds;
2081 uint16_t speed;
2082 } gpsc;
2083
2084 #define GFF_FCP_SCSI_OFFSET 7
2085 struct {
2086 uint8_t fc4_features[128];
2087 } gff_id;
2088 } rsp;
2089 };
2090
2091 struct ct_sns_pkt {
2092 union {
2093 struct ct_sns_req req;
2094 struct ct_sns_rsp rsp;
2095 } p;
2096 };
2097
2098 /*
2099 * SNS command structures -- for 2200 compatibility.
2100 */
2101 #define RFT_ID_SNS_SCMD_LEN 22
2102 #define RFT_ID_SNS_CMD_SIZE 60
2103 #define RFT_ID_SNS_DATA_SIZE 16
2104
2105 #define RNN_ID_SNS_SCMD_LEN 10
2106 #define RNN_ID_SNS_CMD_SIZE 36
2107 #define RNN_ID_SNS_DATA_SIZE 16
2108
2109 #define GA_NXT_SNS_SCMD_LEN 6
2110 #define GA_NXT_SNS_CMD_SIZE 28
2111 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2112
2113 #define GID_PT_SNS_SCMD_LEN 6
2114 #define GID_PT_SNS_CMD_SIZE 28
2115 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2116
2117 #define GPN_ID_SNS_SCMD_LEN 6
2118 #define GPN_ID_SNS_CMD_SIZE 28
2119 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2120
2121 #define GNN_ID_SNS_SCMD_LEN 6
2122 #define GNN_ID_SNS_CMD_SIZE 28
2123 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2124
2125 struct sns_cmd_pkt {
2126 union {
2127 struct {
2128 uint16_t buffer_length;
2129 uint16_t reserved_1;
2130 uint32_t buffer_address[2];
2131 uint16_t subcommand_length;
2132 uint16_t reserved_2;
2133 uint16_t subcommand;
2134 uint16_t size;
2135 uint32_t reserved_3;
2136 uint8_t param[36];
2137 } cmd;
2138
2139 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2140 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2141 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2142 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2143 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2144 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2145 } p;
2146 };
2147
2148 struct fw_blob {
2149 char *name;
2150 uint32_t segs[4];
2151 const struct firmware *fw;
2152 };
2153
2154 /* Return data from MBC_GET_ID_LIST call. */
2155 struct gid_list_info {
2156 uint8_t al_pa;
2157 uint8_t area;
2158 uint8_t domain;
2159 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2160 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2161 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2162 };
2163 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2164
2165 /* NPIV */
2166 typedef struct vport_info {
2167 uint8_t port_name[WWN_SIZE];
2168 uint8_t node_name[WWN_SIZE];
2169 int vp_id;
2170 uint16_t loop_id;
2171 unsigned long host_no;
2172 uint8_t port_id[3];
2173 int loop_state;
2174 } vport_info_t;
2175
2176 typedef struct vport_params {
2177 uint8_t port_name[WWN_SIZE];
2178 uint8_t node_name[WWN_SIZE];
2179 uint32_t options;
2180 #define VP_OPTS_RETRY_ENABLE BIT_0
2181 #define VP_OPTS_VP_DISABLE BIT_1
2182 } vport_params_t;
2183
2184 /* NPIV - return codes of VP create and modify */
2185 #define VP_RET_CODE_OK 0
2186 #define VP_RET_CODE_FATAL 1
2187 #define VP_RET_CODE_WRONG_ID 2
2188 #define VP_RET_CODE_WWPN 3
2189 #define VP_RET_CODE_RESOURCES 4
2190 #define VP_RET_CODE_NO_MEM 5
2191 #define VP_RET_CODE_NOT_FOUND 6
2192
2193 struct qla_hw_data;
2194 struct rsp_que;
2195 /*
2196 * ISP operations
2197 */
2198 struct isp_operations {
2199
2200 int (*pci_config) (struct scsi_qla_host *);
2201 void (*reset_chip) (struct scsi_qla_host *);
2202 int (*chip_diag) (struct scsi_qla_host *);
2203 void (*config_rings) (struct scsi_qla_host *);
2204 void (*reset_adapter) (struct scsi_qla_host *);
2205 int (*nvram_config) (struct scsi_qla_host *);
2206 void (*update_fw_options) (struct scsi_qla_host *);
2207 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2208
2209 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2210 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2211
2212 irq_handler_t intr_handler;
2213 void (*enable_intrs) (struct qla_hw_data *);
2214 void (*disable_intrs) (struct qla_hw_data *);
2215
2216 int (*abort_command) (srb_t *);
2217 int (*target_reset) (struct fc_port *, unsigned int, int);
2218 int (*lun_reset) (struct fc_port *, unsigned int, int);
2219 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2220 uint8_t, uint8_t, uint16_t *, uint8_t);
2221 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2222 uint8_t, uint8_t);
2223
2224 uint16_t (*calc_req_entries) (uint16_t);
2225 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2226 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2227 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2228 uint32_t);
2229
2230 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2231 uint32_t, uint32_t);
2232 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2233 uint32_t);
2234
2235 void (*fw_dump) (struct scsi_qla_host *, int);
2236
2237 int (*beacon_on) (struct scsi_qla_host *);
2238 int (*beacon_off) (struct scsi_qla_host *);
2239 void (*beacon_blink) (struct scsi_qla_host *);
2240
2241 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2242 uint32_t, uint32_t);
2243 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2244 uint32_t);
2245
2246 int (*get_flash_version) (struct scsi_qla_host *, void *);
2247 int (*start_scsi) (srb_t *);
2248 int (*abort_isp) (struct scsi_qla_host *);
2249 int (*iospace_config)(struct qla_hw_data*);
2250 };
2251
2252 /* MSI-X Support *************************************************************/
2253
2254 #define QLA_MSIX_CHIP_REV_24XX 3
2255 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2256 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2257
2258 #define QLA_MSIX_DEFAULT 0x00
2259 #define QLA_MSIX_RSP_Q 0x01
2260
2261 #define QLA_MIDX_DEFAULT 0
2262 #define QLA_MIDX_RSP_Q 1
2263 #define QLA_PCI_MSIX_CONTROL 0xa2
2264
2265 struct scsi_qla_host;
2266
2267 struct qla_msix_entry {
2268 int have_irq;
2269 uint32_t vector;
2270 uint16_t entry;
2271 struct rsp_que *rsp;
2272 };
2273
2274 #define WATCH_INTERVAL 1 /* number of seconds */
2275
2276 /* Work events. */
2277 enum qla_work_type {
2278 QLA_EVT_AEN,
2279 QLA_EVT_IDC_ACK,
2280 QLA_EVT_ASYNC_LOGIN,
2281 QLA_EVT_ASYNC_LOGIN_DONE,
2282 QLA_EVT_ASYNC_LOGOUT,
2283 QLA_EVT_ASYNC_LOGOUT_DONE,
2284 QLA_EVT_ASYNC_ADISC,
2285 QLA_EVT_ASYNC_ADISC_DONE,
2286 QLA_EVT_UEVENT,
2287 };
2288
2289
2290 struct qla_work_evt {
2291 struct list_head list;
2292 enum qla_work_type type;
2293 u32 flags;
2294 #define QLA_EVT_FLAG_FREE 0x1
2295
2296 union {
2297 struct {
2298 enum fc_host_event_code code;
2299 u32 data;
2300 } aen;
2301 struct {
2302 #define QLA_IDC_ACK_REGS 7
2303 uint16_t mb[QLA_IDC_ACK_REGS];
2304 } idc_ack;
2305 struct {
2306 struct fc_port *fcport;
2307 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2308 u16 data[2];
2309 } logio;
2310 struct {
2311 u32 code;
2312 #define QLA_UEVENT_CODE_FW_DUMP 0
2313 } uevent;
2314 } u;
2315 };
2316
2317 struct qla_chip_state_84xx {
2318 struct list_head list;
2319 struct kref kref;
2320
2321 void *bus;
2322 spinlock_t access_lock;
2323 struct mutex fw_update_mutex;
2324 uint32_t fw_update;
2325 uint32_t op_fw_version;
2326 uint32_t op_fw_size;
2327 uint32_t op_fw_seq_size;
2328 uint32_t diag_fw_version;
2329 uint32_t gold_fw_version;
2330 };
2331
2332 struct qla_statistics {
2333 uint32_t total_isp_aborts;
2334 uint64_t input_bytes;
2335 uint64_t output_bytes;
2336 };
2337
2338 /* Multi queue support */
2339 #define MBC_INITIALIZE_MULTIQ 0x1f
2340 #define QLA_QUE_PAGE 0X1000
2341 #define QLA_MQ_SIZE 32
2342 #define QLA_MAX_QUEUES 256
2343 #define ISP_QUE_REG(ha, id) \
2344 ((ha->mqenable) ? \
2345 ((void *)(ha->mqiobase) +\
2346 (QLA_QUE_PAGE * id)) :\
2347 ((void *)(ha->iobase)))
2348 #define QLA_REQ_QUE_ID(tag) \
2349 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2350 #define QLA_DEFAULT_QUE_QOS 5
2351 #define QLA_PRECONFIG_VPORTS 32
2352 #define QLA_MAX_VPORTS_QLA24XX 128
2353 #define QLA_MAX_VPORTS_QLA25XX 256
2354 /* Response queue data structure */
2355 struct rsp_que {
2356 dma_addr_t dma;
2357 response_t *ring;
2358 response_t *ring_ptr;
2359 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2360 uint32_t __iomem *rsp_q_out;
2361 uint16_t ring_index;
2362 uint16_t out_ptr;
2363 uint16_t length;
2364 uint16_t options;
2365 uint16_t rid;
2366 uint16_t id;
2367 uint16_t vp_idx;
2368 struct qla_hw_data *hw;
2369 struct qla_msix_entry *msix;
2370 struct req_que *req;
2371 srb_t *status_srb; /* status continuation entry */
2372 struct work_struct q_work;
2373 };
2374
2375 /* Request queue data structure */
2376 struct req_que {
2377 dma_addr_t dma;
2378 request_t *ring;
2379 request_t *ring_ptr;
2380 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2381 uint32_t __iomem *req_q_out;
2382 uint16_t ring_index;
2383 uint16_t in_ptr;
2384 uint16_t cnt;
2385 uint16_t length;
2386 uint16_t options;
2387 uint16_t rid;
2388 uint16_t id;
2389 uint16_t qos;
2390 uint16_t vp_idx;
2391 struct rsp_que *rsp;
2392 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2393 uint32_t current_outstanding_cmd;
2394 int max_q_depth;
2395 };
2396
2397 /* Place holder for FW buffer parameters */
2398 struct qlfc_fw {
2399 void *fw_buf;
2400 dma_addr_t fw_dma;
2401 uint32_t len;
2402 };
2403
2404 /*
2405 * Qlogic host adapter specific data structure.
2406 */
2407 struct qla_hw_data {
2408 struct pci_dev *pdev;
2409 /* SRB cache. */
2410 #define SRB_MIN_REQ 128
2411 mempool_t *srb_mempool;
2412
2413 volatile struct {
2414 uint32_t mbox_int :1;
2415 uint32_t mbox_busy :1;
2416 uint32_t disable_risc_code_load :1;
2417 uint32_t enable_64bit_addressing :1;
2418 uint32_t enable_lip_reset :1;
2419 uint32_t enable_target_reset :1;
2420 uint32_t enable_lip_full_login :1;
2421 uint32_t enable_led_scheme :1;
2422
2423 uint32_t msi_enabled :1;
2424 uint32_t msix_enabled :1;
2425 uint32_t disable_serdes :1;
2426 uint32_t gpsc_supported :1;
2427 uint32_t npiv_supported :1;
2428 uint32_t pci_channel_io_perm_failure :1;
2429 uint32_t fce_enabled :1;
2430 uint32_t fac_supported :1;
2431
2432 uint32_t chip_reset_done :1;
2433 uint32_t port0 :1;
2434 uint32_t running_gold_fw :1;
2435 uint32_t eeh_busy :1;
2436 uint32_t cpu_affinity_enabled :1;
2437 uint32_t disable_msix_handshake :1;
2438 uint32_t fcp_prio_enabled :1;
2439 uint32_t isp82xx_fw_hung:1;
2440
2441 uint32_t quiesce_owner:1;
2442 uint32_t thermal_supported:1;
2443 uint32_t isp82xx_reset_hdlr_active:1;
2444 uint32_t isp82xx_reset_owner:1;
2445 /* 28 bits */
2446 } flags;
2447
2448 /* This spinlock is used to protect "io transactions", you must
2449 * acquire it before doing any IO to the card, eg with RD_REG*() and
2450 * WRT_REG*() for the duration of your entire commandtransaction.
2451 *
2452 * This spinlock is of lower priority than the io request lock.
2453 */
2454
2455 spinlock_t hardware_lock ____cacheline_aligned;
2456 int bars;
2457 int mem_only;
2458 device_reg_t __iomem *iobase; /* Base I/O address */
2459 resource_size_t pio_address;
2460
2461 #define MIN_IOBASE_LEN 0x100
2462 /* Multi queue data structs */
2463 device_reg_t __iomem *mqiobase;
2464 uint16_t msix_count;
2465 uint8_t mqenable;
2466 struct req_que **req_q_map;
2467 struct rsp_que **rsp_q_map;
2468 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2469 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2470 uint8_t max_req_queues;
2471 uint8_t max_rsp_queues;
2472 struct qla_npiv_entry *npiv_info;
2473 uint16_t nvram_npiv_size;
2474
2475 uint16_t switch_cap;
2476 #define FLOGI_SEQ_DEL BIT_8
2477 #define FLOGI_MID_SUPPORT BIT_10
2478 #define FLOGI_VSAN_SUPPORT BIT_12
2479 #define FLOGI_SP_SUPPORT BIT_13
2480
2481 uint8_t port_no; /* Physical port of adapter */
2482
2483 /* Timeout timers. */
2484 uint8_t loop_down_abort_time; /* port down timer */
2485 atomic_t loop_down_timer; /* loop down timer */
2486 uint8_t link_down_timeout; /* link down timeout */
2487 uint16_t max_loop_id;
2488
2489 uint16_t fb_rev;
2490 uint16_t min_external_loopid; /* First external loop Id */
2491
2492 #define PORT_SPEED_UNKNOWN 0xFFFF
2493 #define PORT_SPEED_1GB 0x00
2494 #define PORT_SPEED_2GB 0x01
2495 #define PORT_SPEED_4GB 0x03
2496 #define PORT_SPEED_8GB 0x04
2497 #define PORT_SPEED_10GB 0x13
2498 uint16_t link_data_rate; /* F/W operating speed */
2499
2500 uint8_t current_topology;
2501 uint8_t prev_topology;
2502 #define ISP_CFG_NL 1
2503 #define ISP_CFG_N 2
2504 #define ISP_CFG_FL 4
2505 #define ISP_CFG_F 8
2506
2507 uint8_t operating_mode; /* F/W operating mode */
2508 #define LOOP 0
2509 #define P2P 1
2510 #define LOOP_P2P 2
2511 #define P2P_LOOP 3
2512 uint8_t interrupts_on;
2513 uint32_t isp_abort_cnt;
2514
2515 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2516 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2517 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2518 uint32_t device_type;
2519 #define DT_ISP2100 BIT_0
2520 #define DT_ISP2200 BIT_1
2521 #define DT_ISP2300 BIT_2
2522 #define DT_ISP2312 BIT_3
2523 #define DT_ISP2322 BIT_4
2524 #define DT_ISP6312 BIT_5
2525 #define DT_ISP6322 BIT_6
2526 #define DT_ISP2422 BIT_7
2527 #define DT_ISP2432 BIT_8
2528 #define DT_ISP5422 BIT_9
2529 #define DT_ISP5432 BIT_10
2530 #define DT_ISP2532 BIT_11
2531 #define DT_ISP8432 BIT_12
2532 #define DT_ISP8001 BIT_13
2533 #define DT_ISP8021 BIT_14
2534 #define DT_ISP_LAST (DT_ISP8021 << 1)
2535
2536 #define DT_T10_PI BIT_25
2537 #define DT_IIDMA BIT_26
2538 #define DT_FWI2 BIT_27
2539 #define DT_ZIO_SUPPORTED BIT_28
2540 #define DT_OEM_001 BIT_29
2541 #define DT_ISP2200A BIT_30
2542 #define DT_EXTENDED_IDS BIT_31
2543 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2544 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2545 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2546 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2547 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2548 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2549 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2550 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2551 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2552 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2553 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2554 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2555 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2556 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2557 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2558 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2559
2560 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2561 IS_QLA6312(ha) || IS_QLA6322(ha))
2562 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2563 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2564 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2565 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2566 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2567 IS_QLA84XX(ha))
2568 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2569 #define IS_QLA8XXX_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha))
2570 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2571 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2572 IS_QLA82XX(ha))
2573 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha))
2574 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2575 (ha)->flags.msix_enabled)
2576 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2577 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2578 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2579
2580 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
2581 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2582 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2583 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2584 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2585 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2586
2587 /* HBA serial number */
2588 uint8_t serial0;
2589 uint8_t serial1;
2590 uint8_t serial2;
2591
2592 /* NVRAM configuration data */
2593 #define MAX_NVRAM_SIZE 4096
2594 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2595 uint16_t nvram_size;
2596 uint16_t nvram_base;
2597 void *nvram;
2598 uint16_t vpd_size;
2599 uint16_t vpd_base;
2600 void *vpd;
2601
2602 uint16_t loop_reset_delay;
2603 uint8_t retry_count;
2604 uint8_t login_timeout;
2605 uint16_t r_a_tov;
2606 int port_down_retry_count;
2607 uint8_t mbx_count;
2608
2609 uint32_t login_retry_count;
2610 /* SNS command interfaces. */
2611 ms_iocb_entry_t *ms_iocb;
2612 dma_addr_t ms_iocb_dma;
2613 struct ct_sns_pkt *ct_sns;
2614 dma_addr_t ct_sns_dma;
2615 /* SNS command interfaces for 2200. */
2616 struct sns_cmd_pkt *sns_cmd;
2617 dma_addr_t sns_cmd_dma;
2618
2619 #define SFP_DEV_SIZE 256
2620 #define SFP_BLOCK_SIZE 64
2621 void *sfp_data;
2622 dma_addr_t sfp_data_dma;
2623
2624 uint8_t *edc_data;
2625 dma_addr_t edc_data_dma;
2626 uint16_t edc_data_len;
2627
2628 #define XGMAC_DATA_SIZE 4096
2629 void *xgmac_data;
2630 dma_addr_t xgmac_data_dma;
2631
2632 #define DCBX_TLV_DATA_SIZE 4096
2633 void *dcbx_tlv;
2634 dma_addr_t dcbx_tlv_dma;
2635
2636 struct task_struct *dpc_thread;
2637 uint8_t dpc_active; /* DPC routine is active */
2638
2639 dma_addr_t gid_list_dma;
2640 struct gid_list_info *gid_list;
2641 int gid_list_info_size;
2642
2643 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2644 #define DMA_POOL_SIZE 256
2645 struct dma_pool *s_dma_pool;
2646
2647 dma_addr_t init_cb_dma;
2648 init_cb_t *init_cb;
2649 int init_cb_size;
2650 dma_addr_t ex_init_cb_dma;
2651 struct ex_init_cb_81xx *ex_init_cb;
2652
2653 void *async_pd;
2654 dma_addr_t async_pd_dma;
2655
2656 /* These are used by mailbox operations. */
2657 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2658
2659 mbx_cmd_t *mcp;
2660 unsigned long mbx_cmd_flags;
2661 #define MBX_INTERRUPT 1
2662 #define MBX_INTR_WAIT 2
2663 #define MBX_UPDATE_FLASH_ACTIVE 3
2664
2665 struct mutex vport_lock; /* Virtual port synchronization */
2666 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
2667 struct completion mbx_cmd_comp; /* Serialize mbx access */
2668 struct completion mbx_intr_comp; /* Used for completion notification */
2669 struct completion dcbx_comp; /* For set port config notification */
2670 int notify_dcbx_comp;
2671
2672 /* Basic firmware related information. */
2673 uint16_t fw_major_version;
2674 uint16_t fw_minor_version;
2675 uint16_t fw_subminor_version;
2676 uint16_t fw_attributes;
2677 uint32_t fw_memory_size;
2678 uint32_t fw_transfer_size;
2679 uint32_t fw_srisc_address;
2680 #define RISC_START_ADDRESS_2100 0x1000
2681 #define RISC_START_ADDRESS_2300 0x800
2682 #define RISC_START_ADDRESS_2400 0x100000
2683 uint16_t fw_xcb_count;
2684
2685 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2686 uint8_t fw_seriallink_options[4];
2687 uint16_t fw_seriallink_options24[4];
2688
2689 uint8_t mpi_version[3];
2690 uint32_t mpi_capabilities;
2691 uint8_t phy_version[3];
2692
2693 /* Firmware dump information. */
2694 struct qla2xxx_fw_dump *fw_dump;
2695 uint32_t fw_dump_len;
2696 int fw_dumped;
2697 int fw_dump_reading;
2698 dma_addr_t eft_dma;
2699 void *eft;
2700
2701 uint32_t chain_offset;
2702 struct dentry *dfs_dir;
2703 struct dentry *dfs_fce;
2704 dma_addr_t fce_dma;
2705 void *fce;
2706 uint32_t fce_bufs;
2707 uint16_t fce_mb[8];
2708 uint64_t fce_wr, fce_rd;
2709 struct mutex fce_mutex;
2710
2711 uint32_t pci_attr;
2712 uint16_t chip_revision;
2713
2714 uint16_t product_id[4];
2715
2716 uint8_t model_number[16+1];
2717 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2718 char model_desc[80];
2719 uint8_t adapter_id[16+1];
2720
2721 /* Option ROM information. */
2722 char *optrom_buffer;
2723 uint32_t optrom_size;
2724 int optrom_state;
2725 #define QLA_SWAITING 0
2726 #define QLA_SREADING 1
2727 #define QLA_SWRITING 2
2728 uint32_t optrom_region_start;
2729 uint32_t optrom_region_size;
2730
2731 /* PCI expansion ROM image information. */
2732 #define ROM_CODE_TYPE_BIOS 0
2733 #define ROM_CODE_TYPE_FCODE 1
2734 #define ROM_CODE_TYPE_EFI 3
2735 uint8_t bios_revision[2];
2736 uint8_t efi_revision[2];
2737 uint8_t fcode_revision[16];
2738 uint32_t fw_revision[4];
2739
2740 uint32_t gold_fw_version[4];
2741
2742 /* Offsets for flash/nvram access (set to ~0 if not used). */
2743 uint32_t flash_conf_off;
2744 uint32_t flash_data_off;
2745 uint32_t nvram_conf_off;
2746 uint32_t nvram_data_off;
2747
2748 uint32_t fdt_wrt_disable;
2749 uint32_t fdt_erase_cmd;
2750 uint32_t fdt_block_size;
2751 uint32_t fdt_unprotect_sec_cmd;
2752 uint32_t fdt_protect_sec_cmd;
2753
2754 uint32_t flt_region_flt;
2755 uint32_t flt_region_fdt;
2756 uint32_t flt_region_boot;
2757 uint32_t flt_region_fw;
2758 uint32_t flt_region_vpd_nvram;
2759 uint32_t flt_region_vpd;
2760 uint32_t flt_region_nvram;
2761 uint32_t flt_region_npiv_conf;
2762 uint32_t flt_region_gold_fw;
2763 uint32_t flt_region_fcp_prio;
2764 uint32_t flt_region_bootload;
2765
2766 /* Needed for BEACON */
2767 uint16_t beacon_blink_led;
2768 uint8_t beacon_color_state;
2769 #define QLA_LED_GRN_ON 0x01
2770 #define QLA_LED_YLW_ON 0x02
2771 #define QLA_LED_ABR_ON 0x04
2772 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2773 /* ISP2322: red, green, amber. */
2774 uint16_t zio_mode;
2775 uint16_t zio_timer;
2776 struct fc_host_statistics fc_host_stat;
2777
2778 struct qla_msix_entry *msix_entries;
2779
2780 struct list_head vp_list; /* list of VP */
2781 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2782 sizeof(unsigned long)];
2783 uint16_t num_vhosts; /* number of vports created */
2784 uint16_t num_vsans; /* number of vsan created */
2785 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2786 int cur_vport_count;
2787
2788 struct qla_chip_state_84xx *cs84xx;
2789 struct qla_statistics qla_stats;
2790 struct isp_operations *isp_ops;
2791 struct workqueue_struct *wq;
2792 struct qlfc_fw fw_buf;
2793
2794 /* FCP_CMND priority support */
2795 struct qla_fcp_prio_cfg *fcp_prio_cfg;
2796
2797 struct dma_pool *dl_dma_pool;
2798 #define DSD_LIST_DMA_POOL_SIZE 512
2799
2800 struct dma_pool *fcp_cmnd_dma_pool;
2801 mempool_t *ctx_mempool;
2802 #define FCP_CMND_DMA_POOL_SIZE 512
2803
2804 unsigned long nx_pcibase; /* Base I/O address */
2805 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
2806 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
2807
2808 uint32_t crb_win;
2809 uint32_t curr_window;
2810 uint32_t ddr_mn_window;
2811 unsigned long mn_win_crb;
2812 unsigned long ms_win_crb;
2813 int qdr_sn_window;
2814 uint32_t nx_dev_init_timeout;
2815 uint32_t nx_reset_timeout;
2816 rwlock_t hw_lock;
2817 uint16_t portnum; /* port number */
2818 int link_width;
2819 struct fw_blob *hablob;
2820 struct qla82xx_legacy_intr_set nx_legacy_intr;
2821
2822 uint16_t gbl_dsd_inuse;
2823 uint16_t gbl_dsd_avail;
2824 struct list_head gbl_dsd_list;
2825 #define NUM_DSD_CHAIN 4096
2826
2827 uint8_t fw_type;
2828 __le32 file_prd_off; /* File firmware product offset */
2829
2830 uint32_t md_template_size;
2831 void *md_tmplt_hdr;
2832 dma_addr_t md_tmplt_hdr_dma;
2833 void *md_dump;
2834 uint32_t md_dump_size;
2835 };
2836
2837 /*
2838 * Qlogic scsi host structure
2839 */
2840 typedef struct scsi_qla_host {
2841 struct list_head list;
2842 struct list_head vp_fcports; /* list of fcports */
2843 struct list_head work_list;
2844 spinlock_t work_lock;
2845
2846 /* Commonly used flags and state information. */
2847 struct Scsi_Host *host;
2848 unsigned long host_no;
2849 uint8_t host_str[16];
2850
2851 volatile struct {
2852 uint32_t init_done :1;
2853 uint32_t online :1;
2854 uint32_t rscn_queue_overflow :1;
2855 uint32_t reset_active :1;
2856
2857 uint32_t management_server_logged_in :1;
2858 uint32_t process_response_queue :1;
2859 uint32_t difdix_supported:1;
2860 uint32_t delete_progress:1;
2861 } flags;
2862
2863 atomic_t loop_state;
2864 #define LOOP_TIMEOUT 1
2865 #define LOOP_DOWN 2
2866 #define LOOP_UP 3
2867 #define LOOP_UPDATE 4
2868 #define LOOP_READY 5
2869 #define LOOP_DEAD 6
2870
2871 unsigned long dpc_flags;
2872 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2873 #define RESET_ACTIVE 1
2874 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2875 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2876 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2877 #define LOOP_RESYNC_ACTIVE 5
2878 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2879 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2880 #define RELOGIN_NEEDED 8
2881 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2882 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2883 #define BEACON_BLINK_NEEDED 11
2884 #define REGISTER_FDMI_NEEDED 12
2885 #define FCPORT_UPDATE_NEEDED 13
2886 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2887 #define UNLOADING 15
2888 #define NPIV_CONFIG_NEEDED 16
2889 #define ISP_UNRECOVERABLE 17
2890 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
2891 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
2892 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
2893
2894 uint32_t device_flags;
2895 #define SWITCH_FOUND BIT_0
2896 #define DFLG_NO_CABLE BIT_1
2897 #define DFLG_DEV_FAILED BIT_5
2898
2899 /* ISP configuration data. */
2900 uint16_t loop_id; /* Host adapter loop id */
2901
2902 port_id_t d_id; /* Host adapter port id */
2903 uint8_t marker_needed;
2904 uint16_t mgmt_svr_loop_id;
2905
2906
2907
2908 /* RSCN queue. */
2909 uint32_t rscn_queue[MAX_RSCN_COUNT];
2910 uint8_t rscn_in_ptr;
2911 uint8_t rscn_out_ptr;
2912
2913 /* Timeout timers. */
2914 uint8_t loop_down_abort_time; /* port down timer */
2915 atomic_t loop_down_timer; /* loop down timer */
2916 uint8_t link_down_timeout; /* link down timeout */
2917
2918 uint32_t timer_active;
2919 struct timer_list timer;
2920
2921 uint8_t node_name[WWN_SIZE];
2922 uint8_t port_name[WWN_SIZE];
2923 uint8_t fabric_node_name[WWN_SIZE];
2924
2925 uint16_t fcoe_vlan_id;
2926 uint16_t fcoe_fcf_idx;
2927 uint8_t fcoe_vn_port_mac[6];
2928
2929 uint32_t vp_abort_cnt;
2930
2931 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2932 uint16_t vp_idx; /* vport ID */
2933
2934 unsigned long vp_flags;
2935 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2936 #define VP_CREATE_NEEDED 1
2937 #define VP_BIND_NEEDED 2
2938 #define VP_DELETE_NEEDED 3
2939 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2940 atomic_t vp_state;
2941 #define VP_OFFLINE 0
2942 #define VP_ACTIVE 1
2943 #define VP_FAILED 2
2944 // #define VP_DISABLE 3
2945 uint16_t vp_err_state;
2946 uint16_t vp_prev_err_state;
2947 #define VP_ERR_UNKWN 0
2948 #define VP_ERR_PORTDWN 1
2949 #define VP_ERR_FAB_UNSUPPORTED 2
2950 #define VP_ERR_FAB_NORESOURCES 3
2951 #define VP_ERR_FAB_LOGOUT 4
2952 #define VP_ERR_ADAP_NORESOURCES 5
2953 struct qla_hw_data *hw;
2954 struct req_que *req;
2955 int fw_heartbeat_counter;
2956 int seconds_since_last_heartbeat;
2957
2958 atomic_t vref_count;
2959 } scsi_qla_host_t;
2960
2961 /*
2962 * Macros to help code, maintain, etc.
2963 */
2964 #define LOOP_TRANSITION(ha) \
2965 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2966 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2967 atomic_read(&ha->loop_state) == LOOP_DOWN)
2968
2969 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
2970 atomic_inc(&__vha->vref_count); \
2971 mb(); \
2972 if (__vha->flags.delete_progress) { \
2973 atomic_dec(&__vha->vref_count); \
2974 __bail = 1; \
2975 } else { \
2976 __bail = 0; \
2977 } \
2978 } while (0)
2979
2980 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
2981 atomic_dec(&__vha->vref_count); \
2982 } while (0)
2983
2984 /*
2985 * qla2x00 local function return status codes
2986 */
2987 #define MBS_MASK 0x3fff
2988
2989 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2990 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2991 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2992 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2993 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2994 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2995 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2996 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2997 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2998 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2999
3000 #define QLA_FUNCTION_TIMEOUT 0x100
3001 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
3002 #define QLA_FUNCTION_FAILED 0x102
3003 #define QLA_MEMORY_ALLOC_FAILED 0x103
3004 #define QLA_LOCK_TIMEOUT 0x104
3005 #define QLA_ABORTED 0x105
3006 #define QLA_SUSPENDED 0x106
3007 #define QLA_BUSY 0x107
3008 #define QLA_RSCNS_HANDLED 0x108
3009 #define QLA_ALREADY_REGISTERED 0x109
3010
3011 #define NVRAM_DELAY() udelay(10)
3012
3013 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
3014
3015 /*
3016 * Flash support definitions
3017 */
3018 #define OPTROM_SIZE_2300 0x20000
3019 #define OPTROM_SIZE_2322 0x100000
3020 #define OPTROM_SIZE_24XX 0x100000
3021 #define OPTROM_SIZE_25XX 0x200000
3022 #define OPTROM_SIZE_81XX 0x400000
3023 #define OPTROM_SIZE_82XX 0x800000
3024
3025 #define OPTROM_BURST_SIZE 0x1000
3026 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3027
3028 #define QLA_DSDS_PER_IOCB 37
3029
3030 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3031
3032 #define QLA_SG_ALL 1024
3033
3034 enum nexus_wait_type {
3035 WAIT_HOST = 0,
3036 WAIT_TARGET,
3037 WAIT_LUN,
3038 };
3039
3040 #include "qla_gbl.h"
3041 #include "qla_dbg.h"
3042 #include "qla_inline.h"
3043 #endif