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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / scsi / qla2xxx / qla_fw.h
blobaa69486dc06487107aee2e029a2d545906ae2cb8
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_FW_H
8 #define __QLA_FW_H
9
10 #define MBS_CHECKSUM_ERROR 0x4010
11 #define MBS_INVALID_PRODUCT_KEY 0x4020
12
13 /*
14 * Firmware Options.
15 */
16 #define FO1_ENABLE_PUREX BIT_10
17 #define FO1_DISABLE_LED_CTRL BIT_6
18 #define FO1_ENABLE_8016 BIT_0
19 #define FO2_ENABLE_SEL_CLASS2 BIT_5
20 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
21 #define FO3_HOLD_STS_IOCB BIT_12
22
23 /*
24 * Port Database structure definition for ISP 24xx.
25 */
26 #define PDO_FORCE_ADISC BIT_1
27 #define PDO_FORCE_PLOGI BIT_0
28
29
30 #define PORT_DATABASE_24XX_SIZE 64
31 struct port_database_24xx {
32 uint16_t flags;
33 #define PDF_TASK_RETRY_ID BIT_14
34 #define PDF_FC_TAPE BIT_7
35 #define PDF_ACK0_CAPABLE BIT_6
36 #define PDF_FCP2_CONF BIT_5
37 #define PDF_CLASS_2 BIT_4
38 #define PDF_HARD_ADDR BIT_1
39
40 uint8_t current_login_state;
41 uint8_t last_login_state;
42 #define PDS_PLOGI_PENDING 0x03
43 #define PDS_PLOGI_COMPLETE 0x04
44 #define PDS_PRLI_PENDING 0x05
45 #define PDS_PRLI_COMPLETE 0x06
46 #define PDS_PORT_UNAVAILABLE 0x07
47 #define PDS_PRLO_PENDING 0x09
48 #define PDS_LOGO_PENDING 0x11
49 #define PDS_PRLI2_PENDING 0x12
50
51 uint8_t hard_address[3];
52 uint8_t reserved_1;
53
54 uint8_t port_id[3];
55 uint8_t sequence_id;
56
57 uint16_t port_timer;
58
59 uint16_t nport_handle; /* N_PORT handle. */
60
61 uint16_t receive_data_size;
62 uint16_t reserved_2;
63
64 uint8_t prli_svc_param_word_0[2]; /* Big endian */
65 /* Bits 15-0 of word 0 */
66 uint8_t prli_svc_param_word_3[2]; /* Big endian */
67 /* Bits 15-0 of word 3 */
68
69 uint8_t port_name[WWN_SIZE];
70 uint8_t node_name[WWN_SIZE];
71
72 uint8_t reserved_3[24];
73 };
74
75 struct vp_database_24xx {
76 uint16_t vp_status;
77 uint8_t options;
78 uint8_t id;
79 uint8_t port_name[WWN_SIZE];
80 uint8_t node_name[WWN_SIZE];
81 uint16_t port_id_low;
82 uint16_t port_id_high;
83 };
84
85 struct nvram_24xx {
86 /* NVRAM header. */
87 uint8_t id[4];
88 uint16_t nvram_version;
89 uint16_t reserved_0;
90
91 /* Firmware Initialization Control Block. */
92 uint16_t version;
93 uint16_t reserved_1;
94 uint16_t frame_payload_size;
95 uint16_t execution_throttle;
96 uint16_t exchange_count;
97 uint16_t hard_address;
98
99 uint8_t port_name[WWN_SIZE];
100 uint8_t node_name[WWN_SIZE];
101
102 uint16_t login_retry_count;
103 uint16_t link_down_on_nos;
104 uint16_t interrupt_delay_timer;
105 uint16_t login_timeout;
106
107 uint32_t firmware_options_1;
108 uint32_t firmware_options_2;
109 uint32_t firmware_options_3;
110
111 /* Offset 56. */
112
113 /*
114 * BIT 0 = Control Enable
115 * BIT 1-15 =
116 *
117 * BIT 0-7 = Reserved
118 * BIT 8-10 = Output Swing 1G
119 * BIT 11-13 = Output Emphasis 1G
120 * BIT 14-15 = Reserved
121 *
122 * BIT 0-7 = Reserved
123 * BIT 8-10 = Output Swing 2G
124 * BIT 11-13 = Output Emphasis 2G
125 * BIT 14-15 = Reserved
126 *
127 * BIT 0-7 = Reserved
128 * BIT 8-10 = Output Swing 4G
129 * BIT 11-13 = Output Emphasis 4G
130 * BIT 14-15 = Reserved
131 */
132 uint16_t seriallink_options[4];
133
134 uint16_t reserved_2[16];
135
136 /* Offset 96. */
137 uint16_t reserved_3[16];
138
139 /* PCIe table entries. */
140 uint16_t reserved_4[16];
141
142 /* Offset 160. */
143 uint16_t reserved_5[16];
144
145 /* Offset 192. */
146 uint16_t reserved_6[16];
147
148 /* Offset 224. */
149 uint16_t reserved_7[16];
150
151 /*
152 * BIT 0 = Enable spinup delay
153 * BIT 1 = Disable BIOS
154 * BIT 2 = Enable Memory Map BIOS
155 * BIT 3 = Enable Selectable Boot
156 * BIT 4 = Disable RISC code load
157 * BIT 5 = Disable Serdes
158 * BIT 6 =
159 * BIT 7 =
160 *
161 * BIT 8 =
162 * BIT 9 =
163 * BIT 10 = Enable lip full login
164 * BIT 11 = Enable target reset
165 * BIT 12 =
166 * BIT 13 =
167 * BIT 14 =
168 * BIT 15 = Enable alternate WWN
169 *
170 * BIT 16-31 =
171 */
172 uint32_t host_p;
173
174 uint8_t alternate_port_name[WWN_SIZE];
175 uint8_t alternate_node_name[WWN_SIZE];
176
177 uint8_t boot_port_name[WWN_SIZE];
178 uint16_t boot_lun_number;
179 uint16_t reserved_8;
180
181 uint8_t alt1_boot_port_name[WWN_SIZE];
182 uint16_t alt1_boot_lun_number;
183 uint16_t reserved_9;
184
185 uint8_t alt2_boot_port_name[WWN_SIZE];
186 uint16_t alt2_boot_lun_number;
187 uint16_t reserved_10;
188
189 uint8_t alt3_boot_port_name[WWN_SIZE];
190 uint16_t alt3_boot_lun_number;
191 uint16_t reserved_11;
192
193 /*
194 * BIT 0 = Selective Login
195 * BIT 1 = Alt-Boot Enable
196 * BIT 2 = Reserved
197 * BIT 3 = Boot Order List
198 * BIT 4 = Reserved
199 * BIT 5 = Selective LUN
200 * BIT 6 = Reserved
201 * BIT 7-31 =
202 */
203 uint32_t efi_parameters;
204
205 uint8_t reset_delay;
206 uint8_t reserved_12;
207 uint16_t reserved_13;
208
209 uint16_t boot_id_number;
210 uint16_t reserved_14;
211
212 uint16_t max_luns_per_target;
213 uint16_t reserved_15;
214
215 uint16_t port_down_retry_count;
216 uint16_t link_down_timeout;
217
218 /* FCode parameters. */
219 uint16_t fcode_parameter;
220
221 uint16_t reserved_16[3];
222
223 /* Offset 352. */
224 uint8_t prev_drv_ver_major;
225 uint8_t prev_drv_ver_submajob;
226 uint8_t prev_drv_ver_minor;
227 uint8_t prev_drv_ver_subminor;
228
229 uint16_t prev_bios_ver_major;
230 uint16_t prev_bios_ver_minor;
231
232 uint16_t prev_efi_ver_major;
233 uint16_t prev_efi_ver_minor;
234
235 uint16_t prev_fw_ver_major;
236 uint8_t prev_fw_ver_minor;
237 uint8_t prev_fw_ver_subminor;
238
239 uint16_t reserved_17[8];
240
241 /* Offset 384. */
242 uint16_t reserved_18[16];
243
244 /* Offset 416. */
245 uint16_t reserved_19[16];
246
247 /* Offset 448. */
248 uint16_t reserved_20[16];
249
250 /* Offset 480. */
251 uint8_t model_name[16];
252
253 uint16_t reserved_21[2];
254
255 /* Offset 500. */
256 /* HW Parameter Block. */
257 uint16_t pcie_table_sig;
258 uint16_t pcie_table_offset;
259
260 uint16_t subsystem_vendor_id;
261 uint16_t subsystem_device_id;
262
263 uint32_t checksum;
264 };
265
266 /*
267 * ISP Initialization Control Block.
268 * Little endian except where noted.
269 */
270 #define ICB_VERSION 1
271 struct init_cb_24xx {
272 uint16_t version;
273 uint16_t reserved_1;
274
275 uint16_t frame_payload_size;
276 uint16_t execution_throttle;
277 uint16_t exchange_count;
278
279 uint16_t hard_address;
280
281 uint8_t port_name[WWN_SIZE]; /* Big endian. */
282 uint8_t node_name[WWN_SIZE]; /* Big endian. */
283
284 uint16_t response_q_inpointer;
285 uint16_t request_q_outpointer;
286
287 uint16_t login_retry_count;
288
289 uint16_t prio_request_q_outpointer;
290
291 uint16_t response_q_length;
292 uint16_t request_q_length;
293
294 uint16_t link_down_on_nos; /* Milliseconds. */
295
296 uint16_t prio_request_q_length;
297
298 uint32_t request_q_address[2];
299 uint32_t response_q_address[2];
300 uint32_t prio_request_q_address[2];
301
302 uint16_t msix;
303 uint8_t reserved_2[6];
304
305 uint16_t atio_q_inpointer;
306 uint16_t atio_q_length;
307 uint32_t atio_q_address[2];
308
309 uint16_t interrupt_delay_timer; /* 100us increments. */
310 uint16_t login_timeout;
311
312 /*
313 * BIT 0 = Enable Hard Loop Id
314 * BIT 1 = Enable Fairness
315 * BIT 2 = Enable Full-Duplex
316 * BIT 3 = Reserved
317 * BIT 4 = Enable Target Mode
318 * BIT 5 = Disable Initiator Mode
319 * BIT 6 = Reserved
320 * BIT 7 = Reserved
321 *
322 * BIT 8 = Reserved
323 * BIT 9 = Non Participating LIP
324 * BIT 10 = Descending Loop ID Search
325 * BIT 11 = Acquire Loop ID in LIPA
326 * BIT 12 = Reserved
327 * BIT 13 = Full Login after LIP
328 * BIT 14 = Node Name Option
329 * BIT 15-31 = Reserved
330 */
331 uint32_t firmware_options_1;
332
333 /*
334 * BIT 0 = Operation Mode bit 0
335 * BIT 1 = Operation Mode bit 1
336 * BIT 2 = Operation Mode bit 2
337 * BIT 3 = Operation Mode bit 3
338 * BIT 4 = Connection Options bit 0
339 * BIT 5 = Connection Options bit 1
340 * BIT 6 = Connection Options bit 2
341 * BIT 7 = Enable Non part on LIHA failure
342 *
343 * BIT 8 = Enable Class 2
344 * BIT 9 = Enable ACK0
345 * BIT 10 = Reserved
346 * BIT 11 = Enable FC-SP Security
347 * BIT 12 = FC Tape Enable
348 * BIT 13 = Reserved
349 * BIT 14 = Enable Target PRLI Control
350 * BIT 15-31 = Reserved
351 */
352 uint32_t firmware_options_2;
353
354 /*
355 * BIT 0 = Reserved
356 * BIT 1 = Soft ID only
357 * BIT 2 = Reserved
358 * BIT 3 = Reserved
359 * BIT 4 = FCP RSP Payload bit 0
360 * BIT 5 = FCP RSP Payload bit 1
361 * BIT 6 = Enable Receive Out-of-Order data frame handling
362 * BIT 7 = Disable Automatic PLOGI on Local Loop
363 *
364 * BIT 8 = Reserved
365 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
366 * BIT 10 = Reserved
367 * BIT 11 = Reserved
368 * BIT 12 = Reserved
369 * BIT 13 = Data Rate bit 0
370 * BIT 14 = Data Rate bit 1
371 * BIT 15 = Data Rate bit 2
372 * BIT 16 = Enable 75 ohm Termination Select
373 * BIT 17-31 = Reserved
374 */
375 uint32_t firmware_options_3;
376 uint16_t qos;
377 uint16_t rid;
378 uint8_t reserved_3[20];
379 };
380
381 /*
382 * ISP queue - command entry structure definition.
383 */
384 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
385 struct cmd_type_6 {
386 uint8_t entry_type; /* Entry type. */
387 uint8_t entry_count; /* Entry count. */
388 uint8_t sys_define; /* System defined. */
389 uint8_t entry_status; /* Entry Status. */
390
391 uint32_t handle; /* System handle. */
392
393 uint16_t nport_handle; /* N_PORT handle. */
394 uint16_t timeout; /* Command timeout. */
395
396 uint16_t dseg_count; /* Data segment count. */
397
398 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
399
400 struct scsi_lun lun; /* FCP LUN (BE). */
401
402 uint16_t control_flags; /* Control flags. */
403 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
404 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
405 #define CF_READ_DATA BIT_1
406 #define CF_WRITE_DATA BIT_0
407
408 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
409 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
410
411 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
412
413 uint32_t byte_count; /* Total byte count. */
414
415 uint8_t port_id[3]; /* PortID of destination port. */
416 uint8_t vp_index;
417
418 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
419 uint32_t fcp_data_dseg_len; /* Data segment length. */
420 };
421
422 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
423 struct cmd_type_7 {
424 uint8_t entry_type; /* Entry type. */
425 uint8_t entry_count; /* Entry count. */
426 uint8_t sys_define; /* System defined. */
427 uint8_t entry_status; /* Entry Status. */
428
429 uint32_t handle; /* System handle. */
430
431 uint16_t nport_handle; /* N_PORT handle. */
432 uint16_t timeout; /* Command timeout. */
433 #define FW_MAX_TIMEOUT 0x1999
434
435 uint16_t dseg_count; /* Data segment count. */
436 uint16_t reserved_1;
437
438 struct scsi_lun lun; /* FCP LUN (BE). */
439
440 uint16_t task_mgmt_flags; /* Task management flags. */
441 #define TMF_CLEAR_ACA BIT_14
442 #define TMF_TARGET_RESET BIT_13
443 #define TMF_LUN_RESET BIT_12
444 #define TMF_CLEAR_TASK_SET BIT_10
445 #define TMF_ABORT_TASK_SET BIT_9
446 #define TMF_DSD_LIST_ENABLE BIT_2
447 #define TMF_READ_DATA BIT_1
448 #define TMF_WRITE_DATA BIT_0
449
450 uint8_t task;
451 #define TSK_SIMPLE 0
452 #define TSK_HEAD_OF_QUEUE 1
453 #define TSK_ORDERED 2
454 #define TSK_ACA 4
455 #define TSK_UNTAGGED 5
456
457 uint8_t crn;
458
459 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
460 uint32_t byte_count; /* Total byte count. */
461
462 uint8_t port_id[3]; /* PortID of destination port. */
463 uint8_t vp_index;
464
465 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
466 uint32_t dseg_0_len; /* Data segment 0 length. */
467 };
468
469 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
470 * (T10-DIF) */
471 struct cmd_type_crc_2 {
472 uint8_t entry_type; /* Entry type. */
473 uint8_t entry_count; /* Entry count. */
474 uint8_t sys_define; /* System defined. */
475 uint8_t entry_status; /* Entry Status. */
476
477 uint32_t handle; /* System handle. */
478
479 uint16_t nport_handle; /* N_PORT handle. */
480 uint16_t timeout; /* Command timeout. */
481
482 uint16_t dseg_count; /* Data segment count. */
483
484 uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */
485
486 struct scsi_lun lun; /* FCP LUN (BE). */
487
488 uint16_t control_flags; /* Control flags. */
489
490 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
491 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
492
493 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
494
495 uint32_t byte_count; /* Total byte count. */
496
497 uint8_t port_id[3]; /* PortID of destination port. */
498 uint8_t vp_index;
499
500 uint32_t crc_context_address[2]; /* Data segment address. */
501 uint16_t crc_context_len; /* Data segment length. */
502 uint16_t reserved_1; /* MUST be set to 0. */
503 };
504
505
506 /*
507 * ISP queue - status entry structure definition.
508 */
509 #define STATUS_TYPE 0x03 /* Status entry. */
510 struct sts_entry_24xx {
511 uint8_t entry_type; /* Entry type. */
512 uint8_t entry_count; /* Entry count. */
513 uint8_t sys_define; /* System defined. */
514 uint8_t entry_status; /* Entry Status. */
515
516 uint32_t handle; /* System handle. */
517
518 uint16_t comp_status; /* Completion status. */
519 uint16_t ox_id; /* OX_ID used by the firmware. */
520
521 uint32_t residual_len; /* FW calc residual transfer length. */
522
523 uint16_t reserved_1;
524 uint16_t state_flags; /* State flags. */
525 #define SF_TRANSFERRED_DATA BIT_11
526 #define SF_FCP_RSP_DMA BIT_0
527
528 uint16_t reserved_2;
529 uint16_t scsi_status; /* SCSI status. */
530 #define SS_CONFIRMATION_REQ BIT_12
531
532 uint32_t rsp_residual_count; /* FCP RSP residual count. */
533
534 uint32_t sense_len; /* FCP SENSE length. */
535 uint32_t rsp_data_len; /* FCP response data length. */
536 uint8_t data[28]; /* FCP response/sense information. */
537 /*
538 * If DIF Error is set in comp_status, these additional fields are
539 * defined:
540 *
541 * !!! NOTE: Firmware sends expected/actual DIF data in big endian
542 * format; but all of the "data" field gets swab32-d in the beginning
543 * of qla2x00_status_entry().
544 *
545 * &data[10] : uint8_t report_runt_bg[2]; - computed guard
546 * &data[12] : uint8_t actual_dif[8]; - DIF Data received
547 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed
548 */
549 };
550
551
552 /*
553 * Status entry completion status
554 */
555 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
556 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
557 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
558 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
559 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
560
561 /*
562 * ISP queue - marker entry structure definition.
563 */
564 #define MARKER_TYPE 0x04 /* Marker entry. */
565 struct mrk_entry_24xx {
566 uint8_t entry_type; /* Entry type. */
567 uint8_t entry_count; /* Entry count. */
568 uint8_t handle_count; /* Handle count. */
569 uint8_t entry_status; /* Entry Status. */
570
571 uint32_t handle; /* System handle. */
572
573 uint16_t nport_handle; /* N_PORT handle. */
574
575 uint8_t modifier; /* Modifier (7-0). */
576 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
577 #define MK_SYNC_ID 1 /* Synchronize ID */
578 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
579 uint8_t reserved_1;
580
581 uint8_t reserved_2;
582 uint8_t vp_index;
583
584 uint16_t reserved_3;
585
586 uint8_t lun[8]; /* FCP LUN (BE). */
587 uint8_t reserved_4[40];
588 };
589
590 /*
591 * ISP queue - CT Pass-Through entry structure definition.
592 */
593 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
594 struct ct_entry_24xx {
595 uint8_t entry_type; /* Entry type. */
596 uint8_t entry_count; /* Entry count. */
597 uint8_t sys_define; /* System Defined. */
598 uint8_t entry_status; /* Entry Status. */
599
600 uint32_t handle; /* System handle. */
601
602 uint16_t comp_status; /* Completion status. */
603
604 uint16_t nport_handle; /* N_PORT handle. */
605
606 uint16_t cmd_dsd_count;
607
608 uint8_t vp_index;
609 uint8_t reserved_1;
610
611 uint16_t timeout; /* Command timeout. */
612 uint16_t reserved_2;
613
614 uint16_t rsp_dsd_count;
615
616 uint8_t reserved_3[10];
617
618 uint32_t rsp_byte_count;
619 uint32_t cmd_byte_count;
620
621 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
622 uint32_t dseg_0_len; /* Data segment 0 length. */
623 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
624 uint32_t dseg_1_len; /* Data segment 1 length. */
625 };
626
627 /*
628 * ISP queue - ELS Pass-Through entry structure definition.
629 */
630 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
631 struct els_entry_24xx {
632 uint8_t entry_type; /* Entry type. */
633 uint8_t entry_count; /* Entry count. */
634 uint8_t sys_define; /* System Defined. */
635 uint8_t entry_status; /* Entry Status. */
636
637 uint32_t handle; /* System handle. */
638
639 uint16_t reserved_1;
640
641 uint16_t nport_handle; /* N_PORT handle. */
642
643 uint16_t tx_dsd_count;
644
645 uint8_t vp_index;
646 uint8_t sof_type;
647 #define EST_SOFI3 (1 << 4)
648 #define EST_SOFI2 (3 << 4)
649
650 uint32_t rx_xchg_address; /* Receive exchange address. */
651 uint16_t rx_dsd_count;
652
653 uint8_t opcode;
654 uint8_t reserved_2;
655
656 uint8_t port_id[3];
657 uint8_t reserved_3;
658
659 uint16_t reserved_4;
660
661 uint16_t control_flags; /* Control flags. */
662 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
663 #define EPD_ELS_COMMAND (0 << 13)
664 #define EPD_ELS_ACC (1 << 13)
665 #define EPD_ELS_RJT (2 << 13)
666 #define EPD_RX_XCHG (3 << 13)
667 #define ECF_CLR_PASSTHRU_PEND BIT_12
668 #define ECF_INCL_FRAME_HDR BIT_11
669
670 uint32_t rx_byte_count;
671 uint32_t tx_byte_count;
672
673 uint32_t tx_address[2]; /* Data segment 0 address. */
674 uint32_t tx_len; /* Data segment 0 length. */
675 uint32_t rx_address[2]; /* Data segment 1 address. */
676 uint32_t rx_len; /* Data segment 1 length. */
677 };
678
679 struct els_sts_entry_24xx {
680 uint8_t entry_type; /* Entry type. */
681 uint8_t entry_count; /* Entry count. */
682 uint8_t sys_define; /* System Defined. */
683 uint8_t entry_status; /* Entry Status. */
684
685 uint32_t handle; /* System handle. */
686
687 uint16_t comp_status;
688
689 uint16_t nport_handle; /* N_PORT handle. */
690
691 uint16_t reserved_1;
692
693 uint8_t vp_index;
694 uint8_t sof_type;
695
696 uint32_t rx_xchg_address; /* Receive exchange address. */
697 uint16_t reserved_2;
698
699 uint8_t opcode;
700 uint8_t reserved_3;
701
702 uint8_t port_id[3];
703 uint8_t reserved_4;
704
705 uint16_t reserved_5;
706
707 uint16_t control_flags; /* Control flags. */
708 uint32_t total_byte_count;
709 uint32_t error_subcode_1;
710 uint32_t error_subcode_2;
711 };
712 /*
713 * ISP queue - Mailbox Command entry structure definition.
714 */
715 #define MBX_IOCB_TYPE 0x39
716 struct mbx_entry_24xx {
717 uint8_t entry_type; /* Entry type. */
718 uint8_t entry_count; /* Entry count. */
719 uint8_t handle_count; /* Handle count. */
720 uint8_t entry_status; /* Entry Status. */
721
722 uint32_t handle; /* System handle. */
723
724 uint16_t mbx[28];
725 };
726
727
728 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
729 struct logio_entry_24xx {
730 uint8_t entry_type; /* Entry type. */
731 uint8_t entry_count; /* Entry count. */
732 uint8_t sys_define; /* System defined. */
733 uint8_t entry_status; /* Entry Status. */
734
735 uint32_t handle; /* System handle. */
736
737 uint16_t comp_status; /* Completion status. */
738 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
739
740 uint16_t nport_handle; /* N_PORT handle. */
741
742 uint16_t control_flags; /* Control flags. */
743 /* Modifiers. */
744 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */
745 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
746 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
747 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
748 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
749 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
750 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
751 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
752 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
753 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
754 /* Commands. */
755 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
756 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
757 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
758 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
759 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
760 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
761 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
762
763 uint8_t vp_index;
764 uint8_t reserved_1;
765
766 uint8_t port_id[3]; /* PortID of destination port. */
767
768 uint8_t rsp_size; /* Response size in 32bit words. */
769
770 uint32_t io_parameter[11]; /* General I/O parameters. */
771 #define LSC_SCODE_NOLINK 0x01
772 #define LSC_SCODE_NOIOCB 0x02
773 #define LSC_SCODE_NOXCB 0x03
774 #define LSC_SCODE_CMD_FAILED 0x04
775 #define LSC_SCODE_NOFABRIC 0x05
776 #define LSC_SCODE_FW_NOT_READY 0x07
777 #define LSC_SCODE_NOT_LOGGED_IN 0x09
778 #define LSC_SCODE_NOPCB 0x0A
779
780 #define LSC_SCODE_ELS_REJECT 0x18
781 #define LSC_SCODE_CMD_PARAM_ERR 0x19
782 #define LSC_SCODE_PORTID_USED 0x1A
783 #define LSC_SCODE_NPORT_USED 0x1B
784 #define LSC_SCODE_NONPORT 0x1C
785 #define LSC_SCODE_LOGGED_IN 0x1D
786 #define LSC_SCODE_NOFLOGI_ACC 0x1F
787 };
788
789 #define TSK_MGMT_IOCB_TYPE 0x14
790 struct tsk_mgmt_entry {
791 uint8_t entry_type; /* Entry type. */
792 uint8_t entry_count; /* Entry count. */
793 uint8_t handle_count; /* Handle count. */
794 uint8_t entry_status; /* Entry Status. */
795
796 uint32_t handle; /* System handle. */
797
798 uint16_t nport_handle; /* N_PORT handle. */
799
800 uint16_t reserved_1;
801
802 uint16_t delay; /* Activity delay in seconds. */
803
804 uint16_t timeout; /* Command timeout. */
805
806 struct scsi_lun lun; /* FCP LUN (BE). */
807
808 uint32_t control_flags; /* Control Flags. */
809 #define TCF_NOTMCMD_TO_TARGET BIT_31
810 #define TCF_LUN_RESET BIT_4
811 #define TCF_ABORT_TASK_SET BIT_3
812 #define TCF_CLEAR_TASK_SET BIT_2
813 #define TCF_TARGET_RESET BIT_1
814 #define TCF_CLEAR_ACA BIT_0
815
816 uint8_t reserved_2[20];
817
818 uint8_t port_id[3]; /* PortID of destination port. */
819 uint8_t vp_index;
820
821 uint8_t reserved_3[12];
822 };
823
824 #define ABORT_IOCB_TYPE 0x33
825 struct abort_entry_24xx {
826 uint8_t entry_type; /* Entry type. */
827 uint8_t entry_count; /* Entry count. */
828 uint8_t handle_count; /* Handle count. */
829 uint8_t entry_status; /* Entry Status. */
830
831 uint32_t handle; /* System handle. */
832
833 uint16_t nport_handle; /* N_PORT handle. */
834 /* or Completion status. */
835
836 uint16_t options; /* Options. */
837 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
838
839 uint32_t handle_to_abort; /* System handle to abort. */
840
841 uint16_t req_que_no;
842 uint8_t reserved_1[30];
843
844 uint8_t port_id[3]; /* PortID of destination port. */
845 uint8_t vp_index;
846
847 uint8_t reserved_2[12];
848 };
849
850 /*
851 * ISP I/O Register Set structure definitions.
852 */
853 struct device_reg_24xx {
854 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
855 #define FARX_DATA_FLAG BIT_31
856 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
857 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
858 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
859 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
860
861 #define FA_NVRAM_FUNC0_ADDR 0x80
862 #define FA_NVRAM_FUNC1_ADDR 0x180
863
864 #define FA_NVRAM_VPD_SIZE 0x200
865 #define FA_NVRAM_VPD0_ADDR 0x00
866 #define FA_NVRAM_VPD1_ADDR 0x100
867
868 #define FA_BOOT_CODE_ADDR 0x00000
869 /*
870 * RISC code begins at offset 512KB
871 * within flash. Consisting of two
872 * contiguous RISC code segments.
873 */
874 #define FA_RISC_CODE_ADDR 0x20000
875 #define FA_RISC_CODE_SEGMENTS 2
876
877 #define FA_FLASH_DESCR_ADDR_24 0x11000
878 #define FA_FLASH_LAYOUT_ADDR_24 0x11400
879 #define FA_NPIV_CONF0_ADDR_24 0x16000
880 #define FA_NPIV_CONF1_ADDR_24 0x17000
881
882 #define FA_FW_AREA_ADDR 0x40000
883 #define FA_VPD_NVRAM_ADDR 0x48000
884 #define FA_FEATURE_ADDR 0x4C000
885 #define FA_FLASH_DESCR_ADDR 0x50000
886 #define FA_FLASH_LAYOUT_ADDR 0x50400
887 #define FA_HW_EVENT0_ADDR 0x54000
888 #define FA_HW_EVENT1_ADDR 0x54400
889 #define FA_HW_EVENT_SIZE 0x200
890 #define FA_HW_EVENT_ENTRY_SIZE 4
891 #define FA_NPIV_CONF0_ADDR 0x5C000
892 #define FA_NPIV_CONF1_ADDR 0x5D000
893 #define FA_FCP_PRIO0_ADDR 0x10000
894 #define FA_FCP_PRIO1_ADDR 0x12000
895
896 /*
897 * Flash Error Log Event Codes.
898 */
899 #define HW_EVENT_RESET_ERR 0xF00B
900 #define HW_EVENT_ISP_ERR 0xF020
901 #define HW_EVENT_PARITY_ERR 0xF022
902 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
903 #define HW_EVENT_FLASH_FW_ERR 0xF024
904
905 uint32_t flash_data; /* Flash/NVRAM BIOS data. */
906
907 uint32_t ctrl_status; /* Control/Status. */
908 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
909 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
910 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
911 #define CSRX_FUNCTION BIT_15 /* Function number. */
912 /* PCI-X Bus Mode. */
913 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
914 #define PBM_PCI_33MHZ (0 << 8)
915 #define PBM_PCIX_M1_66MHZ (1 << 8)
916 #define PBM_PCIX_M1_100MHZ (2 << 8)
917 #define PBM_PCIX_M1_133MHZ (3 << 8)
918 #define PBM_PCIX_M2_66MHZ (5 << 8)
919 #define PBM_PCIX_M2_100MHZ (6 << 8)
920 #define PBM_PCIX_M2_133MHZ (7 << 8)
921 #define PBM_PCI_66MHZ (8 << 8)
922 /* Max Write Burst byte count. */
923 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
924 #define MWB_512_BYTES (0 << 4)
925 #define MWB_1024_BYTES (1 << 4)
926 #define MWB_2048_BYTES (2 << 4)
927 #define MWB_4096_BYTES (3 << 4)
928
929 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
930 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
931 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
932
933 uint32_t ictrl; /* Interrupt control. */
934 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
935
936 uint32_t istatus; /* Interrupt status. */
937 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
938
939 uint32_t unused_1[2]; /* Gap. */
940
941 /* Request Queue. */
942 uint32_t req_q_in; /* In-Pointer. */
943 uint32_t req_q_out; /* Out-Pointer. */
944 /* Response Queue. */
945 uint32_t rsp_q_in; /* In-Pointer. */
946 uint32_t rsp_q_out; /* Out-Pointer. */
947 /* Priority Request Queue. */
948 uint32_t preq_q_in; /* In-Pointer. */
949 uint32_t preq_q_out; /* Out-Pointer. */
950
951 uint32_t unused_2[2]; /* Gap. */
952
953 /* ATIO Queue. */
954 uint32_t atio_q_in; /* In-Pointer. */
955 uint32_t atio_q_out; /* Out-Pointer. */
956
957 uint32_t host_status;
958 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
959 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
960
961 uint32_t hccr; /* Host command & control register. */
962 /* HCCR statuses. */
963 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
964 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
965 /* HCCR commands. */
966 /* NOOP. */
967 #define HCCRX_NOOP 0x00000000
968 /* Set RISC Reset. */
969 #define HCCRX_SET_RISC_RESET 0x10000000
970 /* Clear RISC Reset. */
971 #define HCCRX_CLR_RISC_RESET 0x20000000
972 /* Set RISC Pause. */
973 #define HCCRX_SET_RISC_PAUSE 0x30000000
974 /* Releases RISC Pause. */
975 #define HCCRX_REL_RISC_PAUSE 0x40000000
976 /* Set HOST to RISC interrupt. */
977 #define HCCRX_SET_HOST_INT 0x50000000
978 /* Clear HOST to RISC interrupt. */
979 #define HCCRX_CLR_HOST_INT 0x60000000
980 /* Clear RISC to PCI interrupt. */
981 #define HCCRX_CLR_RISC_INT 0xA0000000
982
983 uint32_t gpiod; /* GPIO Data register. */
984
985 /* LED update mask. */
986 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
987 /* Data update mask. */
988 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
989 /* Data update mask. */
990 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
991 /* LED control mask. */
992 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
993 /* LED bit values. Color names as
994 * referenced in fw spec.
995 */
996 #define GPDX_LED_YELLOW_ON BIT_2
997 #define GPDX_LED_GREEN_ON BIT_3
998 #define GPDX_LED_AMBER_ON BIT_4
999 /* Data in/out. */
1000 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1001
1002 uint32_t gpioe; /* GPIO Enable register. */
1003 /* Enable update mask. */
1004 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1005 /* Enable update mask. */
1006 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1007 /* Enable. */
1008 #define GPEX_ENABLE (BIT_1|BIT_0)
1009
1010 uint32_t iobase_addr; /* I/O Bus Base Address register. */
1011
1012 uint32_t unused_3[10]; /* Gap. */
1013
1014 uint16_t mailbox0;
1015 uint16_t mailbox1;
1016 uint16_t mailbox2;
1017 uint16_t mailbox3;
1018 uint16_t mailbox4;
1019 uint16_t mailbox5;
1020 uint16_t mailbox6;
1021 uint16_t mailbox7;
1022 uint16_t mailbox8;
1023 uint16_t mailbox9;
1024 uint16_t mailbox10;
1025 uint16_t mailbox11;
1026 uint16_t mailbox12;
1027 uint16_t mailbox13;
1028 uint16_t mailbox14;
1029 uint16_t mailbox15;
1030 uint16_t mailbox16;
1031 uint16_t mailbox17;
1032 uint16_t mailbox18;
1033 uint16_t mailbox19;
1034 uint16_t mailbox20;
1035 uint16_t mailbox21;
1036 uint16_t mailbox22;
1037 uint16_t mailbox23;
1038 uint16_t mailbox24;
1039 uint16_t mailbox25;
1040 uint16_t mailbox26;
1041 uint16_t mailbox27;
1042 uint16_t mailbox28;
1043 uint16_t mailbox29;
1044 uint16_t mailbox30;
1045 uint16_t mailbox31;
1046
1047 uint32_t iobase_window;
1048 uint32_t iobase_c4;
1049 uint32_t iobase_c8;
1050 uint32_t unused_4_1[6]; /* Gap. */
1051 uint32_t iobase_q;
1052 uint32_t unused_5[2]; /* Gap. */
1053 uint32_t iobase_select;
1054 uint32_t unused_6[2]; /* Gap. */
1055 uint32_t iobase_sdata;
1056 };
1057
1058 /* Trace Control *************************************************************/
1059
1060 #define TC_AEN_DISABLE 0
1061
1062 #define TC_EFT_ENABLE 4
1063 #define TC_EFT_DISABLE 5
1064
1065 #define TC_FCE_ENABLE 8
1066 #define TC_FCE_OPTIONS 0
1067 #define TC_FCE_DEFAULT_RX_SIZE 2112
1068 #define TC_FCE_DEFAULT_TX_SIZE 2112
1069 #define TC_FCE_DISABLE 9
1070 #define TC_FCE_DISABLE_TRACE BIT_0
1071
1072 /* MID Support ***************************************************************/
1073
1074 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */
1075 #define MAX_MULTI_ID_FABRIC 256 /* ... */
1076
1077 #define for_each_mapped_vp_idx(_ha, _idx) \
1078 for (_idx = find_next_bit((_ha)->vp_idx_map, \
1079 (_ha)->max_npiv_vports + 1, 1); \
1080 _idx <= (_ha)->max_npiv_vports; \
1081 _idx = find_next_bit((_ha)->vp_idx_map, \
1082 (_ha)->max_npiv_vports + 1, _idx + 1)) \
1083
1084 struct mid_conf_entry_24xx {
1085 uint16_t reserved_1;
1086
1087 /*
1088 * BIT 0 = Enable Hard Loop Id
1089 * BIT 1 = Acquire Loop ID in LIPA
1090 * BIT 2 = ID not Acquired
1091 * BIT 3 = Enable VP
1092 * BIT 4 = Enable Initiator Mode
1093 * BIT 5 = Disable Target Mode
1094 * BIT 6-7 = Reserved
1095 */
1096 uint8_t options;
1097
1098 uint8_t hard_address;
1099
1100 uint8_t port_name[WWN_SIZE];
1101 uint8_t node_name[WWN_SIZE];
1102 };
1103
1104 struct mid_init_cb_24xx {
1105 struct init_cb_24xx init_cb;
1106
1107 uint16_t count;
1108 uint16_t options;
1109
1110 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1111 };
1112
1113
1114 struct mid_db_entry_24xx {
1115 uint16_t status;
1116 #define MDBS_NON_PARTIC BIT_3
1117 #define MDBS_ID_ACQUIRED BIT_1
1118 #define MDBS_ENABLED BIT_0
1119
1120 uint8_t options;
1121 uint8_t hard_address;
1122
1123 uint8_t port_name[WWN_SIZE];
1124 uint8_t node_name[WWN_SIZE];
1125
1126 uint8_t port_id[3];
1127 uint8_t reserved_1;
1128 };
1129
1130 /*
1131 * Virtual Port Control IOCB
1132 */
1133 #define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */
1134 struct vp_ctrl_entry_24xx {
1135 uint8_t entry_type; /* Entry type. */
1136 uint8_t entry_count; /* Entry count. */
1137 uint8_t sys_define; /* System defined. */
1138 uint8_t entry_status; /* Entry Status. */
1139
1140 uint32_t handle; /* System handle. */
1141
1142 uint16_t vp_idx_failed;
1143
1144 uint16_t comp_status; /* Completion status. */
1145 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1146 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1147 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1148
1149 uint16_t command;
1150 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1151 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1152 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1153 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1154 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1155
1156 uint16_t vp_count;
1157
1158 uint8_t vp_idx_map[16];
1159 uint16_t flags;
1160 uint16_t id;
1161 uint16_t reserved_4;
1162 uint16_t hopct;
1163 uint8_t reserved_5[24];
1164 };
1165
1166 /*
1167 * Modify Virtual Port Configuration IOCB
1168 */
1169 #define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */
1170 struct vp_config_entry_24xx {
1171 uint8_t entry_type; /* Entry type. */
1172 uint8_t entry_count; /* Entry count. */
1173 uint8_t handle_count;
1174 uint8_t entry_status; /* Entry Status. */
1175
1176 uint32_t handle; /* System handle. */
1177
1178 uint16_t flags;
1179 #define CS_VF_BIND_VPORTS_TO_VF BIT_0
1180 #define CS_VF_SET_QOS_OF_VPORTS BIT_1
1181 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1182
1183 uint16_t comp_status; /* Completion status. */
1184 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1185 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1186 #define CS_VCT_ERROR 0x03 /* Unknown error. */
1187 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1188 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1189
1190 uint8_t command;
1191 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
1192 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1193
1194 uint8_t vp_count;
1195
1196 uint8_t vp_index1;
1197 uint8_t vp_index2;
1198
1199 uint8_t options_idx1;
1200 uint8_t hard_address_idx1;
1201 uint16_t reserved_vp1;
1202 uint8_t port_name_idx1[WWN_SIZE];
1203 uint8_t node_name_idx1[WWN_SIZE];
1204
1205 uint8_t options_idx2;
1206 uint8_t hard_address_idx2;
1207 uint16_t reserved_vp2;
1208 uint8_t port_name_idx2[WWN_SIZE];
1209 uint8_t node_name_idx2[WWN_SIZE];
1210 uint16_t id;
1211 uint16_t reserved_4;
1212 uint16_t hopct;
1213 uint8_t reserved_5[2];
1214 };
1215
1216 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1217 struct vp_rpt_id_entry_24xx {
1218 uint8_t entry_type; /* Entry type. */
1219 uint8_t entry_count; /* Entry count. */
1220 uint8_t sys_define; /* System defined. */
1221 uint8_t entry_status; /* Entry Status. */
1222
1223 uint32_t handle; /* System handle. */
1224
1225 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */
1226 /* Format 1 -- | VP count |. */
1227 uint16_t vp_idx; /* Format 0 -- Reserved. */
1228 /* Format 1 -- VP status and index. */
1229
1230 uint8_t port_id[3];
1231 uint8_t format;
1232
1233 uint8_t vp_idx_map[16];
1234
1235 uint8_t reserved_4[32];
1236 };
1237
1238 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
1239 struct vf_evfp_entry_24xx {
1240 uint8_t entry_type; /* Entry type. */
1241 uint8_t entry_count; /* Entry count. */
1242 uint8_t sys_define; /* System defined. */
1243 uint8_t entry_status; /* Entry Status. */
1244
1245 uint32_t handle; /* System handle. */
1246 uint16_t comp_status; /* Completion status. */
1247 uint16_t timeout; /* timeout */
1248 uint16_t adim_tagging_mode;
1249
1250 uint16_t vfport_id;
1251 uint32_t exch_addr;
1252
1253 uint16_t nport_handle; /* N_PORT handle. */
1254 uint16_t control_flags;
1255 uint32_t io_parameter_0;
1256 uint32_t io_parameter_1;
1257 uint32_t tx_address[2]; /* Data segment 0 address. */
1258 uint32_t tx_len; /* Data segment 0 length. */
1259 uint32_t rx_address[2]; /* Data segment 1 address. */
1260 uint32_t rx_len; /* Data segment 1 length. */
1261 };
1262
1263 /* END MID Support ***********************************************************/
1264
1265 /* Flash Description Table ***************************************************/
1266
1267 struct qla_fdt_layout {
1268 uint8_t sig[4];
1269 uint16_t version;
1270 uint16_t len;
1271 uint16_t checksum;
1272 uint8_t unused1[2];
1273 uint8_t model[16];
1274 uint16_t man_id;
1275 uint16_t id;
1276 uint8_t flags;
1277 uint8_t erase_cmd;
1278 uint8_t alt_erase_cmd;
1279 uint8_t wrt_enable_cmd;
1280 uint8_t wrt_enable_bits;
1281 uint8_t wrt_sts_reg_cmd;
1282 uint8_t unprotect_sec_cmd;
1283 uint8_t read_man_id_cmd;
1284 uint32_t block_size;
1285 uint32_t alt_block_size;
1286 uint32_t flash_size;
1287 uint32_t wrt_enable_data;
1288 uint8_t read_id_addr_len;
1289 uint8_t wrt_disable_bits;
1290 uint8_t read_dev_id_len;
1291 uint8_t chip_erase_cmd;
1292 uint16_t read_timeout;
1293 uint8_t protect_sec_cmd;
1294 uint8_t unused2[65];
1295 };
1296
1297 /* Flash Layout Table ********************************************************/
1298
1299 struct qla_flt_location {
1300 uint8_t sig[4];
1301 uint16_t start_lo;
1302 uint16_t start_hi;
1303 uint8_t version;
1304 uint8_t unused[5];
1305 uint16_t checksum;
1306 };
1307
1308 struct qla_flt_header {
1309 uint16_t version;
1310 uint16_t length;
1311 uint16_t checksum;
1312 uint16_t unused;
1313 };
1314
1315 #define FLT_REG_FW 0x01
1316 #define FLT_REG_BOOT_CODE 0x07
1317 #define FLT_REG_VPD_0 0x14
1318 #define FLT_REG_NVRAM_0 0x15
1319 #define FLT_REG_VPD_1 0x16
1320 #define FLT_REG_NVRAM_1 0x17
1321 #define FLT_REG_FDT 0x1a
1322 #define FLT_REG_FLT 0x1c
1323 #define FLT_REG_HW_EVENT_0 0x1d
1324 #define FLT_REG_HW_EVENT_1 0x1f
1325 #define FLT_REG_NPIV_CONF_0 0x29
1326 #define FLT_REG_NPIV_CONF_1 0x2a
1327 #define FLT_REG_GOLD_FW 0x2f
1328 #define FLT_REG_FCP_PRIO_0 0x87
1329 #define FLT_REG_FCP_PRIO_1 0x88
1330
1331 struct qla_flt_region {
1332 uint32_t code;
1333 uint32_t size;
1334 uint32_t start;
1335 uint32_t end;
1336 };
1337
1338 /* Flash NPIV Configuration Table ********************************************/
1339
1340 struct qla_npiv_header {
1341 uint8_t sig[2];
1342 uint16_t version;
1343 uint16_t entries;
1344 uint16_t unused[4];
1345 uint16_t checksum;
1346 };
1347
1348 struct qla_npiv_entry {
1349 uint16_t flags;
1350 uint16_t vf_id;
1351 uint8_t q_qos;
1352 uint8_t f_qos;
1353 uint16_t unused1;
1354 uint8_t port_name[WWN_SIZE];
1355 uint8_t node_name[WWN_SIZE];
1356 };
1357
1358 /* 84XX Support **************************************************************/
1359
1360 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
1361 #define A84_PANIC_RECOVERY 0x1
1362 #define A84_OP_LOGIN_COMPLETE 0x2
1363 #define A84_DIAG_LOGIN_COMPLETE 0x3
1364 #define A84_GOLD_LOGIN_COMPLETE 0x4
1365
1366 #define MBC_ISP84XX_RESET 0x3a /* Reset. */
1367
1368 #define FSTATE_REMOTE_FC_DOWN BIT_0
1369 #define FSTATE_NSL_LINK_DOWN BIT_1
1370 #define FSTATE_IS_DIAG_FW BIT_2
1371 #define FSTATE_LOGGED_IN BIT_3
1372 #define FSTATE_WAITING_FOR_VERIFY BIT_4
1373
1374 #define VERIFY_CHIP_IOCB_TYPE 0x1B
1375 struct verify_chip_entry_84xx {
1376 uint8_t entry_type;
1377 uint8_t entry_count;
1378 uint8_t sys_defined;
1379 uint8_t entry_status;
1380
1381 uint32_t handle;
1382
1383 uint16_t options;
1384 #define VCO_DONT_UPDATE_FW BIT_0
1385 #define VCO_FORCE_UPDATE BIT_1
1386 #define VCO_DONT_RESET_UPDATE BIT_2
1387 #define VCO_DIAG_FW BIT_3
1388 #define VCO_END_OF_DATA BIT_14
1389 #define VCO_ENABLE_DSD BIT_15
1390
1391 uint16_t reserved_1;
1392
1393 uint16_t data_seg_cnt;
1394 uint16_t reserved_2[3];
1395
1396 uint32_t fw_ver;
1397 uint32_t exchange_address;
1398
1399 uint32_t reserved_3[3];
1400 uint32_t fw_size;
1401 uint32_t fw_seq_size;
1402 uint32_t relative_offset;
1403
1404 uint32_t dseg_address[2];
1405 uint32_t dseg_length;
1406 };
1407
1408 struct verify_chip_rsp_84xx {
1409 uint8_t entry_type;
1410 uint8_t entry_count;
1411 uint8_t sys_defined;
1412 uint8_t entry_status;
1413
1414 uint32_t handle;
1415
1416 uint16_t comp_status;
1417 #define CS_VCS_CHIP_FAILURE 0x3
1418 #define CS_VCS_BAD_EXCHANGE 0x8
1419 #define CS_VCS_SEQ_COMPLETEi 0x40
1420
1421 uint16_t failure_code;
1422 #define VFC_CHECKSUM_ERROR 0x1
1423 #define VFC_INVALID_LEN 0x2
1424 #define VFC_ALREADY_IN_PROGRESS 0x8
1425
1426 uint16_t reserved_1[4];
1427
1428 uint32_t fw_ver;
1429 uint32_t exchange_address;
1430
1431 uint32_t reserved_2[6];
1432 };
1433
1434 #define ACCESS_CHIP_IOCB_TYPE 0x2B
1435 struct access_chip_84xx {
1436 uint8_t entry_type;
1437 uint8_t entry_count;
1438 uint8_t sys_defined;
1439 uint8_t entry_status;
1440
1441 uint32_t handle;
1442
1443 uint16_t options;
1444 #define ACO_DUMP_MEMORY 0x0
1445 #define ACO_LOAD_MEMORY 0x1
1446 #define ACO_CHANGE_CONFIG_PARAM 0x2
1447 #define ACO_REQUEST_INFO 0x3
1448
1449 uint16_t reserved1;
1450
1451 uint16_t dseg_count;
1452 uint16_t reserved2[3];
1453
1454 uint32_t parameter1;
1455 uint32_t parameter2;
1456 uint32_t parameter3;
1457
1458 uint32_t reserved3[3];
1459 uint32_t total_byte_cnt;
1460 uint32_t reserved4;
1461
1462 uint32_t dseg_address[2];
1463 uint32_t dseg_length;
1464 };
1465
1466 struct access_chip_rsp_84xx {
1467 uint8_t entry_type;
1468 uint8_t entry_count;
1469 uint8_t sys_defined;
1470 uint8_t entry_status;
1471
1472 uint32_t handle;
1473
1474 uint16_t comp_status;
1475 uint16_t failure_code;
1476 uint32_t residual_count;
1477
1478 uint32_t reserved[12];
1479 };
1480
1481 /* 81XX Support **************************************************************/
1482
1483 #define MBA_DCBX_START 0x8016
1484 #define MBA_DCBX_COMPLETE 0x8030
1485 #define MBA_FCF_CONF_ERR 0x8031
1486 #define MBA_DCBX_PARAM_UPDATE 0x8032
1487 #define MBA_IDC_COMPLETE 0x8100
1488 #define MBA_IDC_NOTIFY 0x8101
1489 #define MBA_IDC_TIME_EXT 0x8102
1490
1491 #define MBC_IDC_ACK 0x101
1492 #define MBC_RESTART_MPI_FW 0x3d
1493 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
1494 #define MBC_GET_XGMAC_STATS 0x7a
1495 #define MBC_GET_DCBX_PARAMS 0x51
1496
1497 /* Flash access control option field bit definitions */
1498 #define FAC_OPT_FORCE_SEMAPHORE BIT_15
1499 #define FAC_OPT_REQUESTOR_ID BIT_14
1500 #define FAC_OPT_CMD_SUBCODE 0xff
1501
1502 /* Flash access control command subcodes */
1503 #define FAC_OPT_CMD_WRITE_PROTECT 0x00
1504 #define FAC_OPT_CMD_WRITE_ENABLE 0x01
1505 #define FAC_OPT_CMD_ERASE_SECTOR 0x02
1506 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
1507 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
1508 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
1509
1510 struct nvram_81xx {
1511 /* NVRAM header. */
1512 uint8_t id[4];
1513 uint16_t nvram_version;
1514 uint16_t reserved_0;
1515
1516 /* Firmware Initialization Control Block. */
1517 uint16_t version;
1518 uint16_t reserved_1;
1519 uint16_t frame_payload_size;
1520 uint16_t execution_throttle;
1521 uint16_t exchange_count;
1522 uint16_t reserved_2;
1523
1524 uint8_t port_name[WWN_SIZE];
1525 uint8_t node_name[WWN_SIZE];
1526
1527 uint16_t login_retry_count;
1528 uint16_t reserved_3;
1529 uint16_t interrupt_delay_timer;
1530 uint16_t login_timeout;
1531
1532 uint32_t firmware_options_1;
1533 uint32_t firmware_options_2;
1534 uint32_t firmware_options_3;
1535
1536 uint16_t reserved_4[4];
1537
1538 /* Offset 64. */
1539 uint8_t enode_mac[6];
1540 uint16_t reserved_5[5];
1541
1542 /* Offset 80. */
1543 uint16_t reserved_6[24];
1544
1545 /* Offset 128. */
1546 uint16_t ex_version;
1547 uint8_t prio_fcf_matching_flags;
1548 uint8_t reserved_6_1[3];
1549 uint16_t pri_fcf_vlan_id;
1550 uint8_t pri_fcf_fabric_name[8];
1551 uint16_t reserved_6_2[7];
1552 uint8_t spma_mac_addr[6];
1553 uint16_t reserved_6_3[14];
1554
1555 /* Offset 192. */
1556 uint16_t reserved_7[32];
1557
1558 /*
1559 * BIT 0 = Enable spinup delay
1560 * BIT 1 = Disable BIOS
1561 * BIT 2 = Enable Memory Map BIOS
1562 * BIT 3 = Enable Selectable Boot
1563 * BIT 4 = Disable RISC code load
1564 * BIT 5 = Disable Serdes
1565 * BIT 6 = Opt boot mode
1566 * BIT 7 = Interrupt enable
1567 *
1568 * BIT 8 = EV Control enable
1569 * BIT 9 = Enable lip reset
1570 * BIT 10 = Enable lip full login
1571 * BIT 11 = Enable target reset
1572 * BIT 12 = Stop firmware
1573 * BIT 13 = Enable nodename option
1574 * BIT 14 = Default WWPN valid
1575 * BIT 15 = Enable alternate WWN
1576 *
1577 * BIT 16 = CLP LUN string
1578 * BIT 17 = CLP Target string
1579 * BIT 18 = CLP BIOS enable string
1580 * BIT 19 = CLP Serdes string
1581 * BIT 20 = CLP WWPN string
1582 * BIT 21 = CLP WWNN string
1583 * BIT 22 =
1584 * BIT 23 =
1585 * BIT 24 = Keep WWPN
1586 * BIT 25 = Temp WWPN
1587 * BIT 26-31 =
1588 */
1589 uint32_t host_p;
1590
1591 uint8_t alternate_port_name[WWN_SIZE];
1592 uint8_t alternate_node_name[WWN_SIZE];
1593
1594 uint8_t boot_port_name[WWN_SIZE];
1595 uint16_t boot_lun_number;
1596 uint16_t reserved_8;
1597
1598 uint8_t alt1_boot_port_name[WWN_SIZE];
1599 uint16_t alt1_boot_lun_number;
1600 uint16_t reserved_9;
1601
1602 uint8_t alt2_boot_port_name[WWN_SIZE];
1603 uint16_t alt2_boot_lun_number;
1604 uint16_t reserved_10;
1605
1606 uint8_t alt3_boot_port_name[WWN_SIZE];
1607 uint16_t alt3_boot_lun_number;
1608 uint16_t reserved_11;
1609
1610 /*
1611 * BIT 0 = Selective Login
1612 * BIT 1 = Alt-Boot Enable
1613 * BIT 2 = Reserved
1614 * BIT 3 = Boot Order List
1615 * BIT 4 = Reserved
1616 * BIT 5 = Selective LUN
1617 * BIT 6 = Reserved
1618 * BIT 7-31 =
1619 */
1620 uint32_t efi_parameters;
1621
1622 uint8_t reset_delay;
1623 uint8_t reserved_12;
1624 uint16_t reserved_13;
1625
1626 uint16_t boot_id_number;
1627 uint16_t reserved_14;
1628
1629 uint16_t max_luns_per_target;
1630 uint16_t reserved_15;
1631
1632 uint16_t port_down_retry_count;
1633 uint16_t link_down_timeout;
1634
1635 /* FCode parameters. */
1636 uint16_t fcode_parameter;
1637
1638 uint16_t reserved_16[3];
1639
1640 /* Offset 352. */
1641 uint8_t reserved_17[4];
1642 uint16_t reserved_18[5];
1643 uint8_t reserved_19[2];
1644 uint16_t reserved_20[8];
1645
1646 /* Offset 384. */
1647 uint8_t reserved_21[16];
1648 uint16_t reserved_22[3];
1649
1650 /*
1651 * BIT 0 = Extended BB credits for LR
1652 * BIT 1 = Virtual Fabric Enable
1653 * BIT 2 = Enhanced Features Unused
1654 * BIT 3-7 = Enhanced Features Reserved
1655 */
1656 /* Enhanced Features */
1657 uint8_t enhanced_features;
1658
1659 uint8_t reserved_23;
1660 uint16_t reserved_24[4];
1661
1662 /* Offset 416. */
1663 uint16_t reserved_25[32];
1664
1665 /* Offset 480. */
1666 uint8_t model_name[16];
1667
1668 /* Offset 496. */
1669 uint16_t feature_mask_l;
1670 uint16_t feature_mask_h;
1671 uint16_t reserved_26[2];
1672
1673 uint16_t subsystem_vendor_id;
1674 uint16_t subsystem_device_id;
1675
1676 uint32_t checksum;
1677 };
1678
1679 /*
1680 * ISP Initialization Control Block.
1681 * Little endian except where noted.
1682 */
1683 #define ICB_VERSION 1
1684 struct init_cb_81xx {
1685 uint16_t version;
1686 uint16_t reserved_1;
1687
1688 uint16_t frame_payload_size;
1689 uint16_t execution_throttle;
1690 uint16_t exchange_count;
1691
1692 uint16_t reserved_2;
1693
1694 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1695 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1696
1697 uint16_t response_q_inpointer;
1698 uint16_t request_q_outpointer;
1699
1700 uint16_t login_retry_count;
1701
1702 uint16_t prio_request_q_outpointer;
1703
1704 uint16_t response_q_length;
1705 uint16_t request_q_length;
1706
1707 uint16_t reserved_3;
1708
1709 uint16_t prio_request_q_length;
1710
1711 uint32_t request_q_address[2];
1712 uint32_t response_q_address[2];
1713 uint32_t prio_request_q_address[2];
1714
1715 uint8_t reserved_4[8];
1716
1717 uint16_t atio_q_inpointer;
1718 uint16_t atio_q_length;
1719 uint32_t atio_q_address[2];
1720
1721 uint16_t interrupt_delay_timer; /* 100us increments. */
1722 uint16_t login_timeout;
1723
1724 /*
1725 * BIT 0-3 = Reserved
1726 * BIT 4 = Enable Target Mode
1727 * BIT 5 = Disable Initiator Mode
1728 * BIT 6 = Reserved
1729 * BIT 7 = Reserved
1730 *
1731 * BIT 8-13 = Reserved
1732 * BIT 14 = Node Name Option
1733 * BIT 15-31 = Reserved
1734 */
1735 uint32_t firmware_options_1;
1736
1737 /*
1738 * BIT 0 = Operation Mode bit 0
1739 * BIT 1 = Operation Mode bit 1
1740 * BIT 2 = Operation Mode bit 2
1741 * BIT 3 = Operation Mode bit 3
1742 * BIT 4-7 = Reserved
1743 *
1744 * BIT 8 = Enable Class 2
1745 * BIT 9 = Enable ACK0
1746 * BIT 10 = Reserved
1747 * BIT 11 = Enable FC-SP Security
1748 * BIT 12 = FC Tape Enable
1749 * BIT 13 = Reserved
1750 * BIT 14 = Enable Target PRLI Control
1751 * BIT 15-31 = Reserved
1752 */
1753 uint32_t firmware_options_2;
1754
1755 /*
1756 * BIT 0-3 = Reserved
1757 * BIT 4 = FCP RSP Payload bit 0
1758 * BIT 5 = FCP RSP Payload bit 1
1759 * BIT 6 = Enable Receive Out-of-Order data frame handling
1760 * BIT 7 = Reserved
1761 *
1762 * BIT 8 = Reserved
1763 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
1764 * BIT 10-16 = Reserved
1765 * BIT 17 = Enable multiple FCFs
1766 * BIT 18-20 = MAC addressing mode
1767 * BIT 21-25 = Ethernet data rate
1768 * BIT 26 = Enable ethernet header rx IOCB for ATIO q
1769 * BIT 27 = Enable ethernet header rx IOCB for response q
1770 * BIT 28 = SPMA selection bit 0
1771 * BIT 28 = SPMA selection bit 1
1772 * BIT 30-31 = Reserved
1773 */
1774 uint32_t firmware_options_3;
1775
1776 uint8_t reserved_5[8];
1777
1778 uint8_t enode_mac[6];
1779
1780 uint8_t reserved_6[10];
1781 };
1782
1783 struct mid_init_cb_81xx {
1784 struct init_cb_81xx init_cb;
1785
1786 uint16_t count;
1787 uint16_t options;
1788
1789 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1790 };
1791
1792 struct ex_init_cb_81xx {
1793 uint16_t ex_version;
1794 uint8_t prio_fcf_matching_flags;
1795 uint8_t reserved_1[3];
1796 uint16_t pri_fcf_vlan_id;
1797 uint8_t pri_fcf_fabric_name[8];
1798 uint16_t reserved_2[7];
1799 uint8_t spma_mac_addr[6];
1800 uint16_t reserved_3[14];
1801 };
1802
1803 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
1804 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
1805
1806 /* FCP priority config defines *************************************/
1807 /* operations */
1808 #define QLFC_FCP_PRIO_DISABLE 0x0
1809 #define QLFC_FCP_PRIO_ENABLE 0x1
1810 #define QLFC_FCP_PRIO_GET_CONFIG 0x2
1811 #define QLFC_FCP_PRIO_SET_CONFIG 0x3
1812
1813 struct qla_fcp_prio_entry {
1814 uint16_t flags; /* Describes parameter(s) in FCP */
1815 /* priority entry that are valid */
1816 #define FCP_PRIO_ENTRY_VALID 0x1
1817 #define FCP_PRIO_ENTRY_TAG_VALID 0x2
1818 #define FCP_PRIO_ENTRY_SPID_VALID 0x4
1819 #define FCP_PRIO_ENTRY_DPID_VALID 0x8
1820 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10
1821 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20
1822 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40
1823 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80
1824 uint8_t tag; /* Priority value */
1825 uint8_t reserved; /* Reserved for future use */
1826 uint32_t src_pid; /* Src port id. high order byte */
1827 /* unused; -1 (wild card) */
1828 uint32_t dst_pid; /* Src port id. high order byte */
1829 /* unused; -1 (wild card) */
1830 uint16_t lun_beg; /* 1st lun num of lun range. */
1831 /* -1 (wild card) */
1832 uint16_t lun_end; /* 2nd lun num of lun range. */
1833 /* -1 (wild card) */
1834 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */
1835 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */
1836 };
1837
1838 struct qla_fcp_prio_cfg {
1839 uint8_t signature[4]; /* "HQOS" signature of config data */
1840 uint16_t version; /* 1: Initial version */
1841 uint16_t length; /* config data size in num bytes */
1842 uint16_t checksum; /* config data bytes checksum */
1843 uint16_t num_entries; /* Number of entries */
1844 uint16_t size_of_entry; /* Size of each entry in num bytes */
1845 uint8_t attributes; /* enable/disable, persistence */
1846 #define FCP_PRIO_ATTR_DISABLE 0x0
1847 #define FCP_PRIO_ATTR_ENABLE 0x1
1848 #define FCP_PRIO_ATTR_PERSIST 0x2
1849 uint8_t reserved; /* Reserved for future use */
1850 #define FCP_PRIO_CFG_HDR_SIZE 0x10
1851 struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */
1852 #define FCP_PRIO_CFG_ENTRY_SIZE 0x20
1853 };
1854
1855 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/
1856
1857 /* 25XX Support ****************************************************/
1858 #define FA_FCP_PRIO0_ADDR_25 0x3C000
1859 #define FA_FCP_PRIO1_ADDR_25 0x3E000
1860
1861 /* 81XX Flash locations -- occupies second 2MB region. */
1862 #define FA_BOOT_CODE_ADDR_81 0x80000
1863 #define FA_RISC_CODE_ADDR_81 0xA0000
1864 #define FA_FW_AREA_ADDR_81 0xC0000
1865 #define FA_VPD_NVRAM_ADDR_81 0xD0000
1866 #define FA_VPD0_ADDR_81 0xD0000
1867 #define FA_VPD1_ADDR_81 0xD0400
1868 #define FA_NVRAM0_ADDR_81 0xD0080
1869 #define FA_NVRAM1_ADDR_81 0xD0180
1870 #define FA_FEATURE_ADDR_81 0xD4000
1871 #define FA_FLASH_DESCR_ADDR_81 0xD8000
1872 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
1873 #define FA_HW_EVENT0_ADDR_81 0xDC000
1874 #define FA_HW_EVENT1_ADDR_81 0xDC400
1875 #define FA_NPIV_CONF0_ADDR_81 0xD1000
1876 #define FA_NPIV_CONF1_ADDR_81 0xD2000
1877
1878 #endif