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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / spi / spi-topcliff-pch.c
blob0ddfe7702a19c49a4c139557b0e24504bb23f884
1 /*
2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
3 *
4 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/wait.h>
23 #include <linux/spi/spi.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/spi/spidev.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30
31 #include <linux/dmaengine.h>
32 #include <linux/pch_dma.h>
33
34 /* Register offsets */
35 #define PCH_SPCR 0x00 /* SPI control register */
36 #define PCH_SPBRR 0x04 /* SPI baud rate register */
37 #define PCH_SPSR 0x08 /* SPI status register */
38 #define PCH_SPDWR 0x0C /* SPI write data register */
39 #define PCH_SPDRR 0x10 /* SPI read data register */
40 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
41 #define PCH_SRST 0x1C /* SPI reset register */
42 #define PCH_ADDRESS_SIZE 0x20
43
44 #define PCH_SPSR_TFD 0x000007C0
45 #define PCH_SPSR_RFD 0x0000F800
46
47 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
48 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
49
50 #define PCH_RX_THOLD 7
51 #define PCH_RX_THOLD_MAX 15
52
53 #define PCH_TX_THOLD 2
54
55 #define PCH_MAX_BAUDRATE 5000000
56 #define PCH_MAX_FIFO_DEPTH 16
57
58 #define STATUS_RUNNING 1
59 #define STATUS_EXITING 2
60 #define PCH_SLEEP_TIME 10
61
62 #define SSN_LOW 0x02U
63 #define SSN_HIGH 0x03U
64 #define SSN_NO_CONTROL 0x00U
65 #define PCH_MAX_CS 0xFF
66 #define PCI_DEVICE_ID_GE_SPI 0x8816
67
68 #define SPCR_SPE_BIT (1 << 0)
69 #define SPCR_MSTR_BIT (1 << 1)
70 #define SPCR_LSBF_BIT (1 << 4)
71 #define SPCR_CPHA_BIT (1 << 5)
72 #define SPCR_CPOL_BIT (1 << 6)
73 #define SPCR_TFIE_BIT (1 << 8)
74 #define SPCR_RFIE_BIT (1 << 9)
75 #define SPCR_FIE_BIT (1 << 10)
76 #define SPCR_ORIE_BIT (1 << 11)
77 #define SPCR_MDFIE_BIT (1 << 12)
78 #define SPCR_FICLR_BIT (1 << 24)
79 #define SPSR_TFI_BIT (1 << 0)
80 #define SPSR_RFI_BIT (1 << 1)
81 #define SPSR_FI_BIT (1 << 2)
82 #define SPSR_ORF_BIT (1 << 3)
83 #define SPBRR_SIZE_BIT (1 << 10)
84
85 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
86 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
87
88 #define SPCR_RFIC_FIELD 20
89 #define SPCR_TFIC_FIELD 16
90
91 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
92 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
93 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
94
95 #define PCH_CLOCK_HZ 50000000
96 #define PCH_MAX_SPBR 1023
97
98 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
99 #define PCI_VENDOR_ID_ROHM 0x10DB
100 #define PCI_DEVICE_ID_ML7213_SPI 0x802c
101 #define PCI_DEVICE_ID_ML7223_SPI 0x800F
102 #define PCI_DEVICE_ID_ML7831_SPI 0x8816
103
104 /*
105 * Set the number of SPI instance max
106 * Intel EG20T PCH : 1ch
107 * LAPIS Semiconductor ML7213 IOH : 2ch
108 * LAPIS Semiconductor ML7223 IOH : 1ch
109 * LAPIS Semiconductor ML7831 IOH : 1ch
110 */
111 #define PCH_SPI_MAX_DEV 2
112
113 #define PCH_BUF_SIZE 4096
114 #define PCH_DMA_TRANS_SIZE 12
115
116 static int use_dma = 1;
117
118 struct pch_spi_dma_ctrl {
119 struct dma_async_tx_descriptor *desc_tx;
120 struct dma_async_tx_descriptor *desc_rx;
121 struct pch_dma_slave param_tx;
122 struct pch_dma_slave param_rx;
123 struct dma_chan *chan_tx;
124 struct dma_chan *chan_rx;
125 struct scatterlist *sg_tx_p;
126 struct scatterlist *sg_rx_p;
127 struct scatterlist sg_tx;
128 struct scatterlist sg_rx;
129 int nent;
130 void *tx_buf_virt;
131 void *rx_buf_virt;
132 dma_addr_t tx_buf_dma;
133 dma_addr_t rx_buf_dma;
134 };
135 /**
136 * struct pch_spi_data - Holds the SPI channel specific details
137 * @io_remap_addr: The remapped PCI base address
138 * @master: Pointer to the SPI master structure
139 * @work: Reference to work queue handler
140 * @wk: Workqueue for carrying out execution of the
141 * requests
142 * @wait: Wait queue for waking up upon receiving an
143 * interrupt.
144 * @transfer_complete: Status of SPI Transfer
145 * @bcurrent_msg_processing: Status flag for message processing
146 * @lock: Lock for protecting this structure
147 * @queue: SPI Message queue
148 * @status: Status of the SPI driver
149 * @bpw_len: Length of data to be transferred in bits per
150 * word
151 * @transfer_active: Flag showing active transfer
152 * @tx_index: Transmit data count; for bookkeeping during
153 * transfer
154 * @rx_index: Receive data count; for bookkeeping during
155 * transfer
156 * @tx_buff: Buffer for data to be transmitted
157 * @rx_index: Buffer for Received data
158 * @n_curnt_chip: The chip number that this SPI driver currently
159 * operates on
160 * @current_chip: Reference to the current chip that this SPI
161 * driver currently operates on
162 * @current_msg: The current message that this SPI driver is
163 * handling
164 * @cur_trans: The current transfer that this SPI driver is
165 * handling
166 * @board_dat: Reference to the SPI device data structure
167 * @plat_dev: platform_device structure
168 * @ch: SPI channel number
169 * @irq_reg_sts: Status of IRQ registration
170 */
171 struct pch_spi_data {
172 void __iomem *io_remap_addr;
173 unsigned long io_base_addr;
174 struct spi_master *master;
175 struct work_struct work;
176 struct workqueue_struct *wk;
177 wait_queue_head_t wait;
178 u8 transfer_complete;
179 u8 bcurrent_msg_processing;
180 spinlock_t lock;
181 struct list_head queue;
182 u8 status;
183 u32 bpw_len;
184 u8 transfer_active;
185 u32 tx_index;
186 u32 rx_index;
187 u16 *pkt_tx_buff;
188 u16 *pkt_rx_buff;
189 u8 n_curnt_chip;
190 struct spi_device *current_chip;
191 struct spi_message *current_msg;
192 struct spi_transfer *cur_trans;
193 struct pch_spi_board_data *board_dat;
194 struct platform_device *plat_dev;
195 int ch;
196 struct pch_spi_dma_ctrl dma;
197 int use_dma;
198 u8 irq_reg_sts;
199 };
200
201 /**
202 * struct pch_spi_board_data - Holds the SPI device specific details
203 * @pdev: Pointer to the PCI device
204 * @suspend_sts: Status of suspend
205 * @num: The number of SPI device instance
206 */
207 struct pch_spi_board_data {
208 struct pci_dev *pdev;
209 u8 suspend_sts;
210 int num;
211 };
212
213 struct pch_pd_dev_save {
214 int num;
215 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
216 struct pch_spi_board_data *board_dat;
217 };
218
219 static struct pci_device_id pch_spi_pcidev_id[] = {
220 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
221 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
222 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
223 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
224 { }
225 };
226
227 /**
228 * pch_spi_writereg() - Performs register writes
229 * @master: Pointer to struct spi_master.
230 * @idx: Register offset.
231 * @val: Value to be written to register.
232 */
233 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
234 {
235 struct pch_spi_data *data = spi_master_get_devdata(master);
236 iowrite32(val, (data->io_remap_addr + idx));
237 }
238
239 /**
240 * pch_spi_readreg() - Performs register reads
241 * @master: Pointer to struct spi_master.
242 * @idx: Register offset.
243 */
244 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
245 {
246 struct pch_spi_data *data = spi_master_get_devdata(master);
247 return ioread32(data->io_remap_addr + idx);
248 }
249
250 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
251 u32 set, u32 clr)
252 {
253 u32 tmp = pch_spi_readreg(master, idx);
254 tmp = (tmp & ~clr) | set;
255 pch_spi_writereg(master, idx, tmp);
256 }
257
258 static void pch_spi_set_master_mode(struct spi_master *master)
259 {
260 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
261 }
262
263 /**
264 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
265 * @master: Pointer to struct spi_master.
266 */
267 static void pch_spi_clear_fifo(struct spi_master *master)
268 {
269 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
270 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
271 }
272
273 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
274 void __iomem *io_remap_addr)
275 {
276 u32 n_read, tx_index, rx_index, bpw_len;
277 u16 *pkt_rx_buffer, *pkt_tx_buff;
278 int read_cnt;
279 u32 reg_spcr_val;
280 void __iomem *spsr;
281 void __iomem *spdrr;
282 void __iomem *spdwr;
283
284 spsr = io_remap_addr + PCH_SPSR;
285 iowrite32(reg_spsr_val, spsr);
286
287 if (data->transfer_active) {
288 rx_index = data->rx_index;
289 tx_index = data->tx_index;
290 bpw_len = data->bpw_len;
291 pkt_rx_buffer = data->pkt_rx_buff;
292 pkt_tx_buff = data->pkt_tx_buff;
293
294 spdrr = io_remap_addr + PCH_SPDRR;
295 spdwr = io_remap_addr + PCH_SPDWR;
296
297 n_read = PCH_READABLE(reg_spsr_val);
298
299 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
300 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
301 if (tx_index < bpw_len)
302 iowrite32(pkt_tx_buff[tx_index++], spdwr);
303 }
304
305 /* disable RFI if not needed */
306 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
307 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
308 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
309
310 /* reset rx threshold */
311 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
312 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
313
314 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
315 }
316
317 /* update counts */
318 data->tx_index = tx_index;
319 data->rx_index = rx_index;
320
321 /* if transfer complete interrupt */
322 if (reg_spsr_val & SPSR_FI_BIT) {
323 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
324 /* disable interrupts */
325 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
326 PCH_ALL);
327
328 /* transfer is completed;
329 inform pch_spi_process_messages */
330 data->transfer_complete = true;
331 data->transfer_active = false;
332 wake_up(&data->wait);
333 } else {
334 dev_err(&data->master->dev,
335 "%s : Transfer is not completed",
336 __func__);
337 }
338 }
339 }
340 }
341
342 /**
343 * pch_spi_handler() - Interrupt handler
344 * @irq: The interrupt number.
345 * @dev_id: Pointer to struct pch_spi_board_data.
346 */
347 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
348 {
349 u32 reg_spsr_val;
350 void __iomem *spsr;
351 void __iomem *io_remap_addr;
352 irqreturn_t ret = IRQ_NONE;
353 struct pch_spi_data *data = dev_id;
354 struct pch_spi_board_data *board_dat = data->board_dat;
355
356 if (board_dat->suspend_sts) {
357 dev_dbg(&board_dat->pdev->dev,
358 "%s returning due to suspend\n", __func__);
359 return IRQ_NONE;
360 }
361
362 io_remap_addr = data->io_remap_addr;
363 spsr = io_remap_addr + PCH_SPSR;
364
365 reg_spsr_val = ioread32(spsr);
366
367 if (reg_spsr_val & SPSR_ORF_BIT) {
368 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
369 if (data->current_msg->complete != 0) {
370 data->transfer_complete = true;
371 data->current_msg->status = -EIO;
372 data->current_msg->complete(data->current_msg->context);
373 data->bcurrent_msg_processing = false;
374 data->current_msg = NULL;
375 data->cur_trans = NULL;
376 }
377 }
378
379 if (data->use_dma)
380 return IRQ_NONE;
381
382 /* Check if the interrupt is for SPI device */
383 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
384 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
385 ret = IRQ_HANDLED;
386 }
387
388 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
389 __func__, ret);
390
391 return ret;
392 }
393
394 /**
395 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
396 * @master: Pointer to struct spi_master.
397 * @speed_hz: Baud rate.
398 */
399 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
400 {
401 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
402
403 /* if baud rate is less than we can support limit it */
404 if (n_spbr > PCH_MAX_SPBR)
405 n_spbr = PCH_MAX_SPBR;
406
407 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
408 }
409
410 /**
411 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
412 * @master: Pointer to struct spi_master.
413 * @bits_per_word: Bits per word for SPI transfer.
414 */
415 static void pch_spi_set_bits_per_word(struct spi_master *master,
416 u8 bits_per_word)
417 {
418 if (bits_per_word == 8)
419 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
420 else
421 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
422 }
423
424 /**
425 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
426 * @spi: Pointer to struct spi_device.
427 */
428 static void pch_spi_setup_transfer(struct spi_device *spi)
429 {
430 u32 flags = 0;
431
432 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
433 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
434 spi->max_speed_hz);
435 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
436
437 /* set bits per word */
438 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
439
440 if (!(spi->mode & SPI_LSB_FIRST))
441 flags |= SPCR_LSBF_BIT;
442 if (spi->mode & SPI_CPOL)
443 flags |= SPCR_CPOL_BIT;
444 if (spi->mode & SPI_CPHA)
445 flags |= SPCR_CPHA_BIT;
446 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
447 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
448
449 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
450 pch_spi_clear_fifo(spi->master);
451 }
452
453 /**
454 * pch_spi_reset() - Clears SPI registers
455 * @master: Pointer to struct spi_master.
456 */
457 static void pch_spi_reset(struct spi_master *master)
458 {
459 /* write 1 to reset SPI */
460 pch_spi_writereg(master, PCH_SRST, 0x1);
461
462 /* clear reset */
463 pch_spi_writereg(master, PCH_SRST, 0x0);
464 }
465
466 static int pch_spi_setup(struct spi_device *pspi)
467 {
468 /* check bits per word */
469 if (pspi->bits_per_word == 0) {
470 pspi->bits_per_word = 8;
471 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
472 }
473
474 if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
475 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
476 return -EINVAL;
477 }
478
479 /* Check baud rate setting */
480 /* if baud rate of chip is greater than
481 max we can support,return error */
482 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
483 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
484
485 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
486 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
487
488 return 0;
489 }
490
491 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
492 {
493
494 struct spi_transfer *transfer;
495 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
496 int retval;
497 unsigned long flags;
498
499 /* validate spi message and baud rate */
500 if (unlikely(list_empty(&pmsg->transfers) == 1)) {
501 dev_err(&pspi->dev, "%s list empty\n", __func__);
502 retval = -EINVAL;
503 goto err_out;
504 }
505
506 if (unlikely(pspi->max_speed_hz == 0)) {
507 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
508 __func__, pspi->max_speed_hz);
509 retval = -EINVAL;
510 goto err_out;
511 }
512
513 dev_dbg(&pspi->dev, "%s Transfer List not empty. "
514 "Transfer Speed is set.\n", __func__);
515
516 spin_lock_irqsave(&data->lock, flags);
517 /* validate Tx/Rx buffers and Transfer length */
518 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
519 if (!transfer->tx_buf && !transfer->rx_buf) {
520 dev_err(&pspi->dev,
521 "%s Tx and Rx buffer NULL\n", __func__);
522 retval = -EINVAL;
523 goto err_return_spinlock;
524 }
525
526 if (!transfer->len) {
527 dev_err(&pspi->dev, "%s Transfer length invalid\n",
528 __func__);
529 retval = -EINVAL;
530 goto err_return_spinlock;
531 }
532
533 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
534 " valid\n", __func__);
535
536 /* if baud rate has been specified validate the same */
537 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
538 transfer->speed_hz = PCH_MAX_BAUDRATE;
539
540 /* if bits per word has been specified validate the same */
541 if (transfer->bits_per_word) {
542 if ((transfer->bits_per_word != 8)
543 && (transfer->bits_per_word != 16)) {
544 retval = -EINVAL;
545 dev_err(&pspi->dev,
546 "%s Invalid bits per word\n", __func__);
547 goto err_return_spinlock;
548 }
549 }
550 }
551 spin_unlock_irqrestore(&data->lock, flags);
552
553 /* We won't process any messages if we have been asked to terminate */
554 if (data->status == STATUS_EXITING) {
555 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
556 retval = -ESHUTDOWN;
557 goto err_out;
558 }
559
560 /* If suspended ,return -EINVAL */
561 if (data->board_dat->suspend_sts) {
562 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
563 retval = -EINVAL;
564 goto err_out;
565 }
566
567 /* set status of message */
568 pmsg->actual_length = 0;
569 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
570
571 pmsg->status = -EINPROGRESS;
572 spin_lock_irqsave(&data->lock, flags);
573 /* add message to queue */
574 list_add_tail(&pmsg->queue, &data->queue);
575 spin_unlock_irqrestore(&data->lock, flags);
576
577 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
578
579 /* schedule work queue to run */
580 queue_work(data->wk, &data->work);
581 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
582
583 retval = 0;
584
585 err_out:
586 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
587 return retval;
588 err_return_spinlock:
589 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
590 spin_unlock_irqrestore(&data->lock, flags);
591 return retval;
592 }
593
594 static inline void pch_spi_select_chip(struct pch_spi_data *data,
595 struct spi_device *pspi)
596 {
597 if (data->current_chip != NULL) {
598 if (pspi->chip_select != data->n_curnt_chip) {
599 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
600 data->current_chip = NULL;
601 }
602 }
603
604 data->current_chip = pspi;
605
606 data->n_curnt_chip = data->current_chip->chip_select;
607
608 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
609 pch_spi_setup_transfer(pspi);
610 }
611
612 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
613 {
614 int size;
615 u32 n_writes;
616 int j;
617 struct spi_message *pmsg;
618 const u8 *tx_buf;
619 const u16 *tx_sbuf;
620
621 /* set baud rate if needed */
622 if (data->cur_trans->speed_hz) {
623 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
624 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
625 }
626
627 /* set bits per word if needed */
628 if (data->cur_trans->bits_per_word &&
629 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
630 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
631 pch_spi_set_bits_per_word(data->master,
632 data->cur_trans->bits_per_word);
633 *bpw = data->cur_trans->bits_per_word;
634 } else {
635 *bpw = data->current_msg->spi->bits_per_word;
636 }
637
638 /* reset Tx/Rx index */
639 data->tx_index = 0;
640 data->rx_index = 0;
641
642 data->bpw_len = data->cur_trans->len / (*bpw / 8);
643
644 /* find alloc size */
645 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
646
647 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
648 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
649 if (data->pkt_tx_buff != NULL) {
650 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
651 if (!data->pkt_rx_buff)
652 kfree(data->pkt_tx_buff);
653 }
654
655 if (!data->pkt_rx_buff) {
656 /* flush queue and set status of all transfers to -ENOMEM */
657 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
658 list_for_each_entry(pmsg, data->queue.next, queue) {
659 pmsg->status = -ENOMEM;
660
661 if (pmsg->complete != 0)
662 pmsg->complete(pmsg->context);
663
664 /* delete from queue */
665 list_del_init(&pmsg->queue);
666 }
667 return;
668 }
669
670 /* copy Tx Data */
671 if (data->cur_trans->tx_buf != NULL) {
672 if (*bpw == 8) {
673 tx_buf = data->cur_trans->tx_buf;
674 for (j = 0; j < data->bpw_len; j++)
675 data->pkt_tx_buff[j] = *tx_buf++;
676 } else {
677 tx_sbuf = data->cur_trans->tx_buf;
678 for (j = 0; j < data->bpw_len; j++)
679 data->pkt_tx_buff[j] = *tx_sbuf++;
680 }
681 }
682
683 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
684 n_writes = data->bpw_len;
685 if (n_writes > PCH_MAX_FIFO_DEPTH)
686 n_writes = PCH_MAX_FIFO_DEPTH;
687
688 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
689 "0x2 to SSNXCR\n", __func__);
690 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
691
692 for (j = 0; j < n_writes; j++)
693 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
694
695 /* update tx_index */
696 data->tx_index = j;
697
698 /* reset transfer complete flag */
699 data->transfer_complete = false;
700 data->transfer_active = true;
701 }
702
703 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
704 {
705 struct spi_message *pmsg;
706 dev_dbg(&data->master->dev, "%s called\n", __func__);
707 /* Invoke complete callback
708 * [To the spi core..indicating end of transfer] */
709 data->current_msg->status = 0;
710
711 if (data->current_msg->complete != 0) {
712 dev_dbg(&data->master->dev,
713 "%s:Invoking callback of SPI core\n", __func__);
714 data->current_msg->complete(data->current_msg->context);
715 }
716
717 /* update status in global variable */
718 data->bcurrent_msg_processing = false;
719
720 dev_dbg(&data->master->dev,
721 "%s:data->bcurrent_msg_processing = false\n", __func__);
722
723 data->current_msg = NULL;
724 data->cur_trans = NULL;
725
726 /* check if we have items in list and not suspending
727 * return 1 if list empty */
728 if ((list_empty(&data->queue) == 0) &&
729 (!data->board_dat->suspend_sts) &&
730 (data->status != STATUS_EXITING)) {
731 /* We have some more work to do (either there is more tranint
732 * bpw;sfer requests in the current message or there are
733 *more messages)
734 */
735 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
736 queue_work(data->wk, &data->work);
737 } else if (data->board_dat->suspend_sts ||
738 data->status == STATUS_EXITING) {
739 dev_dbg(&data->master->dev,
740 "%s suspend/remove initiated, flushing queue\n",
741 __func__);
742 list_for_each_entry(pmsg, data->queue.next, queue) {
743 pmsg->status = -EIO;
744
745 if (pmsg->complete)
746 pmsg->complete(pmsg->context);
747
748 /* delete from queue */
749 list_del_init(&pmsg->queue);
750 }
751 }
752 }
753
754 static void pch_spi_set_ir(struct pch_spi_data *data)
755 {
756 /* enable interrupts, set threshold, enable SPI */
757 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
758 /* set receive threshold to PCH_RX_THOLD */
759 pch_spi_setclr_reg(data->master, PCH_SPCR,
760 PCH_RX_THOLD << SPCR_RFIC_FIELD |
761 SPCR_FIE_BIT | SPCR_RFIE_BIT |
762 SPCR_ORIE_BIT | SPCR_SPE_BIT,
763 MASK_RFIC_SPCR_BITS | PCH_ALL);
764 else
765 /* set receive threshold to maximum */
766 pch_spi_setclr_reg(data->master, PCH_SPCR,
767 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
768 SPCR_FIE_BIT | SPCR_ORIE_BIT |
769 SPCR_SPE_BIT,
770 MASK_RFIC_SPCR_BITS | PCH_ALL);
771
772 /* Wait until the transfer completes; go to sleep after
773 initiating the transfer. */
774 dev_dbg(&data->master->dev,
775 "%s:waiting for transfer to get over\n", __func__);
776
777 wait_event_interruptible(data->wait, data->transfer_complete);
778
779 /* clear all interrupts */
780 pch_spi_writereg(data->master, PCH_SPSR,
781 pch_spi_readreg(data->master, PCH_SPSR));
782 /* Disable interrupts and SPI transfer */
783 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
784 /* clear FIFO */
785 pch_spi_clear_fifo(data->master);
786 }
787
788 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
789 {
790 int j;
791 u8 *rx_buf;
792 u16 *rx_sbuf;
793
794 /* copy Rx Data */
795 if (!data->cur_trans->rx_buf)
796 return;
797
798 if (bpw == 8) {
799 rx_buf = data->cur_trans->rx_buf;
800 for (j = 0; j < data->bpw_len; j++)
801 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
802 } else {
803 rx_sbuf = data->cur_trans->rx_buf;
804 for (j = 0; j < data->bpw_len; j++)
805 *rx_sbuf++ = data->pkt_rx_buff[j];
806 }
807 }
808
809 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
810 {
811 int j;
812 u8 *rx_buf;
813 u16 *rx_sbuf;
814 const u8 *rx_dma_buf;
815 const u16 *rx_dma_sbuf;
816
817 /* copy Rx Data */
818 if (!data->cur_trans->rx_buf)
819 return;
820
821 if (bpw == 8) {
822 rx_buf = data->cur_trans->rx_buf;
823 rx_dma_buf = data->dma.rx_buf_virt;
824 for (j = 0; j < data->bpw_len; j++)
825 *rx_buf++ = *rx_dma_buf++ & 0xFF;
826 } else {
827 rx_sbuf = data->cur_trans->rx_buf;
828 rx_dma_sbuf = data->dma.rx_buf_virt;
829 for (j = 0; j < data->bpw_len; j++)
830 *rx_sbuf++ = *rx_dma_sbuf++;
831 }
832 }
833
834 static int pch_spi_start_transfer(struct pch_spi_data *data)
835 {
836 struct pch_spi_dma_ctrl *dma;
837 unsigned long flags;
838 int rtn;
839
840 dma = &data->dma;
841
842 spin_lock_irqsave(&data->lock, flags);
843
844 /* disable interrupts, SPI set enable */
845 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
846
847 spin_unlock_irqrestore(&data->lock, flags);
848
849 /* Wait until the transfer completes; go to sleep after
850 initiating the transfer. */
851 dev_dbg(&data->master->dev,
852 "%s:waiting for transfer to get over\n", __func__);
853 rtn = wait_event_interruptible_timeout(data->wait,
854 data->transfer_complete,
855 msecs_to_jiffies(2 * HZ));
856
857 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
858 DMA_FROM_DEVICE);
859
860 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
861 DMA_FROM_DEVICE);
862 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
863
864 async_tx_ack(dma->desc_rx);
865 async_tx_ack(dma->desc_tx);
866 kfree(dma->sg_tx_p);
867 kfree(dma->sg_rx_p);
868
869 spin_lock_irqsave(&data->lock, flags);
870
871 /* clear fifo threshold, disable interrupts, disable SPI transfer */
872 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
873 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
874 SPCR_SPE_BIT);
875 /* clear all interrupts */
876 pch_spi_writereg(data->master, PCH_SPSR,
877 pch_spi_readreg(data->master, PCH_SPSR));
878 /* clear FIFO */
879 pch_spi_clear_fifo(data->master);
880
881 spin_unlock_irqrestore(&data->lock, flags);
882
883 return rtn;
884 }
885
886 static void pch_dma_rx_complete(void *arg)
887 {
888 struct pch_spi_data *data = arg;
889
890 /* transfer is completed;inform pch_spi_process_messages_dma */
891 data->transfer_complete = true;
892 wake_up_interruptible(&data->wait);
893 }
894
895 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
896 {
897 struct pch_dma_slave *param = slave;
898
899 if ((chan->chan_id == param->chan_id) &&
900 (param->dma_dev == chan->device->dev)) {
901 chan->private = param;
902 return true;
903 } else {
904 return false;
905 }
906 }
907
908 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
909 {
910 dma_cap_mask_t mask;
911 struct dma_chan *chan;
912 struct pci_dev *dma_dev;
913 struct pch_dma_slave *param;
914 struct pch_spi_dma_ctrl *dma;
915 unsigned int width;
916
917 if (bpw == 8)
918 width = PCH_DMA_WIDTH_1_BYTE;
919 else
920 width = PCH_DMA_WIDTH_2_BYTES;
921
922 dma = &data->dma;
923 dma_cap_zero(mask);
924 dma_cap_set(DMA_SLAVE, mask);
925
926 /* Get DMA's dev information */
927 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
928
929 /* Set Tx DMA */
930 param = &dma->param_tx;
931 param->dma_dev = &dma_dev->dev;
932 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
933 param->tx_reg = data->io_base_addr + PCH_SPDWR;
934 param->width = width;
935 chan = dma_request_channel(mask, pch_spi_filter, param);
936 if (!chan) {
937 dev_err(&data->master->dev,
938 "ERROR: dma_request_channel FAILS(Tx)\n");
939 data->use_dma = 0;
940 return;
941 }
942 dma->chan_tx = chan;
943
944 /* Set Rx DMA */
945 param = &dma->param_rx;
946 param->dma_dev = &dma_dev->dev;
947 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
948 param->rx_reg = data->io_base_addr + PCH_SPDRR;
949 param->width = width;
950 chan = dma_request_channel(mask, pch_spi_filter, param);
951 if (!chan) {
952 dev_err(&data->master->dev,
953 "ERROR: dma_request_channel FAILS(Rx)\n");
954 dma_release_channel(dma->chan_tx);
955 dma->chan_tx = NULL;
956 data->use_dma = 0;
957 return;
958 }
959 dma->chan_rx = chan;
960 }
961
962 static void pch_spi_release_dma(struct pch_spi_data *data)
963 {
964 struct pch_spi_dma_ctrl *dma;
965
966 dma = &data->dma;
967 if (dma->chan_tx) {
968 dma_release_channel(dma->chan_tx);
969 dma->chan_tx = NULL;
970 }
971 if (dma->chan_rx) {
972 dma_release_channel(dma->chan_rx);
973 dma->chan_rx = NULL;
974 }
975 return;
976 }
977
978 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
979 {
980 const u8 *tx_buf;
981 const u16 *tx_sbuf;
982 u8 *tx_dma_buf;
983 u16 *tx_dma_sbuf;
984 struct scatterlist *sg;
985 struct dma_async_tx_descriptor *desc_tx;
986 struct dma_async_tx_descriptor *desc_rx;
987 int num;
988 int i;
989 int size;
990 int rem;
991 unsigned long flags;
992 struct pch_spi_dma_ctrl *dma;
993
994 dma = &data->dma;
995
996 /* set baud rate if needed */
997 if (data->cur_trans->speed_hz) {
998 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
999 spin_lock_irqsave(&data->lock, flags);
1000 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
1001 spin_unlock_irqrestore(&data->lock, flags);
1002 }
1003
1004 /* set bits per word if needed */
1005 if (data->cur_trans->bits_per_word &&
1006 (data->current_msg->spi->bits_per_word !=
1007 data->cur_trans->bits_per_word)) {
1008 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
1009 spin_lock_irqsave(&data->lock, flags);
1010 pch_spi_set_bits_per_word(data->master,
1011 data->cur_trans->bits_per_word);
1012 spin_unlock_irqrestore(&data->lock, flags);
1013 *bpw = data->cur_trans->bits_per_word;
1014 } else {
1015 *bpw = data->current_msg->spi->bits_per_word;
1016 }
1017 data->bpw_len = data->cur_trans->len / (*bpw / 8);
1018
1019 /* copy Tx Data */
1020 if (data->cur_trans->tx_buf != NULL) {
1021 if (*bpw == 8) {
1022 tx_buf = data->cur_trans->tx_buf;
1023 tx_dma_buf = dma->tx_buf_virt;
1024 for (i = 0; i < data->bpw_len; i++)
1025 *tx_dma_buf++ = *tx_buf++;
1026 } else {
1027 tx_sbuf = data->cur_trans->tx_buf;
1028 tx_dma_sbuf = dma->tx_buf_virt;
1029 for (i = 0; i < data->bpw_len; i++)
1030 *tx_dma_sbuf++ = *tx_sbuf++;
1031 }
1032 }
1033 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1034 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1035 size = PCH_DMA_TRANS_SIZE;
1036 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1037 } else {
1038 num = 1;
1039 size = data->bpw_len;
1040 rem = data->bpw_len;
1041 }
1042 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1043 __func__, num, size, rem);
1044 spin_lock_irqsave(&data->lock, flags);
1045
1046 /* set receive fifo threshold and transmit fifo threshold */
1047 pch_spi_setclr_reg(data->master, PCH_SPCR,
1048 ((size - 1) << SPCR_RFIC_FIELD) |
1049 (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1050 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1051
1052 spin_unlock_irqrestore(&data->lock, flags);
1053
1054 /* RX */
1055 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1056 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1057 /* offset, length setting */
1058 sg = dma->sg_rx_p;
1059 for (i = 0; i < num; i++, sg++) {
1060 if (i == (num - 2)) {
1061 sg->offset = size * i;
1062 sg->offset = sg->offset * (*bpw / 8);
1063 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1064 sg->offset);
1065 sg_dma_len(sg) = rem;
1066 } else if (i == (num - 1)) {
1067 sg->offset = size * (i - 1) + rem;
1068 sg->offset = sg->offset * (*bpw / 8);
1069 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1070 sg->offset);
1071 sg_dma_len(sg) = size;
1072 } else {
1073 sg->offset = size * i;
1074 sg->offset = sg->offset * (*bpw / 8);
1075 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1076 sg->offset);
1077 sg_dma_len(sg) = size;
1078 }
1079 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1080 }
1081 sg = dma->sg_rx_p;
1082 desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg,
1083 num, DMA_DEV_TO_MEM,
1084 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1085 if (!desc_rx) {
1086 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1087 __func__);
1088 return;
1089 }
1090 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1091 desc_rx->callback = pch_dma_rx_complete;
1092 desc_rx->callback_param = data;
1093 dma->nent = num;
1094 dma->desc_rx = desc_rx;
1095
1096 /* TX */
1097 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1098 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1099 size = PCH_DMA_TRANS_SIZE;
1100 rem = 16;
1101 } else {
1102 num = 1;
1103 size = data->bpw_len;
1104 rem = data->bpw_len;
1105 }
1106
1107 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1108 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1109 /* offset, length setting */
1110 sg = dma->sg_tx_p;
1111 for (i = 0; i < num; i++, sg++) {
1112 if (i == 0) {
1113 sg->offset = 0;
1114 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1115 sg->offset);
1116 sg_dma_len(sg) = rem;
1117 } else {
1118 sg->offset = rem + size * (i - 1);
1119 sg->offset = sg->offset * (*bpw / 8);
1120 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1121 sg->offset);
1122 sg_dma_len(sg) = size;
1123 }
1124 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1125 }
1126 sg = dma->sg_tx_p;
1127 desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx,
1128 sg, num, DMA_MEM_TO_DEV,
1129 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1130 if (!desc_tx) {
1131 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1132 __func__);
1133 return;
1134 }
1135 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1136 desc_tx->callback = NULL;
1137 desc_tx->callback_param = data;
1138 dma->nent = num;
1139 dma->desc_tx = desc_tx;
1140
1141 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1142 "0x2 to SSNXCR\n", __func__);
1143
1144 spin_lock_irqsave(&data->lock, flags);
1145 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1146 desc_rx->tx_submit(desc_rx);
1147 desc_tx->tx_submit(desc_tx);
1148 spin_unlock_irqrestore(&data->lock, flags);
1149
1150 /* reset transfer complete flag */
1151 data->transfer_complete = false;
1152 }
1153
1154 static void pch_spi_process_messages(struct work_struct *pwork)
1155 {
1156 struct spi_message *pmsg;
1157 struct pch_spi_data *data;
1158 int bpw;
1159
1160 data = container_of(pwork, struct pch_spi_data, work);
1161 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1162
1163 spin_lock(&data->lock);
1164 /* check if suspend has been initiated;if yes flush queue */
1165 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1166 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1167 "flushing queue\n", __func__);
1168 list_for_each_entry(pmsg, data->queue.next, queue) {
1169 pmsg->status = -EIO;
1170
1171 if (pmsg->complete != 0) {
1172 spin_unlock(&data->lock);
1173 pmsg->complete(pmsg->context);
1174 spin_lock(&data->lock);
1175 }
1176
1177 /* delete from queue */
1178 list_del_init(&pmsg->queue);
1179 }
1180
1181 spin_unlock(&data->lock);
1182 return;
1183 }
1184
1185 data->bcurrent_msg_processing = true;
1186 dev_dbg(&data->master->dev,
1187 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1188
1189 /* Get the message from the queue and delete it from there. */
1190 data->current_msg = list_entry(data->queue.next, struct spi_message,
1191 queue);
1192
1193 list_del_init(&data->current_msg->queue);
1194
1195 data->current_msg->status = 0;
1196
1197 pch_spi_select_chip(data, data->current_msg->spi);
1198
1199 spin_unlock(&data->lock);
1200
1201 if (data->use_dma)
1202 pch_spi_request_dma(data,
1203 data->current_msg->spi->bits_per_word);
1204 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1205 do {
1206 /* If we are already processing a message get the next
1207 transfer structure from the message otherwise retrieve
1208 the 1st transfer request from the message. */
1209 spin_lock(&data->lock);
1210 if (data->cur_trans == NULL) {
1211 data->cur_trans =
1212 list_entry(data->current_msg->transfers.next,
1213 struct spi_transfer, transfer_list);
1214 dev_dbg(&data->master->dev, "%s "
1215 ":Getting 1st transfer message\n", __func__);
1216 } else {
1217 data->cur_trans =
1218 list_entry(data->cur_trans->transfer_list.next,
1219 struct spi_transfer, transfer_list);
1220 dev_dbg(&data->master->dev, "%s "
1221 ":Getting next transfer message\n", __func__);
1222 }
1223 spin_unlock(&data->lock);
1224
1225 if (data->use_dma) {
1226 pch_spi_handle_dma(data, &bpw);
1227 if (!pch_spi_start_transfer(data))
1228 goto out;
1229 pch_spi_copy_rx_data_for_dma(data, bpw);
1230 } else {
1231 pch_spi_set_tx(data, &bpw);
1232 pch_spi_set_ir(data);
1233 pch_spi_copy_rx_data(data, bpw);
1234 kfree(data->pkt_rx_buff);
1235 data->pkt_rx_buff = NULL;
1236 kfree(data->pkt_tx_buff);
1237 data->pkt_tx_buff = NULL;
1238 }
1239 /* increment message count */
1240 data->current_msg->actual_length += data->cur_trans->len;
1241
1242 dev_dbg(&data->master->dev,
1243 "%s:data->current_msg->actual_length=%d\n",
1244 __func__, data->current_msg->actual_length);
1245
1246 /* check for delay */
1247 if (data->cur_trans->delay_usecs) {
1248 dev_dbg(&data->master->dev, "%s:"
1249 "delay in usec=%d\n", __func__,
1250 data->cur_trans->delay_usecs);
1251 udelay(data->cur_trans->delay_usecs);
1252 }
1253
1254 spin_lock(&data->lock);
1255
1256 /* No more transfer in this message. */
1257 if ((data->cur_trans->transfer_list.next) ==
1258 &(data->current_msg->transfers)) {
1259 pch_spi_nomore_transfer(data);
1260 }
1261
1262 spin_unlock(&data->lock);
1263
1264 } while (data->cur_trans != NULL);
1265
1266 out:
1267 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1268 if (data->use_dma)
1269 pch_spi_release_dma(data);
1270 }
1271
1272 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1273 struct pch_spi_data *data)
1274 {
1275 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1276
1277 /* free workqueue */
1278 if (data->wk != NULL) {
1279 destroy_workqueue(data->wk);
1280 data->wk = NULL;
1281 dev_dbg(&board_dat->pdev->dev,
1282 "%s destroy_workqueue invoked successfully\n",
1283 __func__);
1284 }
1285 }
1286
1287 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1288 struct pch_spi_data *data)
1289 {
1290 int retval = 0;
1291
1292 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1293
1294 /* create workqueue */
1295 data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1296 if (!data->wk) {
1297 dev_err(&board_dat->pdev->dev,
1298 "%s create_singlet hread_workqueue failed\n", __func__);
1299 retval = -EBUSY;
1300 goto err_return;
1301 }
1302
1303 /* reset PCH SPI h/w */
1304 pch_spi_reset(data->master);
1305 dev_dbg(&board_dat->pdev->dev,
1306 "%s pch_spi_reset invoked successfully\n", __func__);
1307
1308 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1309
1310 err_return:
1311 if (retval != 0) {
1312 dev_err(&board_dat->pdev->dev,
1313 "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1314 pch_spi_free_resources(board_dat, data);
1315 }
1316
1317 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1318
1319 return retval;
1320 }
1321
1322 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1323 struct pch_spi_data *data)
1324 {
1325 struct pch_spi_dma_ctrl *dma;
1326
1327 dma = &data->dma;
1328 if (dma->tx_buf_dma)
1329 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1330 dma->tx_buf_virt, dma->tx_buf_dma);
1331 if (dma->rx_buf_dma)
1332 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1333 dma->rx_buf_virt, dma->rx_buf_dma);
1334 return;
1335 }
1336
1337 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1338 struct pch_spi_data *data)
1339 {
1340 struct pch_spi_dma_ctrl *dma;
1341
1342 dma = &data->dma;
1343 /* Get Consistent memory for Tx DMA */
1344 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1345 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1346 /* Get Consistent memory for Rx DMA */
1347 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1348 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1349 }
1350
1351 static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1352 {
1353 int ret;
1354 struct spi_master *master;
1355 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1356 struct pch_spi_data *data;
1357
1358 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1359
1360 master = spi_alloc_master(&board_dat->pdev->dev,
1361 sizeof(struct pch_spi_data));
1362 if (!master) {
1363 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1364 plat_dev->id);
1365 return -ENOMEM;
1366 }
1367
1368 data = spi_master_get_devdata(master);
1369 data->master = master;
1370
1371 platform_set_drvdata(plat_dev, data);
1372
1373 /* baseaddress + address offset) */
1374 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1375 PCH_ADDRESS_SIZE * plat_dev->id;
1376 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1377 PCH_ADDRESS_SIZE * plat_dev->id;
1378 if (!data->io_remap_addr) {
1379 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1380 ret = -ENOMEM;
1381 goto err_pci_iomap;
1382 }
1383
1384 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1385 plat_dev->id, data->io_remap_addr);
1386
1387 /* initialize members of SPI master */
1388 master->bus_num = -1;
1389 master->num_chipselect = PCH_MAX_CS;
1390 master->setup = pch_spi_setup;
1391 master->transfer = pch_spi_transfer;
1392
1393 data->board_dat = board_dat;
1394 data->plat_dev = plat_dev;
1395 data->n_curnt_chip = 255;
1396 data->status = STATUS_RUNNING;
1397 data->ch = plat_dev->id;
1398 data->use_dma = use_dma;
1399
1400 INIT_LIST_HEAD(&data->queue);
1401 spin_lock_init(&data->lock);
1402 INIT_WORK(&data->work, pch_spi_process_messages);
1403 init_waitqueue_head(&data->wait);
1404
1405 ret = pch_spi_get_resources(board_dat, data);
1406 if (ret) {
1407 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1408 goto err_spi_get_resources;
1409 }
1410
1411 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1412 IRQF_SHARED, KBUILD_MODNAME, data);
1413 if (ret) {
1414 dev_err(&plat_dev->dev,
1415 "%s request_irq failed\n", __func__);
1416 goto err_request_irq;
1417 }
1418 data->irq_reg_sts = true;
1419
1420 pch_spi_set_master_mode(master);
1421
1422 ret = spi_register_master(master);
1423 if (ret != 0) {
1424 dev_err(&plat_dev->dev,
1425 "%s spi_register_master FAILED\n", __func__);
1426 goto err_spi_register_master;
1427 }
1428
1429 if (use_dma) {
1430 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1431 pch_alloc_dma_buf(board_dat, data);
1432 }
1433
1434 return 0;
1435
1436 err_spi_register_master:
1437 free_irq(board_dat->pdev->irq, board_dat);
1438 err_request_irq:
1439 pch_spi_free_resources(board_dat, data);
1440 err_spi_get_resources:
1441 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1442 err_pci_iomap:
1443 spi_master_put(master);
1444
1445 return ret;
1446 }
1447
1448 static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1449 {
1450 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1451 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1452 int count;
1453 unsigned long flags;
1454
1455 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1456 __func__, plat_dev->id, board_dat->pdev->irq);
1457
1458 if (use_dma)
1459 pch_free_dma_buf(board_dat, data);
1460
1461 /* check for any pending messages; no action is taken if the queue
1462 * is still full; but at least we tried. Unload anyway */
1463 count = 500;
1464 spin_lock_irqsave(&data->lock, flags);
1465 data->status = STATUS_EXITING;
1466 while ((list_empty(&data->queue) == 0) && --count) {
1467 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1468 __func__);
1469 spin_unlock_irqrestore(&data->lock, flags);
1470 msleep(PCH_SLEEP_TIME);
1471 spin_lock_irqsave(&data->lock, flags);
1472 }
1473 spin_unlock_irqrestore(&data->lock, flags);
1474
1475 pch_spi_free_resources(board_dat, data);
1476 /* disable interrupts & free IRQ */
1477 if (data->irq_reg_sts) {
1478 /* disable interrupts */
1479 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1480 data->irq_reg_sts = false;
1481 free_irq(board_dat->pdev->irq, data);
1482 }
1483
1484 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1485 spi_unregister_master(data->master);
1486 spi_master_put(data->master);
1487 platform_set_drvdata(plat_dev, NULL);
1488
1489 return 0;
1490 }
1491 #ifdef CONFIG_PM
1492 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1493 pm_message_t state)
1494 {
1495 u8 count;
1496 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1497 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1498
1499 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1500
1501 if (!board_dat) {
1502 dev_err(&pd_dev->dev,
1503 "%s pci_get_drvdata returned NULL\n", __func__);
1504 return -EFAULT;
1505 }
1506
1507 /* check if the current message is processed:
1508 Only after thats done the transfer will be suspended */
1509 count = 255;
1510 while ((--count) > 0) {
1511 if (!(data->bcurrent_msg_processing))
1512 break;
1513 msleep(PCH_SLEEP_TIME);
1514 }
1515
1516 /* Free IRQ */
1517 if (data->irq_reg_sts) {
1518 /* disable all interrupts */
1519 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1520 pch_spi_reset(data->master);
1521 free_irq(board_dat->pdev->irq, data);
1522
1523 data->irq_reg_sts = false;
1524 dev_dbg(&pd_dev->dev,
1525 "%s free_irq invoked successfully.\n", __func__);
1526 }
1527
1528 return 0;
1529 }
1530
1531 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1532 {
1533 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1534 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1535 int retval;
1536
1537 if (!board_dat) {
1538 dev_err(&pd_dev->dev,
1539 "%s pci_get_drvdata returned NULL\n", __func__);
1540 return -EFAULT;
1541 }
1542
1543 if (!data->irq_reg_sts) {
1544 /* register IRQ */
1545 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1546 IRQF_SHARED, KBUILD_MODNAME, data);
1547 if (retval < 0) {
1548 dev_err(&pd_dev->dev,
1549 "%s request_irq failed\n", __func__);
1550 return retval;
1551 }
1552
1553 /* reset PCH SPI h/w */
1554 pch_spi_reset(data->master);
1555 pch_spi_set_master_mode(data->master);
1556 data->irq_reg_sts = true;
1557 }
1558 return 0;
1559 }
1560 #else
1561 #define pch_spi_pd_suspend NULL
1562 #define pch_spi_pd_resume NULL
1563 #endif
1564
1565 static struct platform_driver pch_spi_pd_driver = {
1566 .driver = {
1567 .name = "pch-spi",
1568 .owner = THIS_MODULE,
1569 },
1570 .probe = pch_spi_pd_probe,
1571 .remove = __devexit_p(pch_spi_pd_remove),
1572 .suspend = pch_spi_pd_suspend,
1573 .resume = pch_spi_pd_resume
1574 };
1575
1576 static int __devinit pch_spi_probe(struct pci_dev *pdev,
1577 const struct pci_device_id *id)
1578 {
1579 struct pch_spi_board_data *board_dat;
1580 struct platform_device *pd_dev = NULL;
1581 int retval;
1582 int i;
1583 struct pch_pd_dev_save *pd_dev_save;
1584
1585 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1586 if (!pd_dev_save) {
1587 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1588 return -ENOMEM;
1589 }
1590
1591 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1592 if (!board_dat) {
1593 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1594 retval = -ENOMEM;
1595 goto err_no_mem;
1596 }
1597
1598 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1599 if (retval) {
1600 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1601 goto pci_request_regions;
1602 }
1603
1604 board_dat->pdev = pdev;
1605 board_dat->num = id->driver_data;
1606 pd_dev_save->num = id->driver_data;
1607 pd_dev_save->board_dat = board_dat;
1608
1609 retval = pci_enable_device(pdev);
1610 if (retval) {
1611 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1612 goto pci_enable_device;
1613 }
1614
1615 for (i = 0; i < board_dat->num; i++) {
1616 pd_dev = platform_device_alloc("pch-spi", i);
1617 if (!pd_dev) {
1618 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1619 goto err_platform_device;
1620 }
1621 pd_dev_save->pd_save[i] = pd_dev;
1622 pd_dev->dev.parent = &pdev->dev;
1623
1624 retval = platform_device_add_data(pd_dev, board_dat,
1625 sizeof(*board_dat));
1626 if (retval) {
1627 dev_err(&pdev->dev,
1628 "platform_device_add_data failed\n");
1629 platform_device_put(pd_dev);
1630 goto err_platform_device;
1631 }
1632
1633 retval = platform_device_add(pd_dev);
1634 if (retval) {
1635 dev_err(&pdev->dev, "platform_device_add failed\n");
1636 platform_device_put(pd_dev);
1637 goto err_platform_device;
1638 }
1639 }
1640
1641 pci_set_drvdata(pdev, pd_dev_save);
1642
1643 return 0;
1644
1645 err_platform_device:
1646 pci_disable_device(pdev);
1647 pci_enable_device:
1648 pci_release_regions(pdev);
1649 pci_request_regions:
1650 kfree(board_dat);
1651 err_no_mem:
1652 kfree(pd_dev_save);
1653
1654 return retval;
1655 }
1656
1657 static void __devexit pch_spi_remove(struct pci_dev *pdev)
1658 {
1659 int i;
1660 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1661
1662 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1663
1664 for (i = 0; i < pd_dev_save->num; i++)
1665 platform_device_unregister(pd_dev_save->pd_save[i]);
1666
1667 pci_disable_device(pdev);
1668 pci_release_regions(pdev);
1669 kfree(pd_dev_save->board_dat);
1670 kfree(pd_dev_save);
1671 }
1672
1673 #ifdef CONFIG_PM
1674 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1675 {
1676 int retval;
1677 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1678
1679 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1680
1681 pd_dev_save->board_dat->suspend_sts = true;
1682
1683 /* save config space */
1684 retval = pci_save_state(pdev);
1685 if (retval == 0) {
1686 pci_enable_wake(pdev, PCI_D3hot, 0);
1687 pci_disable_device(pdev);
1688 pci_set_power_state(pdev, PCI_D3hot);
1689 } else {
1690 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1691 }
1692
1693 return retval;
1694 }
1695
1696 static int pch_spi_resume(struct pci_dev *pdev)
1697 {
1698 int retval;
1699 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1700 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1701
1702 pci_set_power_state(pdev, PCI_D0);
1703 pci_restore_state(pdev);
1704
1705 retval = pci_enable_device(pdev);
1706 if (retval < 0) {
1707 dev_err(&pdev->dev,
1708 "%s pci_enable_device failed\n", __func__);
1709 } else {
1710 pci_enable_wake(pdev, PCI_D3hot, 0);
1711
1712 /* set suspend status to false */
1713 pd_dev_save->board_dat->suspend_sts = false;
1714 }
1715
1716 return retval;
1717 }
1718 #else
1719 #define pch_spi_suspend NULL
1720 #define pch_spi_resume NULL
1721
1722 #endif
1723
1724 static struct pci_driver pch_spi_pcidev_driver = {
1725 .name = "pch_spi",
1726 .id_table = pch_spi_pcidev_id,
1727 .probe = pch_spi_probe,
1728 .remove = pch_spi_remove,
1729 .suspend = pch_spi_suspend,
1730 .resume = pch_spi_resume,
1731 };
1732
1733 static int __init pch_spi_init(void)
1734 {
1735 int ret;
1736 ret = platform_driver_register(&pch_spi_pd_driver);
1737 if (ret)
1738 return ret;
1739
1740 ret = pci_register_driver(&pch_spi_pcidev_driver);
1741 if (ret)
1742 return ret;
1743
1744 return 0;
1745 }
1746 module_init(pch_spi_init);
1747
1748 static void __exit pch_spi_exit(void)
1749 {
1750 pci_unregister_driver(&pch_spi_pcidev_driver);
1751 platform_driver_unregister(&pch_spi_pd_driver);
1752 }
1753 module_exit(pch_spi_exit);
1754
1755 module_param(use_dma, int, 0644);
1756 MODULE_PARM_DESC(use_dma,
1757 "to use DMA for data transfers pass 1 else 0; default 1");
1758
1759 MODULE_LICENSE("GPL");
1760 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");