drivers/staging/iio/gyro/adxrs450.h

   1 #ifndef SPI_ADXRS450_H_
   2 #define SPI_ADXRS450_H_
   3
   4 #define ADXRS450_STARTUP_DELAY  50 /* ms */
   5
   6 /* The MSB for the spi commands */
   7 #define ADXRS450_SENSOR_DATA    0x20
   8 #define ADXRS450_WRITE_DATA     0x40
   9 #define ADXRS450_READ_DATA      0x80
  10
  11 #define ADXRS450_RATE1  0x00    /* Rate Registers */
  12 #define ADXRS450_TEMP1  0x02    /* Temperature Registers */
  13 #define ADXRS450_LOCST1 0x04    /* Low CST Memory Registers */
  14 #define ADXRS450_HICST1 0x06    /* High CST Memory Registers */
  15 #define ADXRS450_QUAD1  0x08    /* Quad Memory Registers */
  16 #define ADXRS450_FAULT1 0x0A    /* Fault Registers */
  17 #define ADXRS450_PID1   0x0C    /* Part ID Register 1 */
  18 #define ADXRS450_SNH    0x0E    /* Serial Number Registers, 4 bytes */
  19 #define ADXRS450_SNL    0x10
  20 #define ADXRS450_DNC1   0x12    /* Dynamic Null Correction Registers */
  21 /* Check bits */
  22 #define ADXRS450_P      0x01
  23 #define ADXRS450_CHK    0x02
  24 #define ADXRS450_CST    0x04
  25 #define ADXRS450_PWR    0x08
  26 #define ADXRS450_POR    0x10
  27 #define ADXRS450_NVM    0x20
  28 #define ADXRS450_Q      0x40
  29 #define ADXRS450_PLL    0x80
  30 #define ADXRS450_UV     0x100
  31 #define ADXRS450_OV     0x200
  32 #define ADXRS450_AMP    0x400
  33 #define ADXRS450_FAIL   0x800
  34
  35 #define ADXRS450_WRERR_MASK     (0x7 << 29)
  36
  37 #define ADXRS450_MAX_RX 4
  38 #define ADXRS450_MAX_TX 4
  39
  40 #define ADXRS450_GET_ST(a)      ((a >> 26) & 0x3)
  41
  42 enum {
  43         ID_ADXRS450,
  44         ID_ADXRS453,
  45 };
  46
  47 /**
  48  * struct adxrs450_state - device instance specific data
  49  * @us:                 actual spi_device
  50  * @buf_lock:           mutex to protect tx and rx
  51  * @tx:                 transmit buffer
  52  * @rx:                 recieve buffer
  53  **/
  54 struct adxrs450_state {
  55         struct spi_device       *us;
  56         struct mutex            buf_lock;
  57         u8                      tx[ADXRS450_MAX_RX] ____cacheline_aligned;
  58         u8                      rx[ADXRS450_MAX_TX];
  59
  60 };
  61
  62 #endif /* SPI_ADXRS450_H_ */