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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / tty / serial / 8250 / 8250_pci.c
blob858dca865d6ab6b35fd04beb21c826d892050f76
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_core.h>
21 #include <linux/8250_pci.h>
22 #include <linux/bitops.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28
29 #undef SERIAL_DEBUG_PCI
30
31 /*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37 struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
42 int (*probe)(struct pci_dev *dev);
43 int (*init)(struct pci_dev *dev);
44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
46 struct uart_port *, int);
47 void (*exit)(struct pci_dev *dev);
48 };
49
50 #define PCI_NUM_BAR_RESOURCES 6
51
52 struct serial_private {
53 struct pci_dev *dev;
54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58 };
59
60 static int pci_default_setup(struct serial_private*,
61 const struct pciserial_board*, struct uart_port*, int);
62
63 static void moan_device(const char *str, struct pci_dev *dev)
64 {
65 printk(KERN_WARNING
66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73 }
74
75 static int
76 setup_port(struct serial_private *priv, struct uart_port *port,
77 int bar, int offset, int regshift)
78 {
79 struct pci_dev *dev = priv->dev;
80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
85 base = pci_resource_start(dev, bar);
86
87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
95 port->iotype = UPIO_MEM;
96 port->iobase = 0;
97 port->mapbase = base + offset;
98 port->membase = priv->remapped_bar[bar] + offset;
99 port->regshift = regshift;
100 } else {
101 port->iotype = UPIO_PORT;
102 port->iobase = base + offset;
103 port->mapbase = 0;
104 port->membase = NULL;
105 port->regshift = 0;
106 }
107 return 0;
108 }
109
110 /*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113 static int addidata_apci7800_setup(struct serial_private *priv,
114 const struct pciserial_board *board,
115 struct uart_port *port, int idx)
116 {
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134 }
135
136 /*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140 static int
141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
142 struct uart_port *port, int idx)
143 {
144 unsigned int bar, offset = board->first_offset;
145
146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
154 return setup_port(priv, port, bar, offset, board->reg_shift);
155 }
156
157 /*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
164 static int pci_hp_diva_init(struct pci_dev *dev)
165 {
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
183 rc = 1;
184 break;
185 }
186
187 return rc;
188 }
189
190 /*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194 static int
195 pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
197 struct uart_port *port, int idx)
198 {
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
202 switch (priv->dev->subsystem_device) {
203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
219 return setup_port(priv, port, bar, offset, board->reg_shift);
220 }
221
222 /*
223 * Added for EKF Intel i960 serial boards
224 */
225 static int pci_inteli960ni_init(struct pci_dev *dev)
226 {
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239 }
240
241 /*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
247 static int pci_plx9050_init(struct pci_dev *dev)
248 {
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260 irq_config = 0x43;
261
262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
273 /*
274 * enable/disable interrupts
275 */
276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288 }
289
290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291 {
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310 }
311
312 #define NI8420_INT_ENABLE_REG 0x38
313 #define NI8420_INT_ENABLE_BIT 0x2000
314
315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316 {
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336 }
337
338
339 /* MITE registers */
340 #define MITE_IOWBSR1 0xc4
341 #define MITE_IOWCR1 0xf4
342 #define MITE_LCIMR1 0x08
343 #define MITE_LCIMR2 0x10
344
345 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348 {
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367 }
368
369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370 static int
371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
372 struct uart_port *port, int idx)
373 {
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
387 return setup_port(priv, port, bar, offset, board->reg_shift);
388 }
389
390 /*
391 * This does initialization for PMC OCTALPRO cards:
392 * maps the device memory, resets the UARTs (needed, bc
393 * if the module is removed and inserted again, the card
394 * is in the sleep mode) and enables global interrupt.
395 */
396
397 /* global control register offset for SBS PMC-OctalPro */
398 #define OCT_REG_CR_OFF 0x500
399
400 static int sbs_init(struct pci_dev *dev)
401 {
402 u8 __iomem *p;
403
404 p = pci_ioremap_bar(dev, 0);
405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
409 writeb(0x10, p + OCT_REG_CR_OFF);
410 udelay(50);
411 writeb(0x0, p + OCT_REG_CR_OFF);
412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418 }
419
420 /*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424 static void __devexit sbs_exit(struct pci_dev *dev)
425 {
426 u8 __iomem *p;
427
428 p = pci_ioremap_bar(dev, 0);
429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
431 writeb(0, p + OCT_REG_CR_OFF);
432 iounmap(p);
433 }
434
435 /*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
438 * (except cards equipped with 4 UARTs) and initial clocking settings
439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447 *
448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465 static int pci_siig10x_init(struct pci_dev *dev)
466 {
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490 }
491
492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495 static int pci_siig20x_init(struct pci_dev *dev)
496 {
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510 }
511
512 static int pci_siig_init(struct pci_dev *dev)
513 {
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523 }
524
525 static int pci_siig_setup(struct serial_private *priv,
526 const struct pciserial_board *board,
527 struct uart_port *port, int idx)
528 {
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537 }
538
539 /*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
544 static const unsigned short timedia_single_port[] = {
545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546 };
547
548 static const unsigned short timedia_dual_port[] = {
549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554 };
555
556 static const unsigned short timedia_quad_port[] = {
557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561 };
562
563 static const unsigned short timedia_eight_port[] = {
564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566 };
567
568 static const struct timedia_struct {
569 int num;
570 const unsigned short *ids;
571 } timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
575 { 8, timedia_eight_port }
576 };
577
578 /*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584 static int pci_timedia_probe(struct pci_dev *dev)
585 {
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598 }
599
600 static int pci_timedia_init(struct pci_dev *dev)
601 {
602 const unsigned short *ids;
603 int i, j;
604
605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612 }
613
614 /*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618 static int
619 pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
621 struct uart_port *port, int idx)
622 {
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
638 /* FALLTHROUGH */
639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
646 return setup_port(priv, port, bar, offset, board->reg_shift);
647 }
648
649 /*
650 * Some Titan cards are also a little weird
651 */
652 static int
653 titan_400l_800l_setup(struct serial_private *priv,
654 const struct pciserial_board *board,
655 struct uart_port *port, int idx)
656 {
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
671 return setup_port(priv, port, bar, offset, board->reg_shift);
672 }
673
674 static int pci_xircom_init(struct pci_dev *dev)
675 {
676 msleep(100);
677 return 0;
678 }
679
680 static int pci_ni8420_init(struct pci_dev *dev)
681 {
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703 }
704
705 #define MITE_IOWBSR1_WSIZE 0xa
706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
707 #define MITE_IOWBSR1_WENAB (1 << 7)
708 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
709 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712 static int pci_ni8430_init(struct pci_dev *dev)
713 {
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747 }
748
749 /* UART Port Control Register */
750 #define NI8430_PORTCON 0x0f
751 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753 static int
754 pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
756 struct uart_port *port, int idx)
757 {
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
772 /* enable the transceiver */
773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779 }
780
781 static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_port *port, int idx)
784 {
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797 }
798
799 /* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807 static int pci_netmos_9900_numports(struct pci_dev *dev)
808 {
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836 }
837
838 static int pci_netmos_init(struct pci_dev *dev)
839 {
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
845 return 0;
846
847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
865 if (num_serial == 0)
866 return -ENODEV;
867
868 return num_serial;
869 }
870
871 /*
872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881 /* registers */
882 #define ITE_887x_MISCR 0x9c
883 #define ITE_887x_INTCBAR 0x78
884 #define ITE_887x_UARTBAR 0x7c
885 #define ITE_887x_PS0BAR 0x10
886 #define ITE_887x_POSIO0 0x60
887
888 /* I/O space size */
889 #define ITE_887x_IOSIZE 32
890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
891 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
893 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895 #define ITE_887x_POSIO_SPEED (3 << 29)
896 /* enable IO_Space bit */
897 #define ITE_887x_POSIO_ENABLE (1 << 31)
898
899 static int pci_ite887x_init(struct pci_dev *dev)
900 {
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 printk(KERN_ERR "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991 }
992
993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994 {
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 printk(KERN_DEBUG
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_port *port, int idx)
1038 {
1039 unsigned int bar, offset = board->first_offset, maxnr;
1040
1041 bar = FL_GET_BASE(board->flags);
1042 if (board->flags & FL_BASE_BARS)
1043 bar += idx;
1044 else
1045 offset += idx * board->uart_offset;
1046
1047 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048 (board->reg_shift + 3);
1049
1050 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051 return 1;
1052
1053 return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058 const struct pciserial_board *board,
1059 struct uart_port *port, int idx)
1060 {
1061 int ret;
1062
1063 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064 port->iotype = UPIO_MEM32;
1065 port->type = PORT_XSCALE;
1066 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067 port->regshift = 2;
1068
1069 return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074 const struct pciserial_board *board,
1075 struct uart_port *port, int idx)
1076 {
1077 return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int skip_tx_en_setup(struct serial_private *priv,
1081 const struct pciserial_board *board,
1082 struct uart_port *port, int idx)
1083 {
1084 port->flags |= UPF_NO_TXEN_TEST;
1085 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086 "[%04x:%04x] subsystem [%04x:%04x]\n",
1087 priv->dev->vendor,
1088 priv->dev->device,
1089 priv->dev->subsystem_vendor,
1090 priv->dev->subsystem_device);
1091
1092 return pci_default_setup(priv, board, port, idx);
1093 }
1094
1095 static int kt_serial_setup(struct serial_private *priv,
1096 const struct pciserial_board *board,
1097 struct uart_port *port, int idx)
1098 {
1099 port->flags |= UPF_BUG_THRE;
1100 return skip_tx_en_setup(priv, board, port, idx);
1101 }
1102
1103 static int pci_eg20t_init(struct pci_dev *dev)
1104 {
1105 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1106 return -ENODEV;
1107 #else
1108 return 0;
1109 #endif
1110 }
1111
1112 static int
1113 pci_xr17c154_setup(struct serial_private *priv,
1114 const struct pciserial_board *board,
1115 struct uart_port *port, int idx)
1116 {
1117 port->flags |= UPF_EXAR_EFR;
1118 return pci_default_setup(priv, board, port, idx);
1119 }
1120
1121 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1122 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1123 #define PCI_DEVICE_ID_OCTPRO 0x0001
1124 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1125 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1126 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1127 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1128 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1129 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1130 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1131 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1132 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1133 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1134 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1135 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1136 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1137 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1138 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1139 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1140 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1141 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1142 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1143 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1144 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1145 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1146 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1147 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1148 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1149 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1150 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1151
1152 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1153 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1154
1155 /*
1156 * Master list of serial port init/setup/exit quirks.
1157 * This does not describe the general nature of the port.
1158 * (ie, baud base, number and location of ports, etc)
1159 *
1160 * This list is ordered alphabetically by vendor then device.
1161 * Specific entries must come before more generic entries.
1162 */
1163 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1164 /*
1165 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1166 */
1167 {
1168 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1169 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .setup = addidata_apci7800_setup,
1173 },
1174 /*
1175 * AFAVLAB cards - these may be called via parport_serial
1176 * It is not clear whether this applies to all products.
1177 */
1178 {
1179 .vendor = PCI_VENDOR_ID_AFAVLAB,
1180 .device = PCI_ANY_ID,
1181 .subvendor = PCI_ANY_ID,
1182 .subdevice = PCI_ANY_ID,
1183 .setup = afavlab_setup,
1184 },
1185 /*
1186 * HP Diva
1187 */
1188 {
1189 .vendor = PCI_VENDOR_ID_HP,
1190 .device = PCI_DEVICE_ID_HP_DIVA,
1191 .subvendor = PCI_ANY_ID,
1192 .subdevice = PCI_ANY_ID,
1193 .init = pci_hp_diva_init,
1194 .setup = pci_hp_diva_setup,
1195 },
1196 /*
1197 * Intel
1198 */
1199 {
1200 .vendor = PCI_VENDOR_ID_INTEL,
1201 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1202 .subvendor = 0xe4bf,
1203 .subdevice = PCI_ANY_ID,
1204 .init = pci_inteli960ni_init,
1205 .setup = pci_default_setup,
1206 },
1207 {
1208 .vendor = PCI_VENDOR_ID_INTEL,
1209 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1210 .subvendor = PCI_ANY_ID,
1211 .subdevice = PCI_ANY_ID,
1212 .setup = skip_tx_en_setup,
1213 },
1214 {
1215 .vendor = PCI_VENDOR_ID_INTEL,
1216 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1217 .subvendor = PCI_ANY_ID,
1218 .subdevice = PCI_ANY_ID,
1219 .setup = skip_tx_en_setup,
1220 },
1221 {
1222 .vendor = PCI_VENDOR_ID_INTEL,
1223 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1224 .subvendor = PCI_ANY_ID,
1225 .subdevice = PCI_ANY_ID,
1226 .setup = skip_tx_en_setup,
1227 },
1228 {
1229 .vendor = PCI_VENDOR_ID_INTEL,
1230 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1231 .subvendor = PCI_ANY_ID,
1232 .subdevice = PCI_ANY_ID,
1233 .setup = ce4100_serial_setup,
1234 },
1235 {
1236 .vendor = PCI_VENDOR_ID_INTEL,
1237 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1238 .subvendor = PCI_ANY_ID,
1239 .subdevice = PCI_ANY_ID,
1240 .setup = kt_serial_setup,
1241 },
1242 /*
1243 * ITE
1244 */
1245 {
1246 .vendor = PCI_VENDOR_ID_ITE,
1247 .device = PCI_DEVICE_ID_ITE_8872,
1248 .subvendor = PCI_ANY_ID,
1249 .subdevice = PCI_ANY_ID,
1250 .init = pci_ite887x_init,
1251 .setup = pci_default_setup,
1252 .exit = __devexit_p(pci_ite887x_exit),
1253 },
1254 /*
1255 * National Instruments
1256 */
1257 {
1258 .vendor = PCI_VENDOR_ID_NI,
1259 .device = PCI_DEVICE_ID_NI_PCI23216,
1260 .subvendor = PCI_ANY_ID,
1261 .subdevice = PCI_ANY_ID,
1262 .init = pci_ni8420_init,
1263 .setup = pci_default_setup,
1264 .exit = __devexit_p(pci_ni8420_exit),
1265 },
1266 {
1267 .vendor = PCI_VENDOR_ID_NI,
1268 .device = PCI_DEVICE_ID_NI_PCI2328,
1269 .subvendor = PCI_ANY_ID,
1270 .subdevice = PCI_ANY_ID,
1271 .init = pci_ni8420_init,
1272 .setup = pci_default_setup,
1273 .exit = __devexit_p(pci_ni8420_exit),
1274 },
1275 {
1276 .vendor = PCI_VENDOR_ID_NI,
1277 .device = PCI_DEVICE_ID_NI_PCI2324,
1278 .subvendor = PCI_ANY_ID,
1279 .subdevice = PCI_ANY_ID,
1280 .init = pci_ni8420_init,
1281 .setup = pci_default_setup,
1282 .exit = __devexit_p(pci_ni8420_exit),
1283 },
1284 {
1285 .vendor = PCI_VENDOR_ID_NI,
1286 .device = PCI_DEVICE_ID_NI_PCI2322,
1287 .subvendor = PCI_ANY_ID,
1288 .subdevice = PCI_ANY_ID,
1289 .init = pci_ni8420_init,
1290 .setup = pci_default_setup,
1291 .exit = __devexit_p(pci_ni8420_exit),
1292 },
1293 {
1294 .vendor = PCI_VENDOR_ID_NI,
1295 .device = PCI_DEVICE_ID_NI_PCI2324I,
1296 .subvendor = PCI_ANY_ID,
1297 .subdevice = PCI_ANY_ID,
1298 .init = pci_ni8420_init,
1299 .setup = pci_default_setup,
1300 .exit = __devexit_p(pci_ni8420_exit),
1301 },
1302 {
1303 .vendor = PCI_VENDOR_ID_NI,
1304 .device = PCI_DEVICE_ID_NI_PCI2322I,
1305 .subvendor = PCI_ANY_ID,
1306 .subdevice = PCI_ANY_ID,
1307 .init = pci_ni8420_init,
1308 .setup = pci_default_setup,
1309 .exit = __devexit_p(pci_ni8420_exit),
1310 },
1311 {
1312 .vendor = PCI_VENDOR_ID_NI,
1313 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1314 .subvendor = PCI_ANY_ID,
1315 .subdevice = PCI_ANY_ID,
1316 .init = pci_ni8420_init,
1317 .setup = pci_default_setup,
1318 .exit = __devexit_p(pci_ni8420_exit),
1319 },
1320 {
1321 .vendor = PCI_VENDOR_ID_NI,
1322 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1323 .subvendor = PCI_ANY_ID,
1324 .subdevice = PCI_ANY_ID,
1325 .init = pci_ni8420_init,
1326 .setup = pci_default_setup,
1327 .exit = __devexit_p(pci_ni8420_exit),
1328 },
1329 {
1330 .vendor = PCI_VENDOR_ID_NI,
1331 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1332 .subvendor = PCI_ANY_ID,
1333 .subdevice = PCI_ANY_ID,
1334 .init = pci_ni8420_init,
1335 .setup = pci_default_setup,
1336 .exit = __devexit_p(pci_ni8420_exit),
1337 },
1338 {
1339 .vendor = PCI_VENDOR_ID_NI,
1340 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1341 .subvendor = PCI_ANY_ID,
1342 .subdevice = PCI_ANY_ID,
1343 .init = pci_ni8420_init,
1344 .setup = pci_default_setup,
1345 .exit = __devexit_p(pci_ni8420_exit),
1346 },
1347 {
1348 .vendor = PCI_VENDOR_ID_NI,
1349 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1350 .subvendor = PCI_ANY_ID,
1351 .subdevice = PCI_ANY_ID,
1352 .init = pci_ni8420_init,
1353 .setup = pci_default_setup,
1354 .exit = __devexit_p(pci_ni8420_exit),
1355 },
1356 {
1357 .vendor = PCI_VENDOR_ID_NI,
1358 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1359 .subvendor = PCI_ANY_ID,
1360 .subdevice = PCI_ANY_ID,
1361 .init = pci_ni8420_init,
1362 .setup = pci_default_setup,
1363 .exit = __devexit_p(pci_ni8420_exit),
1364 },
1365 {
1366 .vendor = PCI_VENDOR_ID_NI,
1367 .device = PCI_ANY_ID,
1368 .subvendor = PCI_ANY_ID,
1369 .subdevice = PCI_ANY_ID,
1370 .init = pci_ni8430_init,
1371 .setup = pci_ni8430_setup,
1372 .exit = __devexit_p(pci_ni8430_exit),
1373 },
1374 /*
1375 * Panacom
1376 */
1377 {
1378 .vendor = PCI_VENDOR_ID_PANACOM,
1379 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1380 .subvendor = PCI_ANY_ID,
1381 .subdevice = PCI_ANY_ID,
1382 .init = pci_plx9050_init,
1383 .setup = pci_default_setup,
1384 .exit = __devexit_p(pci_plx9050_exit),
1385 },
1386 {
1387 .vendor = PCI_VENDOR_ID_PANACOM,
1388 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1389 .subvendor = PCI_ANY_ID,
1390 .subdevice = PCI_ANY_ID,
1391 .init = pci_plx9050_init,
1392 .setup = pci_default_setup,
1393 .exit = __devexit_p(pci_plx9050_exit),
1394 },
1395 /*
1396 * PLX
1397 */
1398 {
1399 .vendor = PCI_VENDOR_ID_PLX,
1400 .device = PCI_DEVICE_ID_PLX_9030,
1401 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1402 .subdevice = PCI_ANY_ID,
1403 .setup = pci_default_setup,
1404 },
1405 {
1406 .vendor = PCI_VENDOR_ID_PLX,
1407 .device = PCI_DEVICE_ID_PLX_9050,
1408 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1409 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1410 .init = pci_plx9050_init,
1411 .setup = pci_default_setup,
1412 .exit = __devexit_p(pci_plx9050_exit),
1413 },
1414 {
1415 .vendor = PCI_VENDOR_ID_PLX,
1416 .device = PCI_DEVICE_ID_PLX_9050,
1417 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1418 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1419 .init = pci_plx9050_init,
1420 .setup = pci_default_setup,
1421 .exit = __devexit_p(pci_plx9050_exit),
1422 },
1423 {
1424 .vendor = PCI_VENDOR_ID_PLX,
1425 .device = PCI_DEVICE_ID_PLX_9050,
1426 .subvendor = PCI_VENDOR_ID_PLX,
1427 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1428 .init = pci_plx9050_init,
1429 .setup = pci_default_setup,
1430 .exit = __devexit_p(pci_plx9050_exit),
1431 },
1432 {
1433 .vendor = PCI_VENDOR_ID_PLX,
1434 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1435 .subvendor = PCI_VENDOR_ID_PLX,
1436 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1437 .init = pci_plx9050_init,
1438 .setup = pci_default_setup,
1439 .exit = __devexit_p(pci_plx9050_exit),
1440 },
1441 /*
1442 * SBS Technologies, Inc., PMC-OCTALPRO 232
1443 */
1444 {
1445 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1446 .device = PCI_DEVICE_ID_OCTPRO,
1447 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1448 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1449 .init = sbs_init,
1450 .setup = sbs_setup,
1451 .exit = __devexit_p(sbs_exit),
1452 },
1453 /*
1454 * SBS Technologies, Inc., PMC-OCTALPRO 422
1455 */
1456 {
1457 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1458 .device = PCI_DEVICE_ID_OCTPRO,
1459 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1460 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1461 .init = sbs_init,
1462 .setup = sbs_setup,
1463 .exit = __devexit_p(sbs_exit),
1464 },
1465 /*
1466 * SBS Technologies, Inc., P-Octal 232
1467 */
1468 {
1469 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1470 .device = PCI_DEVICE_ID_OCTPRO,
1471 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1472 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1473 .init = sbs_init,
1474 .setup = sbs_setup,
1475 .exit = __devexit_p(sbs_exit),
1476 },
1477 /*
1478 * SBS Technologies, Inc., P-Octal 422
1479 */
1480 {
1481 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1482 .device = PCI_DEVICE_ID_OCTPRO,
1483 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1484 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1485 .init = sbs_init,
1486 .setup = sbs_setup,
1487 .exit = __devexit_p(sbs_exit),
1488 },
1489 /*
1490 * SIIG cards - these may be called via parport_serial
1491 */
1492 {
1493 .vendor = PCI_VENDOR_ID_SIIG,
1494 .device = PCI_ANY_ID,
1495 .subvendor = PCI_ANY_ID,
1496 .subdevice = PCI_ANY_ID,
1497 .init = pci_siig_init,
1498 .setup = pci_siig_setup,
1499 },
1500 /*
1501 * Titan cards
1502 */
1503 {
1504 .vendor = PCI_VENDOR_ID_TITAN,
1505 .device = PCI_DEVICE_ID_TITAN_400L,
1506 .subvendor = PCI_ANY_ID,
1507 .subdevice = PCI_ANY_ID,
1508 .setup = titan_400l_800l_setup,
1509 },
1510 {
1511 .vendor = PCI_VENDOR_ID_TITAN,
1512 .device = PCI_DEVICE_ID_TITAN_800L,
1513 .subvendor = PCI_ANY_ID,
1514 .subdevice = PCI_ANY_ID,
1515 .setup = titan_400l_800l_setup,
1516 },
1517 /*
1518 * Timedia cards
1519 */
1520 {
1521 .vendor = PCI_VENDOR_ID_TIMEDIA,
1522 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1523 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1524 .subdevice = PCI_ANY_ID,
1525 .probe = pci_timedia_probe,
1526 .init = pci_timedia_init,
1527 .setup = pci_timedia_setup,
1528 },
1529 {
1530 .vendor = PCI_VENDOR_ID_TIMEDIA,
1531 .device = PCI_ANY_ID,
1532 .subvendor = PCI_ANY_ID,
1533 .subdevice = PCI_ANY_ID,
1534 .setup = pci_timedia_setup,
1535 },
1536 /*
1537 * Exar cards
1538 */
1539 {
1540 .vendor = PCI_VENDOR_ID_EXAR,
1541 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1542 .subvendor = PCI_ANY_ID,
1543 .subdevice = PCI_ANY_ID,
1544 .setup = pci_xr17c154_setup,
1545 },
1546 {
1547 .vendor = PCI_VENDOR_ID_EXAR,
1548 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1549 .subvendor = PCI_ANY_ID,
1550 .subdevice = PCI_ANY_ID,
1551 .setup = pci_xr17c154_setup,
1552 },
1553 {
1554 .vendor = PCI_VENDOR_ID_EXAR,
1555 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1556 .subvendor = PCI_ANY_ID,
1557 .subdevice = PCI_ANY_ID,
1558 .setup = pci_xr17c154_setup,
1559 },
1560 /*
1561 * Xircom cards
1562 */
1563 {
1564 .vendor = PCI_VENDOR_ID_XIRCOM,
1565 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1566 .subvendor = PCI_ANY_ID,
1567 .subdevice = PCI_ANY_ID,
1568 .init = pci_xircom_init,
1569 .setup = pci_default_setup,
1570 },
1571 /*
1572 * Netmos cards - these may be called via parport_serial
1573 */
1574 {
1575 .vendor = PCI_VENDOR_ID_NETMOS,
1576 .device = PCI_ANY_ID,
1577 .subvendor = PCI_ANY_ID,
1578 .subdevice = PCI_ANY_ID,
1579 .init = pci_netmos_init,
1580 .setup = pci_netmos_9900_setup,
1581 },
1582 /*
1583 * For Oxford Semiconductor Tornado based devices
1584 */
1585 {
1586 .vendor = PCI_VENDOR_ID_OXSEMI,
1587 .device = PCI_ANY_ID,
1588 .subvendor = PCI_ANY_ID,
1589 .subdevice = PCI_ANY_ID,
1590 .init = pci_oxsemi_tornado_init,
1591 .setup = pci_default_setup,
1592 },
1593 {
1594 .vendor = PCI_VENDOR_ID_MAINPINE,
1595 .device = PCI_ANY_ID,
1596 .subvendor = PCI_ANY_ID,
1597 .subdevice = PCI_ANY_ID,
1598 .init = pci_oxsemi_tornado_init,
1599 .setup = pci_default_setup,
1600 },
1601 {
1602 .vendor = PCI_VENDOR_ID_DIGI,
1603 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1604 .subvendor = PCI_SUBVENDOR_ID_IBM,
1605 .subdevice = PCI_ANY_ID,
1606 .init = pci_oxsemi_tornado_init,
1607 .setup = pci_default_setup,
1608 },
1609 {
1610 .vendor = PCI_VENDOR_ID_INTEL,
1611 .device = 0x8811,
1612 .init = pci_eg20t_init,
1613 .setup = pci_default_setup,
1614 },
1615 {
1616 .vendor = PCI_VENDOR_ID_INTEL,
1617 .device = 0x8812,
1618 .init = pci_eg20t_init,
1619 .setup = pci_default_setup,
1620 },
1621 {
1622 .vendor = PCI_VENDOR_ID_INTEL,
1623 .device = 0x8813,
1624 .init = pci_eg20t_init,
1625 .setup = pci_default_setup,
1626 },
1627 {
1628 .vendor = PCI_VENDOR_ID_INTEL,
1629 .device = 0x8814,
1630 .init = pci_eg20t_init,
1631 .setup = pci_default_setup,
1632 },
1633 {
1634 .vendor = 0x10DB,
1635 .device = 0x8027,
1636 .init = pci_eg20t_init,
1637 .setup = pci_default_setup,
1638 },
1639 {
1640 .vendor = 0x10DB,
1641 .device = 0x8028,
1642 .init = pci_eg20t_init,
1643 .setup = pci_default_setup,
1644 },
1645 {
1646 .vendor = 0x10DB,
1647 .device = 0x8029,
1648 .init = pci_eg20t_init,
1649 .setup = pci_default_setup,
1650 },
1651 {
1652 .vendor = 0x10DB,
1653 .device = 0x800C,
1654 .init = pci_eg20t_init,
1655 .setup = pci_default_setup,
1656 },
1657 {
1658 .vendor = 0x10DB,
1659 .device = 0x800D,
1660 .init = pci_eg20t_init,
1661 .setup = pci_default_setup,
1662 },
1663 /*
1664 * Cronyx Omega PCI (PLX-chip based)
1665 */
1666 {
1667 .vendor = PCI_VENDOR_ID_PLX,
1668 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1669 .subvendor = PCI_ANY_ID,
1670 .subdevice = PCI_ANY_ID,
1671 .setup = pci_omegapci_setup,
1672 },
1673 /*
1674 * Default "match everything" terminator entry
1675 */
1676 {
1677 .vendor = PCI_ANY_ID,
1678 .device = PCI_ANY_ID,
1679 .subvendor = PCI_ANY_ID,
1680 .subdevice = PCI_ANY_ID,
1681 .setup = pci_default_setup,
1682 }
1683 };
1684
1685 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1686 {
1687 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1688 }
1689
1690 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1691 {
1692 struct pci_serial_quirk *quirk;
1693
1694 for (quirk = pci_serial_quirks; ; quirk++)
1695 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1696 quirk_id_matches(quirk->device, dev->device) &&
1697 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1698 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1699 break;
1700 return quirk;
1701 }
1702
1703 static inline int get_pci_irq(struct pci_dev *dev,
1704 const struct pciserial_board *board)
1705 {
1706 if (board->flags & FL_NOIRQ)
1707 return 0;
1708 else
1709 return dev->irq;
1710 }
1711
1712 /*
1713 * This is the configuration table for all of the PCI serial boards
1714 * which we support. It is directly indexed by the pci_board_num_t enum
1715 * value, which is encoded in the pci_device_id PCI probe table's
1716 * driver_data member.
1717 *
1718 * The makeup of these names are:
1719 * pbn_bn{_bt}_n_baud{_offsetinhex}
1720 *
1721 * bn = PCI BAR number
1722 * bt = Index using PCI BARs
1723 * n = number of serial ports
1724 * baud = baud rate
1725 * offsetinhex = offset for each sequential port (in hex)
1726 *
1727 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1728 *
1729 * Please note: in theory if n = 1, _bt infix should make no difference.
1730 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1731 */
1732 enum pci_board_num_t {
1733 pbn_default = 0,
1734
1735 pbn_b0_1_115200,
1736 pbn_b0_2_115200,
1737 pbn_b0_4_115200,
1738 pbn_b0_5_115200,
1739 pbn_b0_8_115200,
1740
1741 pbn_b0_1_921600,
1742 pbn_b0_2_921600,
1743 pbn_b0_4_921600,
1744
1745 pbn_b0_2_1130000,
1746
1747 pbn_b0_4_1152000,
1748
1749 pbn_b0_2_1843200,
1750 pbn_b0_4_1843200,
1751
1752 pbn_b0_2_1843200_200,
1753 pbn_b0_4_1843200_200,
1754 pbn_b0_8_1843200_200,
1755
1756 pbn_b0_1_4000000,
1757
1758 pbn_b0_bt_1_115200,
1759 pbn_b0_bt_2_115200,
1760 pbn_b0_bt_4_115200,
1761 pbn_b0_bt_8_115200,
1762
1763 pbn_b0_bt_1_460800,
1764 pbn_b0_bt_2_460800,
1765 pbn_b0_bt_4_460800,
1766
1767 pbn_b0_bt_1_921600,
1768 pbn_b0_bt_2_921600,
1769 pbn_b0_bt_4_921600,
1770 pbn_b0_bt_8_921600,
1771
1772 pbn_b1_1_115200,
1773 pbn_b1_2_115200,
1774 pbn_b1_4_115200,
1775 pbn_b1_8_115200,
1776 pbn_b1_16_115200,
1777
1778 pbn_b1_1_921600,
1779 pbn_b1_2_921600,
1780 pbn_b1_4_921600,
1781 pbn_b1_8_921600,
1782
1783 pbn_b1_2_1250000,
1784
1785 pbn_b1_bt_1_115200,
1786 pbn_b1_bt_2_115200,
1787 pbn_b1_bt_4_115200,
1788
1789 pbn_b1_bt_2_921600,
1790
1791 pbn_b1_1_1382400,
1792 pbn_b1_2_1382400,
1793 pbn_b1_4_1382400,
1794 pbn_b1_8_1382400,
1795
1796 pbn_b2_1_115200,
1797 pbn_b2_2_115200,
1798 pbn_b2_4_115200,
1799 pbn_b2_8_115200,
1800
1801 pbn_b2_1_460800,
1802 pbn_b2_4_460800,
1803 pbn_b2_8_460800,
1804 pbn_b2_16_460800,
1805
1806 pbn_b2_1_921600,
1807 pbn_b2_4_921600,
1808 pbn_b2_8_921600,
1809
1810 pbn_b2_8_1152000,
1811
1812 pbn_b2_bt_1_115200,
1813 pbn_b2_bt_2_115200,
1814 pbn_b2_bt_4_115200,
1815
1816 pbn_b2_bt_2_921600,
1817 pbn_b2_bt_4_921600,
1818
1819 pbn_b3_2_115200,
1820 pbn_b3_4_115200,
1821 pbn_b3_8_115200,
1822
1823 pbn_b4_bt_2_921600,
1824 pbn_b4_bt_4_921600,
1825 pbn_b4_bt_8_921600,
1826
1827 /*
1828 * Board-specific versions.
1829 */
1830 pbn_panacom,
1831 pbn_panacom2,
1832 pbn_panacom4,
1833 pbn_exsys_4055,
1834 pbn_plx_romulus,
1835 pbn_oxsemi,
1836 pbn_oxsemi_1_4000000,
1837 pbn_oxsemi_2_4000000,
1838 pbn_oxsemi_4_4000000,
1839 pbn_oxsemi_8_4000000,
1840 pbn_intel_i960,
1841 pbn_sgi_ioc3,
1842 pbn_computone_4,
1843 pbn_computone_6,
1844 pbn_computone_8,
1845 pbn_sbsxrsio,
1846 pbn_exar_XR17C152,
1847 pbn_exar_XR17C154,
1848 pbn_exar_XR17C158,
1849 pbn_exar_ibm_saturn,
1850 pbn_pasemi_1682M,
1851 pbn_ni8430_2,
1852 pbn_ni8430_4,
1853 pbn_ni8430_8,
1854 pbn_ni8430_16,
1855 pbn_ADDIDATA_PCIe_1_3906250,
1856 pbn_ADDIDATA_PCIe_2_3906250,
1857 pbn_ADDIDATA_PCIe_4_3906250,
1858 pbn_ADDIDATA_PCIe_8_3906250,
1859 pbn_ce4100_1_115200,
1860 pbn_omegapci,
1861 pbn_NETMOS9900_2s_115200,
1862 };
1863
1864 /*
1865 * uart_offset - the space between channels
1866 * reg_shift - describes how the UART registers are mapped
1867 * to PCI memory by the card.
1868 * For example IER register on SBS, Inc. PMC-OctPro is located at
1869 * offset 0x10 from the UART base, while UART_IER is defined as 1
1870 * in include/linux/serial_reg.h,
1871 * see first lines of serial_in() and serial_out() in 8250.c
1872 */
1873
1874 static struct pciserial_board pci_boards[] __devinitdata = {
1875 [pbn_default] = {
1876 .flags = FL_BASE0,
1877 .num_ports = 1,
1878 .base_baud = 115200,
1879 .uart_offset = 8,
1880 },
1881 [pbn_b0_1_115200] = {
1882 .flags = FL_BASE0,
1883 .num_ports = 1,
1884 .base_baud = 115200,
1885 .uart_offset = 8,
1886 },
1887 [pbn_b0_2_115200] = {
1888 .flags = FL_BASE0,
1889 .num_ports = 2,
1890 .base_baud = 115200,
1891 .uart_offset = 8,
1892 },
1893 [pbn_b0_4_115200] = {
1894 .flags = FL_BASE0,
1895 .num_ports = 4,
1896 .base_baud = 115200,
1897 .uart_offset = 8,
1898 },
1899 [pbn_b0_5_115200] = {
1900 .flags = FL_BASE0,
1901 .num_ports = 5,
1902 .base_baud = 115200,
1903 .uart_offset = 8,
1904 },
1905 [pbn_b0_8_115200] = {
1906 .flags = FL_BASE0,
1907 .num_ports = 8,
1908 .base_baud = 115200,
1909 .uart_offset = 8,
1910 },
1911 [pbn_b0_1_921600] = {
1912 .flags = FL_BASE0,
1913 .num_ports = 1,
1914 .base_baud = 921600,
1915 .uart_offset = 8,
1916 },
1917 [pbn_b0_2_921600] = {
1918 .flags = FL_BASE0,
1919 .num_ports = 2,
1920 .base_baud = 921600,
1921 .uart_offset = 8,
1922 },
1923 [pbn_b0_4_921600] = {
1924 .flags = FL_BASE0,
1925 .num_ports = 4,
1926 .base_baud = 921600,
1927 .uart_offset = 8,
1928 },
1929
1930 [pbn_b0_2_1130000] = {
1931 .flags = FL_BASE0,
1932 .num_ports = 2,
1933 .base_baud = 1130000,
1934 .uart_offset = 8,
1935 },
1936
1937 [pbn_b0_4_1152000] = {
1938 .flags = FL_BASE0,
1939 .num_ports = 4,
1940 .base_baud = 1152000,
1941 .uart_offset = 8,
1942 },
1943
1944 [pbn_b0_2_1843200] = {
1945 .flags = FL_BASE0,
1946 .num_ports = 2,
1947 .base_baud = 1843200,
1948 .uart_offset = 8,
1949 },
1950 [pbn_b0_4_1843200] = {
1951 .flags = FL_BASE0,
1952 .num_ports = 4,
1953 .base_baud = 1843200,
1954 .uart_offset = 8,
1955 },
1956
1957 [pbn_b0_2_1843200_200] = {
1958 .flags = FL_BASE0,
1959 .num_ports = 2,
1960 .base_baud = 1843200,
1961 .uart_offset = 0x200,
1962 },
1963 [pbn_b0_4_1843200_200] = {
1964 .flags = FL_BASE0,
1965 .num_ports = 4,
1966 .base_baud = 1843200,
1967 .uart_offset = 0x200,
1968 },
1969 [pbn_b0_8_1843200_200] = {
1970 .flags = FL_BASE0,
1971 .num_ports = 8,
1972 .base_baud = 1843200,
1973 .uart_offset = 0x200,
1974 },
1975 [pbn_b0_1_4000000] = {
1976 .flags = FL_BASE0,
1977 .num_ports = 1,
1978 .base_baud = 4000000,
1979 .uart_offset = 8,
1980 },
1981
1982 [pbn_b0_bt_1_115200] = {
1983 .flags = FL_BASE0|FL_BASE_BARS,
1984 .num_ports = 1,
1985 .base_baud = 115200,
1986 .uart_offset = 8,
1987 },
1988 [pbn_b0_bt_2_115200] = {
1989 .flags = FL_BASE0|FL_BASE_BARS,
1990 .num_ports = 2,
1991 .base_baud = 115200,
1992 .uart_offset = 8,
1993 },
1994 [pbn_b0_bt_4_115200] = {
1995 .flags = FL_BASE0|FL_BASE_BARS,
1996 .num_ports = 4,
1997 .base_baud = 115200,
1998 .uart_offset = 8,
1999 },
2000 [pbn_b0_bt_8_115200] = {
2001 .flags = FL_BASE0|FL_BASE_BARS,
2002 .num_ports = 8,
2003 .base_baud = 115200,
2004 .uart_offset = 8,
2005 },
2006
2007 [pbn_b0_bt_1_460800] = {
2008 .flags = FL_BASE0|FL_BASE_BARS,
2009 .num_ports = 1,
2010 .base_baud = 460800,
2011 .uart_offset = 8,
2012 },
2013 [pbn_b0_bt_2_460800] = {
2014 .flags = FL_BASE0|FL_BASE_BARS,
2015 .num_ports = 2,
2016 .base_baud = 460800,
2017 .uart_offset = 8,
2018 },
2019 [pbn_b0_bt_4_460800] = {
2020 .flags = FL_BASE0|FL_BASE_BARS,
2021 .num_ports = 4,
2022 .base_baud = 460800,
2023 .uart_offset = 8,
2024 },
2025
2026 [pbn_b0_bt_1_921600] = {
2027 .flags = FL_BASE0|FL_BASE_BARS,
2028 .num_ports = 1,
2029 .base_baud = 921600,
2030 .uart_offset = 8,
2031 },
2032 [pbn_b0_bt_2_921600] = {
2033 .flags = FL_BASE0|FL_BASE_BARS,
2034 .num_ports = 2,
2035 .base_baud = 921600,
2036 .uart_offset = 8,
2037 },
2038 [pbn_b0_bt_4_921600] = {
2039 .flags = FL_BASE0|FL_BASE_BARS,
2040 .num_ports = 4,
2041 .base_baud = 921600,
2042 .uart_offset = 8,
2043 },
2044 [pbn_b0_bt_8_921600] = {
2045 .flags = FL_BASE0|FL_BASE_BARS,
2046 .num_ports = 8,
2047 .base_baud = 921600,
2048 .uart_offset = 8,
2049 },
2050
2051 [pbn_b1_1_115200] = {
2052 .flags = FL_BASE1,
2053 .num_ports = 1,
2054 .base_baud = 115200,
2055 .uart_offset = 8,
2056 },
2057 [pbn_b1_2_115200] = {
2058 .flags = FL_BASE1,
2059 .num_ports = 2,
2060 .base_baud = 115200,
2061 .uart_offset = 8,
2062 },
2063 [pbn_b1_4_115200] = {
2064 .flags = FL_BASE1,
2065 .num_ports = 4,
2066 .base_baud = 115200,
2067 .uart_offset = 8,
2068 },
2069 [pbn_b1_8_115200] = {
2070 .flags = FL_BASE1,
2071 .num_ports = 8,
2072 .base_baud = 115200,
2073 .uart_offset = 8,
2074 },
2075 [pbn_b1_16_115200] = {
2076 .flags = FL_BASE1,
2077 .num_ports = 16,
2078 .base_baud = 115200,
2079 .uart_offset = 8,
2080 },
2081
2082 [pbn_b1_1_921600] = {
2083 .flags = FL_BASE1,
2084 .num_ports = 1,
2085 .base_baud = 921600,
2086 .uart_offset = 8,
2087 },
2088 [pbn_b1_2_921600] = {
2089 .flags = FL_BASE1,
2090 .num_ports = 2,
2091 .base_baud = 921600,
2092 .uart_offset = 8,
2093 },
2094 [pbn_b1_4_921600] = {
2095 .flags = FL_BASE1,
2096 .num_ports = 4,
2097 .base_baud = 921600,
2098 .uart_offset = 8,
2099 },
2100 [pbn_b1_8_921600] = {
2101 .flags = FL_BASE1,
2102 .num_ports = 8,
2103 .base_baud = 921600,
2104 .uart_offset = 8,
2105 },
2106 [pbn_b1_2_1250000] = {
2107 .flags = FL_BASE1,
2108 .num_ports = 2,
2109 .base_baud = 1250000,
2110 .uart_offset = 8,
2111 },
2112
2113 [pbn_b1_bt_1_115200] = {
2114 .flags = FL_BASE1|FL_BASE_BARS,
2115 .num_ports = 1,
2116 .base_baud = 115200,
2117 .uart_offset = 8,
2118 },
2119 [pbn_b1_bt_2_115200] = {
2120 .flags = FL_BASE1|FL_BASE_BARS,
2121 .num_ports = 2,
2122 .base_baud = 115200,
2123 .uart_offset = 8,
2124 },
2125 [pbn_b1_bt_4_115200] = {
2126 .flags = FL_BASE1|FL_BASE_BARS,
2127 .num_ports = 4,
2128 .base_baud = 115200,
2129 .uart_offset = 8,
2130 },
2131
2132 [pbn_b1_bt_2_921600] = {
2133 .flags = FL_BASE1|FL_BASE_BARS,
2134 .num_ports = 2,
2135 .base_baud = 921600,
2136 .uart_offset = 8,
2137 },
2138
2139 [pbn_b1_1_1382400] = {
2140 .flags = FL_BASE1,
2141 .num_ports = 1,
2142 .base_baud = 1382400,
2143 .uart_offset = 8,
2144 },
2145 [pbn_b1_2_1382400] = {
2146 .flags = FL_BASE1,
2147 .num_ports = 2,
2148 .base_baud = 1382400,
2149 .uart_offset = 8,
2150 },
2151 [pbn_b1_4_1382400] = {
2152 .flags = FL_BASE1,
2153 .num_ports = 4,
2154 .base_baud = 1382400,
2155 .uart_offset = 8,
2156 },
2157 [pbn_b1_8_1382400] = {
2158 .flags = FL_BASE1,
2159 .num_ports = 8,
2160 .base_baud = 1382400,
2161 .uart_offset = 8,
2162 },
2163
2164 [pbn_b2_1_115200] = {
2165 .flags = FL_BASE2,
2166 .num_ports = 1,
2167 .base_baud = 115200,
2168 .uart_offset = 8,
2169 },
2170 [pbn_b2_2_115200] = {
2171 .flags = FL_BASE2,
2172 .num_ports = 2,
2173 .base_baud = 115200,
2174 .uart_offset = 8,
2175 },
2176 [pbn_b2_4_115200] = {
2177 .flags = FL_BASE2,
2178 .num_ports = 4,
2179 .base_baud = 115200,
2180 .uart_offset = 8,
2181 },
2182 [pbn_b2_8_115200] = {
2183 .flags = FL_BASE2,
2184 .num_ports = 8,
2185 .base_baud = 115200,
2186 .uart_offset = 8,
2187 },
2188
2189 [pbn_b2_1_460800] = {
2190 .flags = FL_BASE2,
2191 .num_ports = 1,
2192 .base_baud = 460800,
2193 .uart_offset = 8,
2194 },
2195 [pbn_b2_4_460800] = {
2196 .flags = FL_BASE2,
2197 .num_ports = 4,
2198 .base_baud = 460800,
2199 .uart_offset = 8,
2200 },
2201 [pbn_b2_8_460800] = {
2202 .flags = FL_BASE2,
2203 .num_ports = 8,
2204 .base_baud = 460800,
2205 .uart_offset = 8,
2206 },
2207 [pbn_b2_16_460800] = {
2208 .flags = FL_BASE2,
2209 .num_ports = 16,
2210 .base_baud = 460800,
2211 .uart_offset = 8,
2212 },
2213
2214 [pbn_b2_1_921600] = {
2215 .flags = FL_BASE2,
2216 .num_ports = 1,
2217 .base_baud = 921600,
2218 .uart_offset = 8,
2219 },
2220 [pbn_b2_4_921600] = {
2221 .flags = FL_BASE2,
2222 .num_ports = 4,
2223 .base_baud = 921600,
2224 .uart_offset = 8,
2225 },
2226 [pbn_b2_8_921600] = {
2227 .flags = FL_BASE2,
2228 .num_ports = 8,
2229 .base_baud = 921600,
2230 .uart_offset = 8,
2231 },
2232
2233 [pbn_b2_8_1152000] = {
2234 .flags = FL_BASE2,
2235 .num_ports = 8,
2236 .base_baud = 1152000,
2237 .uart_offset = 8,
2238 },
2239
2240 [pbn_b2_bt_1_115200] = {
2241 .flags = FL_BASE2|FL_BASE_BARS,
2242 .num_ports = 1,
2243 .base_baud = 115200,
2244 .uart_offset = 8,
2245 },
2246 [pbn_b2_bt_2_115200] = {
2247 .flags = FL_BASE2|FL_BASE_BARS,
2248 .num_ports = 2,
2249 .base_baud = 115200,
2250 .uart_offset = 8,
2251 },
2252 [pbn_b2_bt_4_115200] = {
2253 .flags = FL_BASE2|FL_BASE_BARS,
2254 .num_ports = 4,
2255 .base_baud = 115200,
2256 .uart_offset = 8,
2257 },
2258
2259 [pbn_b2_bt_2_921600] = {
2260 .flags = FL_BASE2|FL_BASE_BARS,
2261 .num_ports = 2,
2262 .base_baud = 921600,
2263 .uart_offset = 8,
2264 },
2265 [pbn_b2_bt_4_921600] = {
2266 .flags = FL_BASE2|FL_BASE_BARS,
2267 .num_ports = 4,
2268 .base_baud = 921600,
2269 .uart_offset = 8,
2270 },
2271
2272 [pbn_b3_2_115200] = {
2273 .flags = FL_BASE3,
2274 .num_ports = 2,
2275 .base_baud = 115200,
2276 .uart_offset = 8,
2277 },
2278 [pbn_b3_4_115200] = {
2279 .flags = FL_BASE3,
2280 .num_ports = 4,
2281 .base_baud = 115200,
2282 .uart_offset = 8,
2283 },
2284 [pbn_b3_8_115200] = {
2285 .flags = FL_BASE3,
2286 .num_ports = 8,
2287 .base_baud = 115200,
2288 .uart_offset = 8,
2289 },
2290
2291 [pbn_b4_bt_2_921600] = {
2292 .flags = FL_BASE4,
2293 .num_ports = 2,
2294 .base_baud = 921600,
2295 .uart_offset = 8,
2296 },
2297 [pbn_b4_bt_4_921600] = {
2298 .flags = FL_BASE4,
2299 .num_ports = 4,
2300 .base_baud = 921600,
2301 .uart_offset = 8,
2302 },
2303 [pbn_b4_bt_8_921600] = {
2304 .flags = FL_BASE4,
2305 .num_ports = 8,
2306 .base_baud = 921600,
2307 .uart_offset = 8,
2308 },
2309
2310 /*
2311 * Entries following this are board-specific.
2312 */
2313
2314 /*
2315 * Panacom - IOMEM
2316 */
2317 [pbn_panacom] = {
2318 .flags = FL_BASE2,
2319 .num_ports = 2,
2320 .base_baud = 921600,
2321 .uart_offset = 0x400,
2322 .reg_shift = 7,
2323 },
2324 [pbn_panacom2] = {
2325 .flags = FL_BASE2|FL_BASE_BARS,
2326 .num_ports = 2,
2327 .base_baud = 921600,
2328 .uart_offset = 0x400,
2329 .reg_shift = 7,
2330 },
2331 [pbn_panacom4] = {
2332 .flags = FL_BASE2|FL_BASE_BARS,
2333 .num_ports = 4,
2334 .base_baud = 921600,
2335 .uart_offset = 0x400,
2336 .reg_shift = 7,
2337 },
2338
2339 [pbn_exsys_4055] = {
2340 .flags = FL_BASE2,
2341 .num_ports = 4,
2342 .base_baud = 115200,
2343 .uart_offset = 8,
2344 },
2345
2346 /* I think this entry is broken - the first_offset looks wrong --rmk */
2347 [pbn_plx_romulus] = {
2348 .flags = FL_BASE2,
2349 .num_ports = 4,
2350 .base_baud = 921600,
2351 .uart_offset = 8 << 2,
2352 .reg_shift = 2,
2353 .first_offset = 0x03,
2354 },
2355
2356 /*
2357 * This board uses the size of PCI Base region 0 to
2358 * signal now many ports are available
2359 */
2360 [pbn_oxsemi] = {
2361 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2362 .num_ports = 32,
2363 .base_baud = 115200,
2364 .uart_offset = 8,
2365 },
2366 [pbn_oxsemi_1_4000000] = {
2367 .flags = FL_BASE0,
2368 .num_ports = 1,
2369 .base_baud = 4000000,
2370 .uart_offset = 0x200,
2371 .first_offset = 0x1000,
2372 },
2373 [pbn_oxsemi_2_4000000] = {
2374 .flags = FL_BASE0,
2375 .num_ports = 2,
2376 .base_baud = 4000000,
2377 .uart_offset = 0x200,
2378 .first_offset = 0x1000,
2379 },
2380 [pbn_oxsemi_4_4000000] = {
2381 .flags = FL_BASE0,
2382 .num_ports = 4,
2383 .base_baud = 4000000,
2384 .uart_offset = 0x200,
2385 .first_offset = 0x1000,
2386 },
2387 [pbn_oxsemi_8_4000000] = {
2388 .flags = FL_BASE0,
2389 .num_ports = 8,
2390 .base_baud = 4000000,
2391 .uart_offset = 0x200,
2392 .first_offset = 0x1000,
2393 },
2394
2395
2396 /*
2397 * EKF addition for i960 Boards form EKF with serial port.
2398 * Max 256 ports.
2399 */
2400 [pbn_intel_i960] = {
2401 .flags = FL_BASE0,
2402 .num_ports = 32,
2403 .base_baud = 921600,
2404 .uart_offset = 8 << 2,
2405 .reg_shift = 2,
2406 .first_offset = 0x10000,
2407 },
2408 [pbn_sgi_ioc3] = {
2409 .flags = FL_BASE0|FL_NOIRQ,
2410 .num_ports = 1,
2411 .base_baud = 458333,
2412 .uart_offset = 8,
2413 .reg_shift = 0,
2414 .first_offset = 0x20178,
2415 },
2416
2417 /*
2418 * Computone - uses IOMEM.
2419 */
2420 [pbn_computone_4] = {
2421 .flags = FL_BASE0,
2422 .num_ports = 4,
2423 .base_baud = 921600,
2424 .uart_offset = 0x40,
2425 .reg_shift = 2,
2426 .first_offset = 0x200,
2427 },
2428 [pbn_computone_6] = {
2429 .flags = FL_BASE0,
2430 .num_ports = 6,
2431 .base_baud = 921600,
2432 .uart_offset = 0x40,
2433 .reg_shift = 2,
2434 .first_offset = 0x200,
2435 },
2436 [pbn_computone_8] = {
2437 .flags = FL_BASE0,
2438 .num_ports = 8,
2439 .base_baud = 921600,
2440 .uart_offset = 0x40,
2441 .reg_shift = 2,
2442 .first_offset = 0x200,
2443 },
2444 [pbn_sbsxrsio] = {
2445 .flags = FL_BASE0,
2446 .num_ports = 8,
2447 .base_baud = 460800,
2448 .uart_offset = 256,
2449 .reg_shift = 4,
2450 },
2451 /*
2452 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2453 * Only basic 16550A support.
2454 * XR17C15[24] are not tested, but they should work.
2455 */
2456 [pbn_exar_XR17C152] = {
2457 .flags = FL_BASE0,
2458 .num_ports = 2,
2459 .base_baud = 921600,
2460 .uart_offset = 0x200,
2461 },
2462 [pbn_exar_XR17C154] = {
2463 .flags = FL_BASE0,
2464 .num_ports = 4,
2465 .base_baud = 921600,
2466 .uart_offset = 0x200,
2467 },
2468 [pbn_exar_XR17C158] = {
2469 .flags = FL_BASE0,
2470 .num_ports = 8,
2471 .base_baud = 921600,
2472 .uart_offset = 0x200,
2473 },
2474 [pbn_exar_ibm_saturn] = {
2475 .flags = FL_BASE0,
2476 .num_ports = 1,
2477 .base_baud = 921600,
2478 .uart_offset = 0x200,
2479 },
2480
2481 /*
2482 * PA Semi PWRficient PA6T-1682M on-chip UART
2483 */
2484 [pbn_pasemi_1682M] = {
2485 .flags = FL_BASE0,
2486 .num_ports = 1,
2487 .base_baud = 8333333,
2488 },
2489 /*
2490 * National Instruments 843x
2491 */
2492 [pbn_ni8430_16] = {
2493 .flags = FL_BASE0,
2494 .num_ports = 16,
2495 .base_baud = 3686400,
2496 .uart_offset = 0x10,
2497 .first_offset = 0x800,
2498 },
2499 [pbn_ni8430_8] = {
2500 .flags = FL_BASE0,
2501 .num_ports = 8,
2502 .base_baud = 3686400,
2503 .uart_offset = 0x10,
2504 .first_offset = 0x800,
2505 },
2506 [pbn_ni8430_4] = {
2507 .flags = FL_BASE0,
2508 .num_ports = 4,
2509 .base_baud = 3686400,
2510 .uart_offset = 0x10,
2511 .first_offset = 0x800,
2512 },
2513 [pbn_ni8430_2] = {
2514 .flags = FL_BASE0,
2515 .num_ports = 2,
2516 .base_baud = 3686400,
2517 .uart_offset = 0x10,
2518 .first_offset = 0x800,
2519 },
2520 /*
2521 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2522 */
2523 [pbn_ADDIDATA_PCIe_1_3906250] = {
2524 .flags = FL_BASE0,
2525 .num_ports = 1,
2526 .base_baud = 3906250,
2527 .uart_offset = 0x200,
2528 .first_offset = 0x1000,
2529 },
2530 [pbn_ADDIDATA_PCIe_2_3906250] = {
2531 .flags = FL_BASE0,
2532 .num_ports = 2,
2533 .base_baud = 3906250,
2534 .uart_offset = 0x200,
2535 .first_offset = 0x1000,
2536 },
2537 [pbn_ADDIDATA_PCIe_4_3906250] = {
2538 .flags = FL_BASE0,
2539 .num_ports = 4,
2540 .base_baud = 3906250,
2541 .uart_offset = 0x200,
2542 .first_offset = 0x1000,
2543 },
2544 [pbn_ADDIDATA_PCIe_8_3906250] = {
2545 .flags = FL_BASE0,
2546 .num_ports = 8,
2547 .base_baud = 3906250,
2548 .uart_offset = 0x200,
2549 .first_offset = 0x1000,
2550 },
2551 [pbn_ce4100_1_115200] = {
2552 .flags = FL_BASE0,
2553 .num_ports = 1,
2554 .base_baud = 921600,
2555 .reg_shift = 2,
2556 },
2557 [pbn_omegapci] = {
2558 .flags = FL_BASE0,
2559 .num_ports = 8,
2560 .base_baud = 115200,
2561 .uart_offset = 0x200,
2562 },
2563 [pbn_NETMOS9900_2s_115200] = {
2564 .flags = FL_BASE0,
2565 .num_ports = 2,
2566 .base_baud = 115200,
2567 },
2568 };
2569
2570 static const struct pci_device_id softmodem_blacklist[] = {
2571 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2572 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2573 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2574 };
2575
2576 /*
2577 * Given a complete unknown PCI device, try to use some heuristics to
2578 * guess what the configuration might be, based on the pitiful PCI
2579 * serial specs. Returns 0 on success, 1 on failure.
2580 */
2581 static int __devinit
2582 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2583 {
2584 const struct pci_device_id *blacklist;
2585 int num_iomem, num_port, first_port = -1, i;
2586
2587 /*
2588 * If it is not a communications device or the programming
2589 * interface is greater than 6, give up.
2590 *
2591 * (Should we try to make guesses for multiport serial devices
2592 * later?)
2593 */
2594 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2595 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2596 (dev->class & 0xff) > 6)
2597 return -ENODEV;
2598
2599 /*
2600 * Do not access blacklisted devices that are known not to
2601 * feature serial ports.
2602 */
2603 for (blacklist = softmodem_blacklist;
2604 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2605 blacklist++) {
2606 if (dev->vendor == blacklist->vendor &&
2607 dev->device == blacklist->device)
2608 return -ENODEV;
2609 }
2610
2611 num_iomem = num_port = 0;
2612 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2613 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2614 num_port++;
2615 if (first_port == -1)
2616 first_port = i;
2617 }
2618 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2619 num_iomem++;
2620 }
2621
2622 /*
2623 * If there is 1 or 0 iomem regions, and exactly one port,
2624 * use it. We guess the number of ports based on the IO
2625 * region size.
2626 */
2627 if (num_iomem <= 1 && num_port == 1) {
2628 board->flags = first_port;
2629 board->num_ports = pci_resource_len(dev, first_port) / 8;
2630 return 0;
2631 }
2632
2633 /*
2634 * Now guess if we've got a board which indexes by BARs.
2635 * Each IO BAR should be 8 bytes, and they should follow
2636 * consecutively.
2637 */
2638 first_port = -1;
2639 num_port = 0;
2640 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2641 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2642 pci_resource_len(dev, i) == 8 &&
2643 (first_port == -1 || (first_port + num_port) == i)) {
2644 num_port++;
2645 if (first_port == -1)
2646 first_port = i;
2647 }
2648 }
2649
2650 if (num_port > 1) {
2651 board->flags = first_port | FL_BASE_BARS;
2652 board->num_ports = num_port;
2653 return 0;
2654 }
2655
2656 return -ENODEV;
2657 }
2658
2659 static inline int
2660 serial_pci_matches(const struct pciserial_board *board,
2661 const struct pciserial_board *guessed)
2662 {
2663 return
2664 board->num_ports == guessed->num_ports &&
2665 board->base_baud == guessed->base_baud &&
2666 board->uart_offset == guessed->uart_offset &&
2667 board->reg_shift == guessed->reg_shift &&
2668 board->first_offset == guessed->first_offset;
2669 }
2670
2671 struct serial_private *
2672 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2673 {
2674 struct uart_port serial_port;
2675 struct serial_private *priv;
2676 struct pci_serial_quirk *quirk;
2677 int rc, nr_ports, i;
2678
2679 nr_ports = board->num_ports;
2680
2681 /*
2682 * Find an init and setup quirks.
2683 */
2684 quirk = find_quirk(dev);
2685
2686 /*
2687 * Run the new-style initialization function.
2688 * The initialization function returns:
2689 * <0 - error
2690 * 0 - use board->num_ports
2691 * >0 - number of ports
2692 */
2693 if (quirk->init) {
2694 rc = quirk->init(dev);
2695 if (rc < 0) {
2696 priv = ERR_PTR(rc);
2697 goto err_out;
2698 }
2699 if (rc)
2700 nr_ports = rc;
2701 }
2702
2703 priv = kzalloc(sizeof(struct serial_private) +
2704 sizeof(unsigned int) * nr_ports,
2705 GFP_KERNEL);
2706 if (!priv) {
2707 priv = ERR_PTR(-ENOMEM);
2708 goto err_deinit;
2709 }
2710
2711 priv->dev = dev;
2712 priv->quirk = quirk;
2713
2714 memset(&serial_port, 0, sizeof(struct uart_port));
2715 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2716 serial_port.uartclk = board->base_baud * 16;
2717 serial_port.irq = get_pci_irq(dev, board);
2718 serial_port.dev = &dev->dev;
2719
2720 for (i = 0; i < nr_ports; i++) {
2721 if (quirk->setup(priv, board, &serial_port, i))
2722 break;
2723
2724 #ifdef SERIAL_DEBUG_PCI
2725 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2726 serial_port.iobase, serial_port.irq, serial_port.iotype);
2727 #endif
2728
2729 priv->line[i] = serial8250_register_port(&serial_port);
2730 if (priv->line[i] < 0) {
2731 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2732 break;
2733 }
2734 }
2735 priv->nr = i;
2736 return priv;
2737
2738 err_deinit:
2739 if (quirk->exit)
2740 quirk->exit(dev);
2741 err_out:
2742 return priv;
2743 }
2744 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2745
2746 void pciserial_remove_ports(struct serial_private *priv)
2747 {
2748 struct pci_serial_quirk *quirk;
2749 int i;
2750
2751 for (i = 0; i < priv->nr; i++)
2752 serial8250_unregister_port(priv->line[i]);
2753
2754 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2755 if (priv->remapped_bar[i])
2756 iounmap(priv->remapped_bar[i]);
2757 priv->remapped_bar[i] = NULL;
2758 }
2759
2760 /*
2761 * Find the exit quirks.
2762 */
2763 quirk = find_quirk(priv->dev);
2764 if (quirk->exit)
2765 quirk->exit(priv->dev);
2766
2767 kfree(priv);
2768 }
2769 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2770
2771 void pciserial_suspend_ports(struct serial_private *priv)
2772 {
2773 int i;
2774
2775 for (i = 0; i < priv->nr; i++)
2776 if (priv->line[i] >= 0)
2777 serial8250_suspend_port(priv->line[i]);
2778 }
2779 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2780
2781 void pciserial_resume_ports(struct serial_private *priv)
2782 {
2783 int i;
2784
2785 /*
2786 * Ensure that the board is correctly configured.
2787 */
2788 if (priv->quirk->init)
2789 priv->quirk->init(priv->dev);
2790
2791 for (i = 0; i < priv->nr; i++)
2792 if (priv->line[i] >= 0)
2793 serial8250_resume_port(priv->line[i]);
2794 }
2795 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2796
2797 /*
2798 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2799 * to the arrangement of serial ports on a PCI card.
2800 */
2801 static int __devinit
2802 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2803 {
2804 struct pci_serial_quirk *quirk;
2805 struct serial_private *priv;
2806 const struct pciserial_board *board;
2807 struct pciserial_board tmp;
2808 int rc;
2809
2810 quirk = find_quirk(dev);
2811 if (quirk->probe) {
2812 rc = quirk->probe(dev);
2813 if (rc)
2814 return rc;
2815 }
2816
2817 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2818 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2819 ent->driver_data);
2820 return -EINVAL;
2821 }
2822
2823 board = &pci_boards[ent->driver_data];
2824
2825 rc = pci_enable_device(dev);
2826 pci_save_state(dev);
2827 if (rc)
2828 return rc;
2829
2830 if (ent->driver_data == pbn_default) {
2831 /*
2832 * Use a copy of the pci_board entry for this;
2833 * avoid changing entries in the table.
2834 */
2835 memcpy(&tmp, board, sizeof(struct pciserial_board));
2836 board = &tmp;
2837
2838 /*
2839 * We matched one of our class entries. Try to
2840 * determine the parameters of this board.
2841 */
2842 rc = serial_pci_guess_board(dev, &tmp);
2843 if (rc)
2844 goto disable;
2845 } else {
2846 /*
2847 * We matched an explicit entry. If we are able to
2848 * detect this boards settings with our heuristic,
2849 * then we no longer need this entry.
2850 */
2851 memcpy(&tmp, &pci_boards[pbn_default],
2852 sizeof(struct pciserial_board));
2853 rc = serial_pci_guess_board(dev, &tmp);
2854 if (rc == 0 && serial_pci_matches(board, &tmp))
2855 moan_device("Redundant entry in serial pci_table.",
2856 dev);
2857 }
2858
2859 priv = pciserial_init_ports(dev, board);
2860 if (!IS_ERR(priv)) {
2861 pci_set_drvdata(dev, priv);
2862 return 0;
2863 }
2864
2865 rc = PTR_ERR(priv);
2866
2867 disable:
2868 pci_disable_device(dev);
2869 return rc;
2870 }
2871
2872 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2873 {
2874 struct serial_private *priv = pci_get_drvdata(dev);
2875
2876 pci_set_drvdata(dev, NULL);
2877
2878 pciserial_remove_ports(priv);
2879
2880 pci_disable_device(dev);
2881 }
2882
2883 #ifdef CONFIG_PM
2884 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2885 {
2886 struct serial_private *priv = pci_get_drvdata(dev);
2887
2888 if (priv)
2889 pciserial_suspend_ports(priv);
2890
2891 pci_save_state(dev);
2892 pci_set_power_state(dev, pci_choose_state(dev, state));
2893 return 0;
2894 }
2895
2896 static int pciserial_resume_one(struct pci_dev *dev)
2897 {
2898 int err;
2899 struct serial_private *priv = pci_get_drvdata(dev);
2900
2901 pci_set_power_state(dev, PCI_D0);
2902 pci_restore_state(dev);
2903
2904 if (priv) {
2905 /*
2906 * The device may have been disabled. Re-enable it.
2907 */
2908 err = pci_enable_device(dev);
2909 /* FIXME: We cannot simply error out here */
2910 if (err)
2911 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2912 pciserial_resume_ports(priv);
2913 }
2914 return 0;
2915 }
2916 #endif
2917
2918 static struct pci_device_id serial_pci_tbl[] = {
2919 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2920 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2921 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2922 pbn_b2_8_921600 },
2923 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2924 PCI_SUBVENDOR_ID_CONNECT_TECH,
2925 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2926 pbn_b1_8_1382400 },
2927 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2928 PCI_SUBVENDOR_ID_CONNECT_TECH,
2929 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2930 pbn_b1_4_1382400 },
2931 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2932 PCI_SUBVENDOR_ID_CONNECT_TECH,
2933 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2934 pbn_b1_2_1382400 },
2935 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2936 PCI_SUBVENDOR_ID_CONNECT_TECH,
2937 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2938 pbn_b1_8_1382400 },
2939 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2940 PCI_SUBVENDOR_ID_CONNECT_TECH,
2941 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2942 pbn_b1_4_1382400 },
2943 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2944 PCI_SUBVENDOR_ID_CONNECT_TECH,
2945 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2946 pbn_b1_2_1382400 },
2947 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2948 PCI_SUBVENDOR_ID_CONNECT_TECH,
2949 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2950 pbn_b1_8_921600 },
2951 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2952 PCI_SUBVENDOR_ID_CONNECT_TECH,
2953 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2954 pbn_b1_8_921600 },
2955 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2956 PCI_SUBVENDOR_ID_CONNECT_TECH,
2957 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2958 pbn_b1_4_921600 },
2959 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2960 PCI_SUBVENDOR_ID_CONNECT_TECH,
2961 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2962 pbn_b1_4_921600 },
2963 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2964 PCI_SUBVENDOR_ID_CONNECT_TECH,
2965 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2966 pbn_b1_2_921600 },
2967 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2968 PCI_SUBVENDOR_ID_CONNECT_TECH,
2969 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2970 pbn_b1_8_921600 },
2971 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2972 PCI_SUBVENDOR_ID_CONNECT_TECH,
2973 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2974 pbn_b1_8_921600 },
2975 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2976 PCI_SUBVENDOR_ID_CONNECT_TECH,
2977 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2978 pbn_b1_4_921600 },
2979 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2980 PCI_SUBVENDOR_ID_CONNECT_TECH,
2981 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2982 pbn_b1_2_1250000 },
2983 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2984 PCI_SUBVENDOR_ID_CONNECT_TECH,
2985 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2986 pbn_b0_2_1843200 },
2987 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2988 PCI_SUBVENDOR_ID_CONNECT_TECH,
2989 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2990 pbn_b0_4_1843200 },
2991 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2992 PCI_VENDOR_ID_AFAVLAB,
2993 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2994 pbn_b0_4_1152000 },
2995 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2996 PCI_SUBVENDOR_ID_CONNECT_TECH,
2997 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2998 pbn_b0_2_1843200_200 },
2999 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3000 PCI_SUBVENDOR_ID_CONNECT_TECH,
3001 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3002 pbn_b0_4_1843200_200 },
3003 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3004 PCI_SUBVENDOR_ID_CONNECT_TECH,
3005 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3006 pbn_b0_8_1843200_200 },
3007 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3008 PCI_SUBVENDOR_ID_CONNECT_TECH,
3009 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3010 pbn_b0_2_1843200_200 },
3011 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3012 PCI_SUBVENDOR_ID_CONNECT_TECH,
3013 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3014 pbn_b0_4_1843200_200 },
3015 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3016 PCI_SUBVENDOR_ID_CONNECT_TECH,
3017 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3018 pbn_b0_8_1843200_200 },
3019 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3020 PCI_SUBVENDOR_ID_CONNECT_TECH,
3021 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3022 pbn_b0_2_1843200_200 },
3023 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3024 PCI_SUBVENDOR_ID_CONNECT_TECH,
3025 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3026 pbn_b0_4_1843200_200 },
3027 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3028 PCI_SUBVENDOR_ID_CONNECT_TECH,
3029 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3030 pbn_b0_8_1843200_200 },
3031 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3032 PCI_SUBVENDOR_ID_CONNECT_TECH,
3033 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3034 pbn_b0_2_1843200_200 },
3035 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3036 PCI_SUBVENDOR_ID_CONNECT_TECH,
3037 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3038 pbn_b0_4_1843200_200 },
3039 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3040 PCI_SUBVENDOR_ID_CONNECT_TECH,
3041 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3042 pbn_b0_8_1843200_200 },
3043 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3044 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3045 0, 0, pbn_exar_ibm_saturn },
3046
3047 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3049 pbn_b2_bt_1_115200 },
3050 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3052 pbn_b2_bt_2_115200 },
3053 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3055 pbn_b2_bt_4_115200 },
3056 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3058 pbn_b2_bt_2_115200 },
3059 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3061 pbn_b2_bt_4_115200 },
3062 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3064 pbn_b2_8_115200 },
3065 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3067 pbn_b2_8_460800 },
3068 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3070 pbn_b2_8_115200 },
3071
3072 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3074 pbn_b2_bt_2_115200 },
3075 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3077 pbn_b2_bt_2_921600 },
3078 /*
3079 * VScom SPCOM800, from sl@s.pl
3080 */
3081 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3083 pbn_b2_8_921600 },
3084 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3086 pbn_b2_4_921600 },
3087 /* Unknown card - subdevice 0x1584 */
3088 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3089 PCI_VENDOR_ID_PLX,
3090 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3091 pbn_b0_4_115200 },
3092 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3093 PCI_SUBVENDOR_ID_KEYSPAN,
3094 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3095 pbn_panacom },
3096 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3098 pbn_panacom4 },
3099 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3101 pbn_panacom2 },
3102 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3103 PCI_VENDOR_ID_ESDGMBH,
3104 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3105 pbn_b2_4_115200 },
3106 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3107 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3108 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3109 pbn_b2_4_460800 },
3110 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3111 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3112 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3113 pbn_b2_8_460800 },
3114 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3115 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3116 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3117 pbn_b2_16_460800 },
3118 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3119 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3120 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3121 pbn_b2_16_460800 },
3122 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3123 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3124 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3125 pbn_b2_4_460800 },
3126 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3127 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3128 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3129 pbn_b2_8_460800 },
3130 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3131 PCI_SUBVENDOR_ID_EXSYS,
3132 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3133 pbn_exsys_4055 },
3134 /*
3135 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3136 * (Exoray@isys.ca)
3137 */
3138 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3139 0x10b5, 0x106a, 0, 0,
3140 pbn_plx_romulus },
3141 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3143 pbn_b1_4_115200 },
3144 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3146 pbn_b1_2_115200 },
3147 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149 pbn_b1_8_115200 },
3150 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152 pbn_b1_8_115200 },
3153 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3154 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3155 0, 0,
3156 pbn_b0_4_921600 },
3157 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3158 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3159 0, 0,
3160 pbn_b0_4_1152000 },
3161 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163 pbn_b0_bt_2_921600 },
3164
3165 /*
3166 * The below card is a little controversial since it is the
3167 * subject of a PCI vendor/device ID clash. (See
3168 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3169 * For now just used the hex ID 0x950a.
3170 */
3171 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3172 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3173 pbn_b0_2_115200 },
3174 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176 pbn_b0_2_1130000 },
3177 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3178 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3179 pbn_b0_1_921600 },
3180 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3182 pbn_b0_4_115200 },
3183 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3185 pbn_b0_bt_2_921600 },
3186 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3187 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3188 pbn_b2_8_1152000 },
3189
3190 /*
3191 * Oxford Semiconductor Inc. Tornado PCI express device range.
3192 */
3193 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3195 pbn_b0_1_4000000 },
3196 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3198 pbn_b0_1_4000000 },
3199 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3201 pbn_oxsemi_1_4000000 },
3202 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3204 pbn_oxsemi_1_4000000 },
3205 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3207 pbn_b0_1_4000000 },
3208 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210 pbn_b0_1_4000000 },
3211 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213 pbn_oxsemi_1_4000000 },
3214 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216 pbn_oxsemi_1_4000000 },
3217 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3219 pbn_b0_1_4000000 },
3220 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3222 pbn_b0_1_4000000 },
3223 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3225 pbn_b0_1_4000000 },
3226 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228 pbn_b0_1_4000000 },
3229 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3231 pbn_oxsemi_2_4000000 },
3232 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3234 pbn_oxsemi_2_4000000 },
3235 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3237 pbn_oxsemi_4_4000000 },
3238 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240 pbn_oxsemi_4_4000000 },
3241 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3243 pbn_oxsemi_8_4000000 },
3244 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3246 pbn_oxsemi_8_4000000 },
3247 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3249 pbn_oxsemi_1_4000000 },
3250 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3252 pbn_oxsemi_1_4000000 },
3253 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3255 pbn_oxsemi_1_4000000 },
3256 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3258 pbn_oxsemi_1_4000000 },
3259 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3261 pbn_oxsemi_1_4000000 },
3262 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3264 pbn_oxsemi_1_4000000 },
3265 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3267 pbn_oxsemi_1_4000000 },
3268 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3270 pbn_oxsemi_1_4000000 },
3271 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3273 pbn_oxsemi_1_4000000 },
3274 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3276 pbn_oxsemi_1_4000000 },
3277 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3279 pbn_oxsemi_1_4000000 },
3280 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3282 pbn_oxsemi_1_4000000 },
3283 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3285 pbn_oxsemi_1_4000000 },
3286 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3288 pbn_oxsemi_1_4000000 },
3289 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3291 pbn_oxsemi_1_4000000 },
3292 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3294 pbn_oxsemi_1_4000000 },
3295 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3297 pbn_oxsemi_1_4000000 },
3298 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3300 pbn_oxsemi_1_4000000 },
3301 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3303 pbn_oxsemi_1_4000000 },
3304 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3306 pbn_oxsemi_1_4000000 },
3307 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3309 pbn_oxsemi_1_4000000 },
3310 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3312 pbn_oxsemi_1_4000000 },
3313 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3315 pbn_oxsemi_1_4000000 },
3316 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3318 pbn_oxsemi_1_4000000 },
3319 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3321 pbn_oxsemi_1_4000000 },
3322 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3324 pbn_oxsemi_1_4000000 },
3325 /*
3326 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3327 */
3328 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3329 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3330 pbn_oxsemi_1_4000000 },
3331 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3332 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3333 pbn_oxsemi_2_4000000 },
3334 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3335 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3336 pbn_oxsemi_4_4000000 },
3337 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3338 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3339 pbn_oxsemi_8_4000000 },
3340
3341 /*
3342 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3343 */
3344 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3345 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3346 pbn_oxsemi_2_4000000 },
3347
3348 /*
3349 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3350 * from skokodyn@yahoo.com
3351 */
3352 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3353 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3354 pbn_sbsxrsio },
3355 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3356 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3357 pbn_sbsxrsio },
3358 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3359 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3360 pbn_sbsxrsio },
3361 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3362 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3363 pbn_sbsxrsio },
3364
3365 /*
3366 * Digitan DS560-558, from jimd@esoft.com
3367 */
3368 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370 pbn_b1_1_115200 },
3371
3372 /*
3373 * Titan Electronic cards
3374 * The 400L and 800L have a custom setup quirk.
3375 */
3376 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3378 pbn_b0_1_921600 },
3379 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3381 pbn_b0_2_921600 },
3382 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384 pbn_b0_4_921600 },
3385 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387 pbn_b0_4_921600 },
3388 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3390 pbn_b1_1_921600 },
3391 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3393 pbn_b1_bt_2_921600 },
3394 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3396 pbn_b0_bt_4_921600 },
3397 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3399 pbn_b0_bt_8_921600 },
3400 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3402 pbn_b4_bt_2_921600 },
3403 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405 pbn_b4_bt_4_921600 },
3406 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3408 pbn_b4_bt_8_921600 },
3409 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3411 pbn_b0_4_921600 },
3412 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3414 pbn_b0_4_921600 },
3415 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3417 pbn_b0_4_921600 },
3418 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420 pbn_oxsemi_1_4000000 },
3421 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423 pbn_oxsemi_2_4000000 },
3424 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3426 pbn_oxsemi_4_4000000 },
3427 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3429 pbn_oxsemi_8_4000000 },
3430 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3432 pbn_oxsemi_2_4000000 },
3433 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435 pbn_oxsemi_2_4000000 },
3436 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438 pbn_b0_4_921600 },
3439 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3441 pbn_b0_4_921600 },
3442 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3444 pbn_b0_4_921600 },
3445 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3447 pbn_b0_4_921600 },
3448
3449 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3451 pbn_b2_1_460800 },
3452 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454 pbn_b2_1_460800 },
3455 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3457 pbn_b2_1_460800 },
3458 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460 pbn_b2_bt_2_921600 },
3461 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3463 pbn_b2_bt_2_921600 },
3464 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3466 pbn_b2_bt_2_921600 },
3467 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3469 pbn_b2_bt_4_921600 },
3470 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472 pbn_b2_bt_4_921600 },
3473 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475 pbn_b2_bt_4_921600 },
3476 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478 pbn_b0_1_921600 },
3479 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481 pbn_b0_1_921600 },
3482 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3484 pbn_b0_1_921600 },
3485 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487 pbn_b0_bt_2_921600 },
3488 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490 pbn_b0_bt_2_921600 },
3491 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493 pbn_b0_bt_2_921600 },
3494 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3496 pbn_b0_bt_4_921600 },
3497 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3499 pbn_b0_bt_4_921600 },
3500 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3502 pbn_b0_bt_4_921600 },
3503 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3505 pbn_b0_bt_8_921600 },
3506 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3508 pbn_b0_bt_8_921600 },
3509 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3511 pbn_b0_bt_8_921600 },
3512
3513 /*
3514 * Computone devices submitted by Doug McNash dmcnash@computone.com
3515 */
3516 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3517 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3518 0, 0, pbn_computone_4 },
3519 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3520 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3521 0, 0, pbn_computone_8 },
3522 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3523 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3524 0, 0, pbn_computone_6 },
3525
3526 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3528 pbn_oxsemi },
3529 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3530 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3531 pbn_b0_bt_1_921600 },
3532
3533 /*
3534 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3535 */
3536 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3538 pbn_b0_bt_8_115200 },
3539 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3541 pbn_b0_bt_8_115200 },
3542
3543 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3545 pbn_b0_bt_2_115200 },
3546 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548 pbn_b0_bt_2_115200 },
3549 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551 pbn_b0_bt_2_115200 },
3552 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554 pbn_b0_bt_2_115200 },
3555 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557 pbn_b0_bt_2_115200 },
3558 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560 pbn_b0_bt_4_460800 },
3561 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3563 pbn_b0_bt_4_460800 },
3564 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3566 pbn_b0_bt_2_460800 },
3567 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3569 pbn_b0_bt_2_460800 },
3570 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3572 pbn_b0_bt_2_460800 },
3573 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3575 pbn_b0_bt_1_115200 },
3576 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3578 pbn_b0_bt_1_460800 },
3579
3580 /*
3581 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3582 * Cards are identified by their subsystem vendor IDs, which
3583 * (in hex) match the model number.
3584 *
3585 * Note that JC140x are RS422/485 cards which require ox950
3586 * ACR = 0x10, and as such are not currently fully supported.
3587 */
3588 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3589 0x1204, 0x0004, 0, 0,
3590 pbn_b0_4_921600 },
3591 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3592 0x1208, 0x0004, 0, 0,
3593 pbn_b0_4_921600 },
3594 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3595 0x1402, 0x0002, 0, 0,
3596 pbn_b0_2_921600 }, */
3597 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3598 0x1404, 0x0004, 0, 0,
3599 pbn_b0_4_921600 }, */
3600 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3601 0x1208, 0x0004, 0, 0,
3602 pbn_b0_4_921600 },
3603
3604 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3605 0x1204, 0x0004, 0, 0,
3606 pbn_b0_4_921600 },
3607 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3608 0x1208, 0x0004, 0, 0,
3609 pbn_b0_4_921600 },
3610 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3611 0x1208, 0x0004, 0, 0,
3612 pbn_b0_4_921600 },
3613 /*
3614 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3615 */
3616 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3618 pbn_b1_1_1382400 },
3619
3620 /*
3621 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3622 */
3623 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3625 pbn_b1_1_1382400 },
3626
3627 /*
3628 * RAStel 2 port modem, gerg@moreton.com.au
3629 */
3630 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3632 pbn_b2_bt_2_115200 },
3633
3634 /*
3635 * EKF addition for i960 Boards form EKF with serial port
3636 */
3637 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3638 0xE4BF, PCI_ANY_ID, 0, 0,
3639 pbn_intel_i960 },
3640
3641 /*
3642 * Xircom Cardbus/Ethernet combos
3643 */
3644 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3646 pbn_b0_1_115200 },
3647 /*
3648 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3649 */
3650 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3652 pbn_b0_1_115200 },
3653
3654 /*
3655 * Untested PCI modems, sent in from various folks...
3656 */
3657
3658 /*
3659 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3660 */
3661 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3662 0x1048, 0x1500, 0, 0,
3663 pbn_b1_1_115200 },
3664
3665 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3666 0xFF00, 0, 0, 0,
3667 pbn_sgi_ioc3 },
3668
3669 /*
3670 * HP Diva card
3671 */
3672 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3673 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3674 pbn_b1_1_115200 },
3675 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3677 pbn_b0_5_115200 },
3678 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3680 pbn_b2_1_115200 },
3681
3682 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3684 pbn_b3_2_115200 },
3685 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3687 pbn_b3_4_115200 },
3688 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3690 pbn_b3_8_115200 },
3691
3692 /*
3693 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3694 */
3695 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3696 PCI_ANY_ID, PCI_ANY_ID,
3697 0,
3698 0, pbn_exar_XR17C152 },
3699 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3700 PCI_ANY_ID, PCI_ANY_ID,
3701 0,
3702 0, pbn_exar_XR17C154 },
3703 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3704 PCI_ANY_ID, PCI_ANY_ID,
3705 0,
3706 0, pbn_exar_XR17C158 },
3707
3708 /*
3709 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3710 */
3711 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3713 pbn_b0_1_115200 },
3714 /*
3715 * ITE
3716 */
3717 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3718 PCI_ANY_ID, PCI_ANY_ID,
3719 0, 0,
3720 pbn_b1_bt_1_115200 },
3721
3722 /*
3723 * IntaShield IS-200
3724 */
3725 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3727 pbn_b2_2_115200 },
3728 /*
3729 * IntaShield IS-400
3730 */
3731 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3733 pbn_b2_4_115200 },
3734 /*
3735 * Perle PCI-RAS cards
3736 */
3737 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3738 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3739 0, 0, pbn_b2_4_921600 },
3740 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3741 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3742 0, 0, pbn_b2_8_921600 },
3743
3744 /*
3745 * Mainpine series cards: Fairly standard layout but fools
3746 * parts of the autodetect in some cases and uses otherwise
3747 * unmatched communications subclasses in the PCI Express case
3748 */
3749
3750 { /* RockForceDUO */
3751 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3752 PCI_VENDOR_ID_MAINPINE, 0x0200,
3753 0, 0, pbn_b0_2_115200 },
3754 { /* RockForceQUATRO */
3755 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3756 PCI_VENDOR_ID_MAINPINE, 0x0300,
3757 0, 0, pbn_b0_4_115200 },
3758 { /* RockForceDUO+ */
3759 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3760 PCI_VENDOR_ID_MAINPINE, 0x0400,
3761 0, 0, pbn_b0_2_115200 },
3762 { /* RockForceQUATRO+ */
3763 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3764 PCI_VENDOR_ID_MAINPINE, 0x0500,
3765 0, 0, pbn_b0_4_115200 },
3766 { /* RockForce+ */
3767 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3768 PCI_VENDOR_ID_MAINPINE, 0x0600,
3769 0, 0, pbn_b0_2_115200 },
3770 { /* RockForce+ */
3771 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3772 PCI_VENDOR_ID_MAINPINE, 0x0700,
3773 0, 0, pbn_b0_4_115200 },
3774 { /* RockForceOCTO+ */
3775 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3776 PCI_VENDOR_ID_MAINPINE, 0x0800,
3777 0, 0, pbn_b0_8_115200 },
3778 { /* RockForceDUO+ */
3779 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3780 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3781 0, 0, pbn_b0_2_115200 },
3782 { /* RockForceQUARTRO+ */
3783 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3784 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3785 0, 0, pbn_b0_4_115200 },
3786 { /* RockForceOCTO+ */
3787 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3788 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3789 0, 0, pbn_b0_8_115200 },
3790 { /* RockForceD1 */
3791 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3792 PCI_VENDOR_ID_MAINPINE, 0x2000,
3793 0, 0, pbn_b0_1_115200 },
3794 { /* RockForceF1 */
3795 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3796 PCI_VENDOR_ID_MAINPINE, 0x2100,
3797 0, 0, pbn_b0_1_115200 },
3798 { /* RockForceD2 */
3799 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3800 PCI_VENDOR_ID_MAINPINE, 0x2200,
3801 0, 0, pbn_b0_2_115200 },
3802 { /* RockForceF2 */
3803 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3804 PCI_VENDOR_ID_MAINPINE, 0x2300,
3805 0, 0, pbn_b0_2_115200 },
3806 { /* RockForceD4 */
3807 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3808 PCI_VENDOR_ID_MAINPINE, 0x2400,
3809 0, 0, pbn_b0_4_115200 },
3810 { /* RockForceF4 */
3811 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3812 PCI_VENDOR_ID_MAINPINE, 0x2500,
3813 0, 0, pbn_b0_4_115200 },
3814 { /* RockForceD8 */
3815 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3816 PCI_VENDOR_ID_MAINPINE, 0x2600,
3817 0, 0, pbn_b0_8_115200 },
3818 { /* RockForceF8 */
3819 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3820 PCI_VENDOR_ID_MAINPINE, 0x2700,
3821 0, 0, pbn_b0_8_115200 },
3822 { /* IQ Express D1 */
3823 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3824 PCI_VENDOR_ID_MAINPINE, 0x3000,
3825 0, 0, pbn_b0_1_115200 },
3826 { /* IQ Express F1 */
3827 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3828 PCI_VENDOR_ID_MAINPINE, 0x3100,
3829 0, 0, pbn_b0_1_115200 },
3830 { /* IQ Express D2 */
3831 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3832 PCI_VENDOR_ID_MAINPINE, 0x3200,
3833 0, 0, pbn_b0_2_115200 },
3834 { /* IQ Express F2 */
3835 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3836 PCI_VENDOR_ID_MAINPINE, 0x3300,
3837 0, 0, pbn_b0_2_115200 },
3838 { /* IQ Express D4 */
3839 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3840 PCI_VENDOR_ID_MAINPINE, 0x3400,
3841 0, 0, pbn_b0_4_115200 },
3842 { /* IQ Express F4 */
3843 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3844 PCI_VENDOR_ID_MAINPINE, 0x3500,
3845 0, 0, pbn_b0_4_115200 },
3846 { /* IQ Express D8 */
3847 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3848 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3849 0, 0, pbn_b0_8_115200 },
3850 { /* IQ Express F8 */
3851 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3852 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3853 0, 0, pbn_b0_8_115200 },
3854
3855
3856 /*
3857 * PA Semi PA6T-1682M on-chip UART
3858 */
3859 { PCI_VENDOR_ID_PASEMI, 0xa004,
3860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3861 pbn_pasemi_1682M },
3862
3863 /*
3864 * National Instruments
3865 */
3866 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3868 pbn_b1_16_115200 },
3869 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3871 pbn_b1_8_115200 },
3872 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3874 pbn_b1_bt_4_115200 },
3875 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3877 pbn_b1_bt_2_115200 },
3878 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3880 pbn_b1_bt_4_115200 },
3881 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3883 pbn_b1_bt_2_115200 },
3884 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3886 pbn_b1_16_115200 },
3887 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3889 pbn_b1_8_115200 },
3890 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3892 pbn_b1_bt_4_115200 },
3893 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3895 pbn_b1_bt_2_115200 },
3896 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3898 pbn_b1_bt_4_115200 },
3899 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3901 pbn_b1_bt_2_115200 },
3902 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3904 pbn_ni8430_2 },
3905 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3907 pbn_ni8430_2 },
3908 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3910 pbn_ni8430_4 },
3911 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3913 pbn_ni8430_4 },
3914 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3916 pbn_ni8430_8 },
3917 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3919 pbn_ni8430_8 },
3920 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3922 pbn_ni8430_16 },
3923 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3925 pbn_ni8430_16 },
3926 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3928 pbn_ni8430_2 },
3929 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3931 pbn_ni8430_2 },
3932 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3934 pbn_ni8430_4 },
3935 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3937 pbn_ni8430_4 },
3938
3939 /*
3940 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3941 */
3942 { PCI_VENDOR_ID_ADDIDATA,
3943 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3944 PCI_ANY_ID,
3945 PCI_ANY_ID,
3946 0,
3947 0,
3948 pbn_b0_4_115200 },
3949
3950 { PCI_VENDOR_ID_ADDIDATA,
3951 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3952 PCI_ANY_ID,
3953 PCI_ANY_ID,
3954 0,
3955 0,
3956 pbn_b0_2_115200 },
3957
3958 { PCI_VENDOR_ID_ADDIDATA,
3959 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3960 PCI_ANY_ID,
3961 PCI_ANY_ID,
3962 0,
3963 0,
3964 pbn_b0_1_115200 },
3965
3966 { PCI_VENDOR_ID_ADDIDATA_OLD,
3967 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3968 PCI_ANY_ID,
3969 PCI_ANY_ID,
3970 0,
3971 0,
3972 pbn_b1_8_115200 },
3973
3974 { PCI_VENDOR_ID_ADDIDATA,
3975 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3976 PCI_ANY_ID,
3977 PCI_ANY_ID,
3978 0,
3979 0,
3980 pbn_b0_4_115200 },
3981
3982 { PCI_VENDOR_ID_ADDIDATA,
3983 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3984 PCI_ANY_ID,
3985 PCI_ANY_ID,
3986 0,
3987 0,
3988 pbn_b0_2_115200 },
3989
3990 { PCI_VENDOR_ID_ADDIDATA,
3991 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3992 PCI_ANY_ID,
3993 PCI_ANY_ID,
3994 0,
3995 0,
3996 pbn_b0_1_115200 },
3997
3998 { PCI_VENDOR_ID_ADDIDATA,
3999 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4000 PCI_ANY_ID,
4001 PCI_ANY_ID,
4002 0,
4003 0,
4004 pbn_b0_4_115200 },
4005
4006 { PCI_VENDOR_ID_ADDIDATA,
4007 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4008 PCI_ANY_ID,
4009 PCI_ANY_ID,
4010 0,
4011 0,
4012 pbn_b0_2_115200 },
4013
4014 { PCI_VENDOR_ID_ADDIDATA,
4015 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4016 PCI_ANY_ID,
4017 PCI_ANY_ID,
4018 0,
4019 0,
4020 pbn_b0_1_115200 },
4021
4022 { PCI_VENDOR_ID_ADDIDATA,
4023 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4024 PCI_ANY_ID,
4025 PCI_ANY_ID,
4026 0,
4027 0,
4028 pbn_b0_8_115200 },
4029
4030 { PCI_VENDOR_ID_ADDIDATA,
4031 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4032 PCI_ANY_ID,
4033 PCI_ANY_ID,
4034 0,
4035 0,
4036 pbn_ADDIDATA_PCIe_4_3906250 },
4037
4038 { PCI_VENDOR_ID_ADDIDATA,
4039 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4040 PCI_ANY_ID,
4041 PCI_ANY_ID,
4042 0,
4043 0,
4044 pbn_ADDIDATA_PCIe_2_3906250 },
4045
4046 { PCI_VENDOR_ID_ADDIDATA,
4047 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4048 PCI_ANY_ID,
4049 PCI_ANY_ID,
4050 0,
4051 0,
4052 pbn_ADDIDATA_PCIe_1_3906250 },
4053
4054 { PCI_VENDOR_ID_ADDIDATA,
4055 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4056 PCI_ANY_ID,
4057 PCI_ANY_ID,
4058 0,
4059 0,
4060 pbn_ADDIDATA_PCIe_8_3906250 },
4061
4062 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4063 PCI_VENDOR_ID_IBM, 0x0299,
4064 0, 0, pbn_b0_bt_2_115200 },
4065
4066 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4067 0xA000, 0x1000,
4068 0, 0, pbn_b0_1_115200 },
4069
4070 /* the 9901 is a rebranded 9912 */
4071 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4072 0xA000, 0x1000,
4073 0, 0, pbn_b0_1_115200 },
4074
4075 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4076 0xA000, 0x1000,
4077 0, 0, pbn_b0_1_115200 },
4078
4079 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4080 0xA000, 0x1000,
4081 0, 0, pbn_b0_1_115200 },
4082
4083 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4084 0xA000, 0x1000,
4085 0, 0, pbn_b0_1_115200 },
4086
4087 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4088 0xA000, 0x3002,
4089 0, 0, pbn_NETMOS9900_2s_115200 },
4090
4091 /*
4092 * Best Connectivity and Rosewill PCI Multi I/O cards
4093 */
4094
4095 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4096 0xA000, 0x1000,
4097 0, 0, pbn_b0_1_115200 },
4098
4099 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4100 0xA000, 0x3002,
4101 0, 0, pbn_b0_bt_2_115200 },
4102
4103 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4104 0xA000, 0x3004,
4105 0, 0, pbn_b0_bt_4_115200 },
4106 /* Intel CE4100 */
4107 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109 pbn_ce4100_1_115200 },
4110
4111 /*
4112 * Cronyx Omega PCI
4113 */
4114 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4116 pbn_omegapci },
4117
4118 /*
4119 * These entries match devices with class COMMUNICATION_SERIAL,
4120 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4121 */
4122 { PCI_ANY_ID, PCI_ANY_ID,
4123 PCI_ANY_ID, PCI_ANY_ID,
4124 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4125 0xffff00, pbn_default },
4126 { PCI_ANY_ID, PCI_ANY_ID,
4127 PCI_ANY_ID, PCI_ANY_ID,
4128 PCI_CLASS_COMMUNICATION_MODEM << 8,
4129 0xffff00, pbn_default },
4130 { PCI_ANY_ID, PCI_ANY_ID,
4131 PCI_ANY_ID, PCI_ANY_ID,
4132 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4133 0xffff00, pbn_default },
4134 { 0, }
4135 };
4136
4137 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4138 pci_channel_state_t state)
4139 {
4140 struct serial_private *priv = pci_get_drvdata(dev);
4141
4142 if (state == pci_channel_io_perm_failure)
4143 return PCI_ERS_RESULT_DISCONNECT;
4144
4145 if (priv)
4146 pciserial_suspend_ports(priv);
4147
4148 pci_disable_device(dev);
4149
4150 return PCI_ERS_RESULT_NEED_RESET;
4151 }
4152
4153 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4154 {
4155 int rc;
4156
4157 rc = pci_enable_device(dev);
4158
4159 if (rc)
4160 return PCI_ERS_RESULT_DISCONNECT;
4161
4162 pci_restore_state(dev);
4163 pci_save_state(dev);
4164
4165 return PCI_ERS_RESULT_RECOVERED;
4166 }
4167
4168 static void serial8250_io_resume(struct pci_dev *dev)
4169 {
4170 struct serial_private *priv = pci_get_drvdata(dev);
4171
4172 if (priv)
4173 pciserial_resume_ports(priv);
4174 }
4175
4176 static struct pci_error_handlers serial8250_err_handler = {
4177 .error_detected = serial8250_io_error_detected,
4178 .slot_reset = serial8250_io_slot_reset,
4179 .resume = serial8250_io_resume,
4180 };
4181
4182 static struct pci_driver serial_pci_driver = {
4183 .name = "serial",
4184 .probe = pciserial_init_one,
4185 .remove = __devexit_p(pciserial_remove_one),
4186 #ifdef CONFIG_PM
4187 .suspend = pciserial_suspend_one,
4188 .resume = pciserial_resume_one,
4189 #endif
4190 .id_table = serial_pci_tbl,
4191 .err_handler = &serial8250_err_handler,
4192 };
4193
4194 static int __init serial8250_pci_init(void)
4195 {
4196 return pci_register_driver(&serial_pci_driver);
4197 }
4198
4199 static void __exit serial8250_pci_exit(void)
4200 {
4201 pci_unregister_driver(&serial_pci_driver);
4202 }
4203
4204 module_init(serial8250_pci_init);
4205 module_exit(serial8250_pci_exit);
4206
4207 MODULE_LICENSE("GPL");
4208 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4209 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);