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i2c-eg20t: change timeout value 50msec to 1000msec
[zen-stable.git] / drivers / tty / serial / sunzilog.c
blob8e916e76b7b54c851305bb746034142a369530d1
1 /* sunzilog.c: Zilog serial driver for Sparc systems.
2 *
3 * Driver for Zilog serial chips found on Sun workstations and
4 * servers. This driver could actually be made more generic.
5 *
6 * This is based on the old drivers/sbus/char/zs.c code. A lot
7 * of code has been simply moved over directly from there but
8 * much has been rewritten. Credits therefore go out to Eddie
9 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10 * work there.
11 *
12 * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #ifdef CONFIG_SERIO
32 #include <linux/serio.h>
33 #endif
34 #include <linux/init.h>
35 #include <linux/of_device.h>
36
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/prom.h>
40
41 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42 #define SUPPORT_SYSRQ
43 #endif
44
45 #include <linux/serial_core.h>
46
47 #include "suncore.h"
48 #include "sunzilog.h"
49
50 /* On 32-bit sparcs we need to delay after register accesses
51 * to accommodate sun4 systems, but we do not need to flush writes.
52 * On 64-bit sparc we only need to flush single writes to ensure
53 * completion.
54 */
55 #ifndef CONFIG_SPARC64
56 #define ZSDELAY() udelay(5)
57 #define ZSDELAY_LONG() udelay(20)
58 #define ZS_WSYNC(channel) do { } while (0)
59 #else
60 #define ZSDELAY()
61 #define ZSDELAY_LONG()
62 #define ZS_WSYNC(__channel) \
63 readb(&((__channel)->control))
64 #endif
65
66 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
67 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
68
69 /*
70 * We wrap our port structure around the generic uart_port.
71 */
72 struct uart_sunzilog_port {
73 struct uart_port port;
74
75 /* IRQ servicing chain. */
76 struct uart_sunzilog_port *next;
77
78 /* Current values of Zilog write registers. */
79 unsigned char curregs[NUM_ZSREGS];
80
81 unsigned int flags;
82 #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
83 #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
84 #define SUNZILOG_FLAG_IS_CONS 0x00000004
85 #define SUNZILOG_FLAG_IS_KGDB 0x00000008
86 #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
87 #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
88 #define SUNZILOG_FLAG_REGS_HELD 0x00000040
89 #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
90 #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
91 #define SUNZILOG_FLAG_ESCC 0x00000200
92 #define SUNZILOG_FLAG_ISR_HANDLER 0x00000400
93
94 unsigned int cflag;
95
96 unsigned char parity_mask;
97 unsigned char prev_status;
98
99 #ifdef CONFIG_SERIO
100 struct serio serio;
101 int serio_open;
102 #endif
103 };
104
105 static void sunzilog_putchar(struct uart_port *port, int ch);
106
107 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
108 #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
109
110 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
111 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
112 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
113 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
114 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
115 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
116 #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
117 #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
118 #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
119
120 /* Reading and writing Zilog8530 registers. The delays are to make this
121 * driver work on the Sun4 which needs a settling delay after each chip
122 * register access, other machines handle this in hardware via auxiliary
123 * flip-flops which implement the settle time we do in software.
124 *
125 * The port lock must be held and local IRQs must be disabled
126 * when {read,write}_zsreg is invoked.
127 */
128 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
129 unsigned char reg)
130 {
131 unsigned char retval;
132
133 writeb(reg, &channel->control);
134 ZSDELAY();
135 retval = readb(&channel->control);
136 ZSDELAY();
137
138 return retval;
139 }
140
141 static void write_zsreg(struct zilog_channel __iomem *channel,
142 unsigned char reg, unsigned char value)
143 {
144 writeb(reg, &channel->control);
145 ZSDELAY();
146 writeb(value, &channel->control);
147 ZSDELAY();
148 }
149
150 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
151 {
152 int i;
153
154 for (i = 0; i < 32; i++) {
155 unsigned char regval;
156
157 regval = readb(&channel->control);
158 ZSDELAY();
159 if (regval & Rx_CH_AV)
160 break;
161
162 regval = read_zsreg(channel, R1);
163 readb(&channel->data);
164 ZSDELAY();
165
166 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
167 writeb(ERR_RES, &channel->control);
168 ZSDELAY();
169 ZS_WSYNC(channel);
170 }
171 }
172 }
173
174 /* This function must only be called when the TX is not busy. The UART
175 * port lock must be held and local interrupts disabled.
176 */
177 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
178 {
179 int i;
180 int escc;
181 unsigned char r15;
182
183 /* Let pending transmits finish. */
184 for (i = 0; i < 1000; i++) {
185 unsigned char stat = read_zsreg(channel, R1);
186 if (stat & ALL_SNT)
187 break;
188 udelay(100);
189 }
190
191 writeb(ERR_RES, &channel->control);
192 ZSDELAY();
193 ZS_WSYNC(channel);
194
195 sunzilog_clear_fifo(channel);
196
197 /* Disable all interrupts. */
198 write_zsreg(channel, R1,
199 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
200
201 /* Set parity, sync config, stop bits, and clock divisor. */
202 write_zsreg(channel, R4, regs[R4]);
203
204 /* Set misc. TX/RX control bits. */
205 write_zsreg(channel, R10, regs[R10]);
206
207 /* Set TX/RX controls sans the enable bits. */
208 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
209 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
210
211 /* Synchronous mode config. */
212 write_zsreg(channel, R6, regs[R6]);
213 write_zsreg(channel, R7, regs[R7]);
214
215 /* Don't mess with the interrupt vector (R2, unused by us) and
216 * master interrupt control (R9). We make sure this is setup
217 * properly at probe time then never touch it again.
218 */
219
220 /* Disable baud generator. */
221 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
222
223 /* Clock mode control. */
224 write_zsreg(channel, R11, regs[R11]);
225
226 /* Lower and upper byte of baud rate generator divisor. */
227 write_zsreg(channel, R12, regs[R12]);
228 write_zsreg(channel, R13, regs[R13]);
229
230 /* Now rewrite R14, with BRENAB (if set). */
231 write_zsreg(channel, R14, regs[R14]);
232
233 /* External status interrupt control. */
234 write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
235
236 /* ESCC Extension Register */
237 r15 = read_zsreg(channel, R15);
238 if (r15 & 0x01) {
239 write_zsreg(channel, R7, regs[R7p]);
240
241 /* External status interrupt and FIFO control. */
242 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
243 escc = 1;
244 } else {
245 /* Clear FIFO bit case it is an issue */
246 regs[R15] &= ~FIFOEN;
247 escc = 0;
248 }
249
250 /* Reset external status interrupts. */
251 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */
252 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
253
254 /* Rewrite R3/R5, this time without enables masked. */
255 write_zsreg(channel, R3, regs[R3]);
256 write_zsreg(channel, R5, regs[R5]);
257
258 /* Rewrite R1, this time without IRQ enabled masked. */
259 write_zsreg(channel, R1, regs[R1]);
260
261 return escc;
262 }
263
264 /* Reprogram the Zilog channel HW registers with the copies found in the
265 * software state struct. If the transmitter is busy, we defer this update
266 * until the next TX complete interrupt. Else, we do it right now.
267 *
268 * The UART port lock must be held and local interrupts disabled.
269 */
270 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
271 struct zilog_channel __iomem *channel)
272 {
273 if (!ZS_REGS_HELD(up)) {
274 if (ZS_TX_ACTIVE(up)) {
275 up->flags |= SUNZILOG_FLAG_REGS_HELD;
276 } else {
277 __load_zsregs(channel, up->curregs);
278 }
279 }
280 }
281
282 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
283 {
284 unsigned int cur_cflag = up->cflag;
285 int brg, new_baud;
286
287 up->cflag &= ~CBAUD;
288 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
289
290 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
291 up->curregs[R12] = (brg & 0xff);
292 up->curregs[R13] = (brg >> 8) & 0xff;
293 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
294 }
295
296 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
297 unsigned char ch, int is_break)
298 {
299 if (ZS_IS_KEYB(up)) {
300 /* Stop-A is handled by drivers/char/keyboard.c now. */
301 #ifdef CONFIG_SERIO
302 if (up->serio_open)
303 serio_interrupt(&up->serio, ch, 0);
304 #endif
305 } else if (ZS_IS_MOUSE(up)) {
306 int ret = suncore_mouse_baud_detection(ch, is_break);
307
308 switch (ret) {
309 case 2:
310 sunzilog_change_mouse_baud(up);
311 /* fallthru */
312 case 1:
313 break;
314
315 case 0:
316 #ifdef CONFIG_SERIO
317 if (up->serio_open)
318 serio_interrupt(&up->serio, ch, 0);
319 #endif
320 break;
321 };
322 }
323 }
324
325 static struct tty_struct *
326 sunzilog_receive_chars(struct uart_sunzilog_port *up,
327 struct zilog_channel __iomem *channel)
328 {
329 struct tty_struct *tty;
330 unsigned char ch, r1, flag;
331
332 tty = NULL;
333 if (up->port.state != NULL && /* Unopened serial console */
334 up->port.state->port.tty != NULL) /* Keyboard || mouse */
335 tty = up->port.state->port.tty;
336
337 for (;;) {
338
339 r1 = read_zsreg(channel, R1);
340 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
341 writeb(ERR_RES, &channel->control);
342 ZSDELAY();
343 ZS_WSYNC(channel);
344 }
345
346 ch = readb(&channel->control);
347 ZSDELAY();
348
349 /* This funny hack depends upon BRK_ABRT not interfering
350 * with the other bits we care about in R1.
351 */
352 if (ch & BRK_ABRT)
353 r1 |= BRK_ABRT;
354
355 if (!(ch & Rx_CH_AV))
356 break;
357
358 ch = readb(&channel->data);
359 ZSDELAY();
360
361 ch &= up->parity_mask;
362
363 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
364 sunzilog_kbdms_receive_chars(up, ch, 0);
365 continue;
366 }
367
368 if (tty == NULL) {
369 uart_handle_sysrq_char(&up->port, ch);
370 continue;
371 }
372
373 /* A real serial line, record the character and status. */
374 flag = TTY_NORMAL;
375 up->port.icount.rx++;
376 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
377 if (r1 & BRK_ABRT) {
378 r1 &= ~(PAR_ERR | CRC_ERR);
379 up->port.icount.brk++;
380 if (uart_handle_break(&up->port))
381 continue;
382 }
383 else if (r1 & PAR_ERR)
384 up->port.icount.parity++;
385 else if (r1 & CRC_ERR)
386 up->port.icount.frame++;
387 if (r1 & Rx_OVR)
388 up->port.icount.overrun++;
389 r1 &= up->port.read_status_mask;
390 if (r1 & BRK_ABRT)
391 flag = TTY_BREAK;
392 else if (r1 & PAR_ERR)
393 flag = TTY_PARITY;
394 else if (r1 & CRC_ERR)
395 flag = TTY_FRAME;
396 }
397 if (uart_handle_sysrq_char(&up->port, ch))
398 continue;
399
400 if (up->port.ignore_status_mask == 0xff ||
401 (r1 & up->port.ignore_status_mask) == 0) {
402 tty_insert_flip_char(tty, ch, flag);
403 }
404 if (r1 & Rx_OVR)
405 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
406 }
407
408 return tty;
409 }
410
411 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
412 struct zilog_channel __iomem *channel)
413 {
414 unsigned char status;
415
416 status = readb(&channel->control);
417 ZSDELAY();
418
419 writeb(RES_EXT_INT, &channel->control);
420 ZSDELAY();
421 ZS_WSYNC(channel);
422
423 if (status & BRK_ABRT) {
424 if (ZS_IS_MOUSE(up))
425 sunzilog_kbdms_receive_chars(up, 0, 1);
426 if (ZS_IS_CONS(up)) {
427 /* Wait for BREAK to deassert to avoid potentially
428 * confusing the PROM.
429 */
430 while (1) {
431 status = readb(&channel->control);
432 ZSDELAY();
433 if (!(status & BRK_ABRT))
434 break;
435 }
436 sun_do_break();
437 return;
438 }
439 }
440
441 if (ZS_WANTS_MODEM_STATUS(up)) {
442 if (status & SYNC)
443 up->port.icount.dsr++;
444
445 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
446 * But it does not tell us which bit has changed, we have to keep
447 * track of this ourselves.
448 */
449 if ((status ^ up->prev_status) ^ DCD)
450 uart_handle_dcd_change(&up->port,
451 (status & DCD));
452 if ((status ^ up->prev_status) ^ CTS)
453 uart_handle_cts_change(&up->port,
454 (status & CTS));
455
456 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
457 }
458
459 up->prev_status = status;
460 }
461
462 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
463 struct zilog_channel __iomem *channel)
464 {
465 struct circ_buf *xmit;
466
467 if (ZS_IS_CONS(up)) {
468 unsigned char status = readb(&channel->control);
469 ZSDELAY();
470
471 /* TX still busy? Just wait for the next TX done interrupt.
472 *
473 * It can occur because of how we do serial console writes. It would
474 * be nice to transmit console writes just like we normally would for
475 * a TTY line. (ie. buffered and TX interrupt driven). That is not
476 * easy because console writes cannot sleep. One solution might be
477 * to poll on enough port->xmit space becoming free. -DaveM
478 */
479 if (!(status & Tx_BUF_EMP))
480 return;
481 }
482
483 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
484
485 if (ZS_REGS_HELD(up)) {
486 __load_zsregs(channel, up->curregs);
487 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
488 }
489
490 if (ZS_TX_STOPPED(up)) {
491 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
492 goto ack_tx_int;
493 }
494
495 if (up->port.x_char) {
496 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
497 writeb(up->port.x_char, &channel->data);
498 ZSDELAY();
499 ZS_WSYNC(channel);
500
501 up->port.icount.tx++;
502 up->port.x_char = 0;
503 return;
504 }
505
506 if (up->port.state == NULL)
507 goto ack_tx_int;
508 xmit = &up->port.state->xmit;
509 if (uart_circ_empty(xmit))
510 goto ack_tx_int;
511
512 if (uart_tx_stopped(&up->port))
513 goto ack_tx_int;
514
515 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
516 writeb(xmit->buf[xmit->tail], &channel->data);
517 ZSDELAY();
518 ZS_WSYNC(channel);
519
520 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
521 up->port.icount.tx++;
522
523 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
524 uart_write_wakeup(&up->port);
525
526 return;
527
528 ack_tx_int:
529 writeb(RES_Tx_P, &channel->control);
530 ZSDELAY();
531 ZS_WSYNC(channel);
532 }
533
534 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
535 {
536 struct uart_sunzilog_port *up = dev_id;
537
538 while (up) {
539 struct zilog_channel __iomem *channel
540 = ZILOG_CHANNEL_FROM_PORT(&up->port);
541 struct tty_struct *tty;
542 unsigned char r3;
543
544 spin_lock(&up->port.lock);
545 r3 = read_zsreg(channel, R3);
546
547 /* Channel A */
548 tty = NULL;
549 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
550 writeb(RES_H_IUS, &channel->control);
551 ZSDELAY();
552 ZS_WSYNC(channel);
553
554 if (r3 & CHARxIP)
555 tty = sunzilog_receive_chars(up, channel);
556 if (r3 & CHAEXT)
557 sunzilog_status_handle(up, channel);
558 if (r3 & CHATxIP)
559 sunzilog_transmit_chars(up, channel);
560 }
561 spin_unlock(&up->port.lock);
562
563 if (tty)
564 tty_flip_buffer_push(tty);
565
566 /* Channel B */
567 up = up->next;
568 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
569
570 spin_lock(&up->port.lock);
571 tty = NULL;
572 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
573 writeb(RES_H_IUS, &channel->control);
574 ZSDELAY();
575 ZS_WSYNC(channel);
576
577 if (r3 & CHBRxIP)
578 tty = sunzilog_receive_chars(up, channel);
579 if (r3 & CHBEXT)
580 sunzilog_status_handle(up, channel);
581 if (r3 & CHBTxIP)
582 sunzilog_transmit_chars(up, channel);
583 }
584 spin_unlock(&up->port.lock);
585
586 if (tty)
587 tty_flip_buffer_push(tty);
588
589 up = up->next;
590 }
591
592 return IRQ_HANDLED;
593 }
594
595 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
596 * port lock, it is acquired here.
597 */
598 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
599 {
600 struct zilog_channel __iomem *channel;
601 unsigned char status;
602
603 channel = ZILOG_CHANNEL_FROM_PORT(port);
604 status = readb(&channel->control);
605 ZSDELAY();
606
607 return status;
608 }
609
610 /* The port lock is not held. */
611 static unsigned int sunzilog_tx_empty(struct uart_port *port)
612 {
613 unsigned long flags;
614 unsigned char status;
615 unsigned int ret;
616
617 spin_lock_irqsave(&port->lock, flags);
618
619 status = sunzilog_read_channel_status(port);
620
621 spin_unlock_irqrestore(&port->lock, flags);
622
623 if (status & Tx_BUF_EMP)
624 ret = TIOCSER_TEMT;
625 else
626 ret = 0;
627
628 return ret;
629 }
630
631 /* The port lock is held and interrupts are disabled. */
632 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
633 {
634 unsigned char status;
635 unsigned int ret;
636
637 status = sunzilog_read_channel_status(port);
638
639 ret = 0;
640 if (status & DCD)
641 ret |= TIOCM_CAR;
642 if (status & SYNC)
643 ret |= TIOCM_DSR;
644 if (status & CTS)
645 ret |= TIOCM_CTS;
646
647 return ret;
648 }
649
650 /* The port lock is held and interrupts are disabled. */
651 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
652 {
653 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
654 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
655 unsigned char set_bits, clear_bits;
656
657 set_bits = clear_bits = 0;
658
659 if (mctrl & TIOCM_RTS)
660 set_bits |= RTS;
661 else
662 clear_bits |= RTS;
663 if (mctrl & TIOCM_DTR)
664 set_bits |= DTR;
665 else
666 clear_bits |= DTR;
667
668 /* NOTE: Not subject to 'transmitter active' rule. */
669 up->curregs[R5] |= set_bits;
670 up->curregs[R5] &= ~clear_bits;
671 write_zsreg(channel, R5, up->curregs[R5]);
672 }
673
674 /* The port lock is held and interrupts are disabled. */
675 static void sunzilog_stop_tx(struct uart_port *port)
676 {
677 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
678
679 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
680 }
681
682 /* The port lock is held and interrupts are disabled. */
683 static void sunzilog_start_tx(struct uart_port *port)
684 {
685 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
686 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
687 unsigned char status;
688
689 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
690 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
691
692 status = readb(&channel->control);
693 ZSDELAY();
694
695 /* TX busy? Just wait for the TX done interrupt. */
696 if (!(status & Tx_BUF_EMP))
697 return;
698
699 /* Send the first character to jump-start the TX done
700 * IRQ sending engine.
701 */
702 if (port->x_char) {
703 writeb(port->x_char, &channel->data);
704 ZSDELAY();
705 ZS_WSYNC(channel);
706
707 port->icount.tx++;
708 port->x_char = 0;
709 } else {
710 struct circ_buf *xmit = &port->state->xmit;
711
712 writeb(xmit->buf[xmit->tail], &channel->data);
713 ZSDELAY();
714 ZS_WSYNC(channel);
715
716 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
717 port->icount.tx++;
718
719 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
720 uart_write_wakeup(&up->port);
721 }
722 }
723
724 /* The port lock is held. */
725 static void sunzilog_stop_rx(struct uart_port *port)
726 {
727 struct uart_sunzilog_port *up = UART_ZILOG(port);
728 struct zilog_channel __iomem *channel;
729
730 if (ZS_IS_CONS(up))
731 return;
732
733 channel = ZILOG_CHANNEL_FROM_PORT(port);
734
735 /* Disable all RX interrupts. */
736 up->curregs[R1] &= ~RxINT_MASK;
737 sunzilog_maybe_update_regs(up, channel);
738 }
739
740 /* The port lock is held. */
741 static void sunzilog_enable_ms(struct uart_port *port)
742 {
743 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
744 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
745 unsigned char new_reg;
746
747 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
748 if (new_reg != up->curregs[R15]) {
749 up->curregs[R15] = new_reg;
750
751 /* NOTE: Not subject to 'transmitter active' rule. */
752 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
753 }
754 }
755
756 /* The port lock is not held. */
757 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
758 {
759 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
760 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
761 unsigned char set_bits, clear_bits, new_reg;
762 unsigned long flags;
763
764 set_bits = clear_bits = 0;
765
766 if (break_state)
767 set_bits |= SND_BRK;
768 else
769 clear_bits |= SND_BRK;
770
771 spin_lock_irqsave(&port->lock, flags);
772
773 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
774 if (new_reg != up->curregs[R5]) {
775 up->curregs[R5] = new_reg;
776
777 /* NOTE: Not subject to 'transmitter active' rule. */
778 write_zsreg(channel, R5, up->curregs[R5]);
779 }
780
781 spin_unlock_irqrestore(&port->lock, flags);
782 }
783
784 static void __sunzilog_startup(struct uart_sunzilog_port *up)
785 {
786 struct zilog_channel __iomem *channel;
787
788 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
789 up->prev_status = readb(&channel->control);
790
791 /* Enable receiver and transmitter. */
792 up->curregs[R3] |= RxENAB;
793 up->curregs[R5] |= TxENAB;
794
795 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
796 sunzilog_maybe_update_regs(up, channel);
797 }
798
799 static int sunzilog_startup(struct uart_port *port)
800 {
801 struct uart_sunzilog_port *up = UART_ZILOG(port);
802 unsigned long flags;
803
804 if (ZS_IS_CONS(up))
805 return 0;
806
807 spin_lock_irqsave(&port->lock, flags);
808 __sunzilog_startup(up);
809 spin_unlock_irqrestore(&port->lock, flags);
810 return 0;
811 }
812
813 /*
814 * The test for ZS_IS_CONS is explained by the following e-mail:
815 *****
816 * From: Russell King <rmk@arm.linux.org.uk>
817 * Date: Sun, 8 Dec 2002 10:18:38 +0000
818 *
819 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
820 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
821 * > and I noticed that something is not right with reference
822 * > counting in this case. It seems that when the console
823 * > is open by kernel initially, this is not accounted
824 * > as an open, and uart_startup is not called.
825 *
826 * That is correct. We are unable to call uart_startup when the serial
827 * console is initialised because it may need to allocate memory (as
828 * request_irq does) and the memory allocators may not have been
829 * initialised.
830 *
831 * 1. initialise the port into a state where it can send characters in the
832 * console write method.
833 *
834 * 2. don't do the actual hardware shutdown in your shutdown() method (but
835 * do the normal software shutdown - ie, free irqs etc)
836 *****
837 */
838 static void sunzilog_shutdown(struct uart_port *port)
839 {
840 struct uart_sunzilog_port *up = UART_ZILOG(port);
841 struct zilog_channel __iomem *channel;
842 unsigned long flags;
843
844 if (ZS_IS_CONS(up))
845 return;
846
847 spin_lock_irqsave(&port->lock, flags);
848
849 channel = ZILOG_CHANNEL_FROM_PORT(port);
850
851 /* Disable receiver and transmitter. */
852 up->curregs[R3] &= ~RxENAB;
853 up->curregs[R5] &= ~TxENAB;
854
855 /* Disable all interrupts and BRK assertion. */
856 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
857 up->curregs[R5] &= ~SND_BRK;
858 sunzilog_maybe_update_regs(up, channel);
859
860 spin_unlock_irqrestore(&port->lock, flags);
861 }
862
863 /* Shared by TTY driver and serial console setup. The port lock is held
864 * and local interrupts are disabled.
865 */
866 static void
867 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
868 unsigned int iflag, int brg)
869 {
870
871 up->curregs[R10] = NRZ;
872 up->curregs[R11] = TCBR | RCBR;
873
874 /* Program BAUD and clock source. */
875 up->curregs[R4] &= ~XCLK_MASK;
876 up->curregs[R4] |= X16CLK;
877 up->curregs[R12] = brg & 0xff;
878 up->curregs[R13] = (brg >> 8) & 0xff;
879 up->curregs[R14] = BRSRC | BRENAB;
880
881 /* Character size, stop bits, and parity. */
882 up->curregs[R3] &= ~RxN_MASK;
883 up->curregs[R5] &= ~TxN_MASK;
884 switch (cflag & CSIZE) {
885 case CS5:
886 up->curregs[R3] |= Rx5;
887 up->curregs[R5] |= Tx5;
888 up->parity_mask = 0x1f;
889 break;
890 case CS6:
891 up->curregs[R3] |= Rx6;
892 up->curregs[R5] |= Tx6;
893 up->parity_mask = 0x3f;
894 break;
895 case CS7:
896 up->curregs[R3] |= Rx7;
897 up->curregs[R5] |= Tx7;
898 up->parity_mask = 0x7f;
899 break;
900 case CS8:
901 default:
902 up->curregs[R3] |= Rx8;
903 up->curregs[R5] |= Tx8;
904 up->parity_mask = 0xff;
905 break;
906 };
907 up->curregs[R4] &= ~0x0c;
908 if (cflag & CSTOPB)
909 up->curregs[R4] |= SB2;
910 else
911 up->curregs[R4] |= SB1;
912 if (cflag & PARENB)
913 up->curregs[R4] |= PAR_ENAB;
914 else
915 up->curregs[R4] &= ~PAR_ENAB;
916 if (!(cflag & PARODD))
917 up->curregs[R4] |= PAR_EVEN;
918 else
919 up->curregs[R4] &= ~PAR_EVEN;
920
921 up->port.read_status_mask = Rx_OVR;
922 if (iflag & INPCK)
923 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
924 if (iflag & (BRKINT | PARMRK))
925 up->port.read_status_mask |= BRK_ABRT;
926
927 up->port.ignore_status_mask = 0;
928 if (iflag & IGNPAR)
929 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
930 if (iflag & IGNBRK) {
931 up->port.ignore_status_mask |= BRK_ABRT;
932 if (iflag & IGNPAR)
933 up->port.ignore_status_mask |= Rx_OVR;
934 }
935
936 if ((cflag & CREAD) == 0)
937 up->port.ignore_status_mask = 0xff;
938 }
939
940 /* The port lock is not held. */
941 static void
942 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
943 struct ktermios *old)
944 {
945 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
946 unsigned long flags;
947 int baud, brg;
948
949 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
950
951 spin_lock_irqsave(&up->port.lock, flags);
952
953 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
954
955 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
956
957 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
958 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
959 else
960 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
961
962 up->cflag = termios->c_cflag;
963
964 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
965
966 uart_update_timeout(port, termios->c_cflag, baud);
967
968 spin_unlock_irqrestore(&up->port.lock, flags);
969 }
970
971 static const char *sunzilog_type(struct uart_port *port)
972 {
973 struct uart_sunzilog_port *up = UART_ZILOG(port);
974
975 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
976 }
977
978 /* We do not request/release mappings of the registers here, this
979 * happens at early serial probe time.
980 */
981 static void sunzilog_release_port(struct uart_port *port)
982 {
983 }
984
985 static int sunzilog_request_port(struct uart_port *port)
986 {
987 return 0;
988 }
989
990 /* These do not need to do anything interesting either. */
991 static void sunzilog_config_port(struct uart_port *port, int flags)
992 {
993 }
994
995 /* We do not support letting the user mess with the divisor, IRQ, etc. */
996 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
997 {
998 return -EINVAL;
999 }
1000
1001 #ifdef CONFIG_CONSOLE_POLL
1002 static int sunzilog_get_poll_char(struct uart_port *port)
1003 {
1004 unsigned char ch, r1;
1005 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
1006 struct zilog_channel __iomem *channel
1007 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1008
1009
1010 r1 = read_zsreg(channel, R1);
1011 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1012 writeb(ERR_RES, &channel->control);
1013 ZSDELAY();
1014 ZS_WSYNC(channel);
1015 }
1016
1017 ch = readb(&channel->control);
1018 ZSDELAY();
1019
1020 /* This funny hack depends upon BRK_ABRT not interfering
1021 * with the other bits we care about in R1.
1022 */
1023 if (ch & BRK_ABRT)
1024 r1 |= BRK_ABRT;
1025
1026 if (!(ch & Rx_CH_AV))
1027 return NO_POLL_CHAR;
1028
1029 ch = readb(&channel->data);
1030 ZSDELAY();
1031
1032 ch &= up->parity_mask;
1033 return ch;
1034 }
1035
1036 static void sunzilog_put_poll_char(struct uart_port *port,
1037 unsigned char ch)
1038 {
1039 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *)port;
1040
1041 sunzilog_putchar(&up->port, ch);
1042 }
1043 #endif /* CONFIG_CONSOLE_POLL */
1044
1045 static struct uart_ops sunzilog_pops = {
1046 .tx_empty = sunzilog_tx_empty,
1047 .set_mctrl = sunzilog_set_mctrl,
1048 .get_mctrl = sunzilog_get_mctrl,
1049 .stop_tx = sunzilog_stop_tx,
1050 .start_tx = sunzilog_start_tx,
1051 .stop_rx = sunzilog_stop_rx,
1052 .enable_ms = sunzilog_enable_ms,
1053 .break_ctl = sunzilog_break_ctl,
1054 .startup = sunzilog_startup,
1055 .shutdown = sunzilog_shutdown,
1056 .set_termios = sunzilog_set_termios,
1057 .type = sunzilog_type,
1058 .release_port = sunzilog_release_port,
1059 .request_port = sunzilog_request_port,
1060 .config_port = sunzilog_config_port,
1061 .verify_port = sunzilog_verify_port,
1062 #ifdef CONFIG_CONSOLE_POLL
1063 .poll_get_char = sunzilog_get_poll_char,
1064 .poll_put_char = sunzilog_put_poll_char,
1065 #endif
1066 };
1067
1068 static int uart_chip_count;
1069 static struct uart_sunzilog_port *sunzilog_port_table;
1070 static struct zilog_layout __iomem **sunzilog_chip_regs;
1071
1072 static struct uart_sunzilog_port *sunzilog_irq_chain;
1073
1074 static struct uart_driver sunzilog_reg = {
1075 .owner = THIS_MODULE,
1076 .driver_name = "sunzilog",
1077 .dev_name = "ttyS",
1078 .major = TTY_MAJOR,
1079 };
1080
1081 static int __init sunzilog_alloc_tables(int num_sunzilog)
1082 {
1083 struct uart_sunzilog_port *up;
1084 unsigned long size;
1085 int num_channels = num_sunzilog * 2;
1086 int i;
1087
1088 size = num_channels * sizeof(struct uart_sunzilog_port);
1089 sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1090 if (!sunzilog_port_table)
1091 return -ENOMEM;
1092
1093 for (i = 0; i < num_channels; i++) {
1094 up = &sunzilog_port_table[i];
1095
1096 spin_lock_init(&up->port.lock);
1097
1098 if (i == 0)
1099 sunzilog_irq_chain = up;
1100
1101 if (i < num_channels - 1)
1102 up->next = up + 1;
1103 else
1104 up->next = NULL;
1105 }
1106
1107 size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1108 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1109 if (!sunzilog_chip_regs) {
1110 kfree(sunzilog_port_table);
1111 sunzilog_irq_chain = NULL;
1112 return -ENOMEM;
1113 }
1114
1115 return 0;
1116 }
1117
1118 static void sunzilog_free_tables(void)
1119 {
1120 kfree(sunzilog_port_table);
1121 sunzilog_irq_chain = NULL;
1122 kfree(sunzilog_chip_regs);
1123 }
1124
1125 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1126
1127 static void sunzilog_putchar(struct uart_port *port, int ch)
1128 {
1129 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1130 int loops = ZS_PUT_CHAR_MAX_DELAY;
1131
1132 /* This is a timed polling loop so do not switch the explicit
1133 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1134 */
1135 do {
1136 unsigned char val = readb(&channel->control);
1137 if (val & Tx_BUF_EMP) {
1138 ZSDELAY();
1139 break;
1140 }
1141 udelay(5);
1142 } while (--loops);
1143
1144 writeb(ch, &channel->data);
1145 ZSDELAY();
1146 ZS_WSYNC(channel);
1147 }
1148
1149 #ifdef CONFIG_SERIO
1150
1151 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1152
1153 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1154 {
1155 struct uart_sunzilog_port *up = serio->port_data;
1156 unsigned long flags;
1157
1158 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1159
1160 sunzilog_putchar(&up->port, ch);
1161
1162 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1163
1164 return 0;
1165 }
1166
1167 static int sunzilog_serio_open(struct serio *serio)
1168 {
1169 struct uart_sunzilog_port *up = serio->port_data;
1170 unsigned long flags;
1171 int ret;
1172
1173 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1174 if (!up->serio_open) {
1175 up->serio_open = 1;
1176 ret = 0;
1177 } else
1178 ret = -EBUSY;
1179 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1180
1181 return ret;
1182 }
1183
1184 static void sunzilog_serio_close(struct serio *serio)
1185 {
1186 struct uart_sunzilog_port *up = serio->port_data;
1187 unsigned long flags;
1188
1189 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1190 up->serio_open = 0;
1191 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1192 }
1193
1194 #endif /* CONFIG_SERIO */
1195
1196 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1197 static void
1198 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1199 {
1200 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1201 unsigned long flags;
1202 int locked = 1;
1203
1204 local_irq_save(flags);
1205 if (up->port.sysrq) {
1206 locked = 0;
1207 } else if (oops_in_progress) {
1208 locked = spin_trylock(&up->port.lock);
1209 } else
1210 spin_lock(&up->port.lock);
1211
1212 uart_console_write(&up->port, s, count, sunzilog_putchar);
1213 udelay(2);
1214
1215 if (locked)
1216 spin_unlock(&up->port.lock);
1217 local_irq_restore(flags);
1218 }
1219
1220 static int __init sunzilog_console_setup(struct console *con, char *options)
1221 {
1222 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1223 unsigned long flags;
1224 int baud, brg;
1225
1226 if (up->port.type != PORT_SUNZILOG)
1227 return -1;
1228
1229 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1230 (sunzilog_reg.minor - 64) + con->index, con->index);
1231
1232 /* Get firmware console settings. */
1233 sunserial_console_termios(con, up->port.dev->of_node);
1234
1235 /* Firmware console speed is limited to 150-->38400 baud so
1236 * this hackish cflag thing is OK.
1237 */
1238 switch (con->cflag & CBAUD) {
1239 case B150: baud = 150; break;
1240 case B300: baud = 300; break;
1241 case B600: baud = 600; break;
1242 case B1200: baud = 1200; break;
1243 case B2400: baud = 2400; break;
1244 case B4800: baud = 4800; break;
1245 default: case B9600: baud = 9600; break;
1246 case B19200: baud = 19200; break;
1247 case B38400: baud = 38400; break;
1248 };
1249
1250 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1251
1252 spin_lock_irqsave(&up->port.lock, flags);
1253
1254 up->curregs[R15] |= BRKIE;
1255 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1256
1257 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1258 __sunzilog_startup(up);
1259
1260 spin_unlock_irqrestore(&up->port.lock, flags);
1261
1262 return 0;
1263 }
1264
1265 static struct console sunzilog_console_ops = {
1266 .name = "ttyS",
1267 .write = sunzilog_console_write,
1268 .device = uart_console_device,
1269 .setup = sunzilog_console_setup,
1270 .flags = CON_PRINTBUFFER,
1271 .index = -1,
1272 .data = &sunzilog_reg,
1273 };
1274
1275 static inline struct console *SUNZILOG_CONSOLE(void)
1276 {
1277 return &sunzilog_console_ops;
1278 }
1279
1280 #else
1281 #define SUNZILOG_CONSOLE() (NULL)
1282 #endif
1283
1284 static void __devinit sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1285 {
1286 int baud, brg;
1287
1288 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1289 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1290 baud = 1200;
1291 } else {
1292 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1293 baud = 4800;
1294 }
1295
1296 up->curregs[R15] |= BRKIE;
1297 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1298 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1299 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1300 __sunzilog_startup(up);
1301 }
1302
1303 #ifdef CONFIG_SERIO
1304 static void __devinit sunzilog_register_serio(struct uart_sunzilog_port *up)
1305 {
1306 struct serio *serio = &up->serio;
1307
1308 serio->port_data = up;
1309
1310 serio->id.type = SERIO_RS232;
1311 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1312 serio->id.proto = SERIO_SUNKBD;
1313 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1314 } else {
1315 serio->id.proto = SERIO_SUN;
1316 serio->id.extra = 1;
1317 strlcpy(serio->name, "zsms", sizeof(serio->name));
1318 }
1319 strlcpy(serio->phys,
1320 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1321 "zs/serio0" : "zs/serio1"),
1322 sizeof(serio->phys));
1323
1324 serio->write = sunzilog_serio_write;
1325 serio->open = sunzilog_serio_open;
1326 serio->close = sunzilog_serio_close;
1327 serio->dev.parent = up->port.dev;
1328
1329 serio_register_port(serio);
1330 }
1331 #endif
1332
1333 static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1334 {
1335 struct zilog_channel __iomem *channel;
1336 unsigned long flags;
1337 int baud, brg;
1338
1339 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1340
1341 spin_lock_irqsave(&up->port.lock, flags);
1342 if (ZS_IS_CHANNEL_A(up)) {
1343 write_zsreg(channel, R9, FHWRES);
1344 ZSDELAY_LONG();
1345 (void) read_zsreg(channel, R0);
1346 }
1347
1348 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1349 SUNZILOG_FLAG_CONS_MOUSE)) {
1350 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1351 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1352 up->curregs[R3] = RxENAB | Rx8;
1353 up->curregs[R5] = TxENAB | Tx8;
1354 up->curregs[R6] = 0x00; /* SDLC Address */
1355 up->curregs[R7] = 0x7E; /* SDLC Flag */
1356 up->curregs[R9] = NV;
1357 up->curregs[R7p] = 0x00;
1358 sunzilog_init_kbdms(up);
1359 /* Only enable interrupts if an ISR handler available */
1360 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1361 up->curregs[R9] |= MIE;
1362 write_zsreg(channel, R9, up->curregs[R9]);
1363 } else {
1364 /* Normal serial TTY. */
1365 up->parity_mask = 0xff;
1366 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1367 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1368 up->curregs[R3] = RxENAB | Rx8;
1369 up->curregs[R5] = TxENAB | Tx8;
1370 up->curregs[R6] = 0x00; /* SDLC Address */
1371 up->curregs[R7] = 0x7E; /* SDLC Flag */
1372 up->curregs[R9] = NV;
1373 up->curregs[R10] = NRZ;
1374 up->curregs[R11] = TCBR | RCBR;
1375 baud = 9600;
1376 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1377 up->curregs[R12] = (brg & 0xff);
1378 up->curregs[R13] = (brg >> 8) & 0xff;
1379 up->curregs[R14] = BRSRC | BRENAB;
1380 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1381 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1382 if (__load_zsregs(channel, up->curregs)) {
1383 up->flags |= SUNZILOG_FLAG_ESCC;
1384 }
1385 /* Only enable interrupts if an ISR handler available */
1386 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1387 up->curregs[R9] |= MIE;
1388 write_zsreg(channel, R9, up->curregs[R9]);
1389 }
1390
1391 spin_unlock_irqrestore(&up->port.lock, flags);
1392
1393 #ifdef CONFIG_SERIO
1394 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1395 SUNZILOG_FLAG_CONS_MOUSE))
1396 sunzilog_register_serio(up);
1397 #endif
1398 }
1399
1400 static int zilog_irq = -1;
1401
1402 static int __devinit zs_probe(struct platform_device *op)
1403 {
1404 static int kbm_inst, uart_inst;
1405 int inst;
1406 struct uart_sunzilog_port *up;
1407 struct zilog_layout __iomem *rp;
1408 int keyboard_mouse = 0;
1409 int err;
1410
1411 if (of_find_property(op->dev.of_node, "keyboard", NULL))
1412 keyboard_mouse = 1;
1413
1414 /* uarts must come before keyboards/mice */
1415 if (keyboard_mouse)
1416 inst = uart_chip_count + kbm_inst;
1417 else
1418 inst = uart_inst;
1419
1420 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1421 sizeof(struct zilog_layout),
1422 "zs");
1423 if (!sunzilog_chip_regs[inst])
1424 return -ENOMEM;
1425
1426 rp = sunzilog_chip_regs[inst];
1427
1428 if (zilog_irq == -1)
1429 zilog_irq = op->archdata.irqs[0];
1430
1431 up = &sunzilog_port_table[inst * 2];
1432
1433 /* Channel A */
1434 up[0].port.mapbase = op->resource[0].start + 0x00;
1435 up[0].port.membase = (void __iomem *) &rp->channelA;
1436 up[0].port.iotype = UPIO_MEM;
1437 up[0].port.irq = op->archdata.irqs[0];
1438 up[0].port.uartclk = ZS_CLOCK;
1439 up[0].port.fifosize = 1;
1440 up[0].port.ops = &sunzilog_pops;
1441 up[0].port.type = PORT_SUNZILOG;
1442 up[0].port.flags = 0;
1443 up[0].port.line = (inst * 2) + 0;
1444 up[0].port.dev = &op->dev;
1445 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1446 if (keyboard_mouse)
1447 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1448 sunzilog_init_hw(&up[0]);
1449
1450 /* Channel B */
1451 up[1].port.mapbase = op->resource[0].start + 0x04;
1452 up[1].port.membase = (void __iomem *) &rp->channelB;
1453 up[1].port.iotype = UPIO_MEM;
1454 up[1].port.irq = op->archdata.irqs[0];
1455 up[1].port.uartclk = ZS_CLOCK;
1456 up[1].port.fifosize = 1;
1457 up[1].port.ops = &sunzilog_pops;
1458 up[1].port.type = PORT_SUNZILOG;
1459 up[1].port.flags = 0;
1460 up[1].port.line = (inst * 2) + 1;
1461 up[1].port.dev = &op->dev;
1462 up[1].flags |= 0;
1463 if (keyboard_mouse)
1464 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1465 sunzilog_init_hw(&up[1]);
1466
1467 if (!keyboard_mouse) {
1468 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1469 &sunzilog_reg, up[0].port.line,
1470 false))
1471 up->flags |= SUNZILOG_FLAG_IS_CONS;
1472 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1473 if (err) {
1474 of_iounmap(&op->resource[0],
1475 rp, sizeof(struct zilog_layout));
1476 return err;
1477 }
1478 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1479 &sunzilog_reg, up[1].port.line,
1480 false))
1481 up->flags |= SUNZILOG_FLAG_IS_CONS;
1482 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1483 if (err) {
1484 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1485 of_iounmap(&op->resource[0],
1486 rp, sizeof(struct zilog_layout));
1487 return err;
1488 }
1489 uart_inst++;
1490 } else {
1491 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1492 "is a %s\n",
1493 dev_name(&op->dev),
1494 (unsigned long long) up[0].port.mapbase,
1495 op->archdata.irqs[0], sunzilog_type(&up[0].port));
1496 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1497 "is a %s\n",
1498 dev_name(&op->dev),
1499 (unsigned long long) up[1].port.mapbase,
1500 op->archdata.irqs[0], sunzilog_type(&up[1].port));
1501 kbm_inst++;
1502 }
1503
1504 dev_set_drvdata(&op->dev, &up[0]);
1505
1506 return 0;
1507 }
1508
1509 static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1510 {
1511 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1512 #ifdef CONFIG_SERIO
1513 serio_unregister_port(&up->serio);
1514 #endif
1515 } else
1516 uart_remove_one_port(&sunzilog_reg, &up->port);
1517 }
1518
1519 static int __devexit zs_remove(struct platform_device *op)
1520 {
1521 struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
1522 struct zilog_layout __iomem *regs;
1523
1524 zs_remove_one(&up[0]);
1525 zs_remove_one(&up[1]);
1526
1527 regs = sunzilog_chip_regs[up[0].port.line / 2];
1528 of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1529
1530 dev_set_drvdata(&op->dev, NULL);
1531
1532 return 0;
1533 }
1534
1535 static const struct of_device_id zs_match[] = {
1536 {
1537 .name = "zs",
1538 },
1539 {},
1540 };
1541 MODULE_DEVICE_TABLE(of, zs_match);
1542
1543 static struct platform_driver zs_driver = {
1544 .driver = {
1545 .name = "zs",
1546 .owner = THIS_MODULE,
1547 .of_match_table = zs_match,
1548 },
1549 .probe = zs_probe,
1550 .remove = __devexit_p(zs_remove),
1551 };
1552
1553 static int __init sunzilog_init(void)
1554 {
1555 struct device_node *dp;
1556 int err;
1557 int num_keybms = 0;
1558 int num_sunzilog = 0;
1559
1560 for_each_node_by_name(dp, "zs") {
1561 num_sunzilog++;
1562 if (of_find_property(dp, "keyboard", NULL))
1563 num_keybms++;
1564 }
1565
1566 if (num_sunzilog) {
1567 err = sunzilog_alloc_tables(num_sunzilog);
1568 if (err)
1569 goto out;
1570
1571 uart_chip_count = num_sunzilog - num_keybms;
1572
1573 err = sunserial_register_minors(&sunzilog_reg,
1574 uart_chip_count * 2);
1575 if (err)
1576 goto out_free_tables;
1577 }
1578
1579 err = platform_driver_register(&zs_driver);
1580 if (err)
1581 goto out_unregister_uart;
1582
1583 if (zilog_irq != -1) {
1584 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1585 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1586 "zs", sunzilog_irq_chain);
1587 if (err)
1588 goto out_unregister_driver;
1589
1590 /* Enable Interrupts */
1591 while (up) {
1592 struct zilog_channel __iomem *channel;
1593
1594 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1595 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1596 up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
1597 up->curregs[R9] |= MIE;
1598 write_zsreg(channel, R9, up->curregs[R9]);
1599 up = up->next;
1600 }
1601 }
1602
1603 out:
1604 return err;
1605
1606 out_unregister_driver:
1607 platform_driver_unregister(&zs_driver);
1608
1609 out_unregister_uart:
1610 if (num_sunzilog) {
1611 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1612 sunzilog_reg.cons = NULL;
1613 }
1614
1615 out_free_tables:
1616 sunzilog_free_tables();
1617 goto out;
1618 }
1619
1620 static void __exit sunzilog_exit(void)
1621 {
1622 platform_driver_unregister(&zs_driver);
1623
1624 if (zilog_irq != -1) {
1625 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1626
1627 /* Disable Interrupts */
1628 while (up) {
1629 struct zilog_channel __iomem *channel;
1630
1631 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1632 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1633 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
1634 up->curregs[R9] &= ~MIE;
1635 write_zsreg(channel, R9, up->curregs[R9]);
1636 up = up->next;
1637 }
1638
1639 free_irq(zilog_irq, sunzilog_irq_chain);
1640 zilog_irq = -1;
1641 }
1642
1643 if (sunzilog_reg.nr) {
1644 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1645 sunzilog_free_tables();
1646 }
1647 }
1648
1649 module_init(sunzilog_init);
1650 module_exit(sunzilog_exit);
1651
1652 MODULE_AUTHOR("David S. Miller");
1653 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1654 MODULE_VERSION("2.0");
1655 MODULE_LICENSE("GPL");